Computer-Aided Design for Integrated Circuits and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 January 2023) | Viewed by 1927

Special Issue Editors


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Guest Editor
Institute of Metrology, Electronics and Computer Science, University of Zielona Góra, 65-417 Zielona Góra, Poland
Interests: logic synthesis; FSM design; FPGA; ASIC; embedded systems; CAD of VLSI-based digital systems
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, 65-417 Zielona Gora, Poland
Interests: logic synthesis; FSM design; FPGA; ASIC; telecommunications; antenna arrays; hardware-software co-design; CAD of VLSI-based digital systems
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
Department of Computer Architecture and Technology, University of Seville, 41012 Sevilla, Spain
Interests: logic synthesis; digital design; embedded systems; hardware implementation of Finite State Machines; reconfigurable computing; FPGA; CAD for digital circuits and systems; optimization; fuzzy systems

Special Issue Information

Dear Colleagues,

Currently, we are witnessing a rapid development of semiconductor technology. As a result of the transition from microelectronics to nanoelectronics, new families of VLSI chips have appeared. The modern integrated circuits and systems consist of billions and billions of semiconductor transistors. Now, a single chip is enough to implement very complex digital and mixed digital-analog systems. The stiff competition between the manufacturers of integrated circuits and VLSI systems guarantees that only the best products come to the market. The enormous complexity of modern circuits and systems requires the use of Computer-Aided Design (CAD) tools that automate the different stages of the design flow. Unfortunately, modern CAD tools cannot effectively use all the potential opportunities provided by current integrated circuits. As before, many problems related to the design process still require active human intervention. Therefore, there is an obvious need to improve the theory and practice in circuit design automation in order to provide solutions to these problems. To sum up, the ever-increasing complexity of current and future industrial projects requires the development of efficient CAD tools that facilitate the implementation of complex integrated circuits and systems.

The aim of this Special Issue is to present novel practical and theoretical approaches related to the CAD of integrated circuits and systems. In particular, methodologies, tools, algorithms, and architectures that allow improving the efficiency of integrated circuits and systems in terms of performance, area occupancy, or power consumption are welcome.

Topics of interest of this Special Issue include, but are not limited to, the following:

  • Theory of Computer-Aided Design;
  • Design methods for reliable and high-efficient (in speed, power consumption or area) integrated circuits and systems;
  • Formal methods for System-Level Design;
  • Energy-efficient integrated circuits and systems;  
  • Design flow for ASICs and programmable devices (FPGAs and CPLDs);
  • Synthesis of synchronous/asynchronous digital systems;
  • Benchmarking in circuit design automation;
  • Design for testability;
  • Design, implementation, and verification of Finite State Machines;
  • Packing and technology mapping;
  • Verification and simulation of digital integrated circuits and systems;
  • HW/SW co-design;
  • Design exploration;
  • CAD for embedded systems;
  • CAD for Cyber-Physical Systems;
  • CAD for networking systems;
  • Reconfigurable computing.

Prof. Dr. Alexander Barkalov
Prof. Dr. Larysa Titarenko
Prof. Dr. Raouf Senhadji-Navarro
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • computer-aided design
  • integrated circuits
  • packing
  • technology mapping
  • logic synthesis
  • testability
  • simulation
  • verification
  • design flow
  • design exploration
  • FPGA-based design
  • ASIC-based design
  • CPLD-based design
  • system-on-a-programmable chip (SOPC)
  • HW/SW co-design
  • low power design

Published Papers (1 paper)

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Research

24 pages, 389 KiB  
Article
Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs
by Alexander Barkalov, Larysa Titarenko and Małgorzata Mazurkiewicz
Electronics 2022, 11(20), 3389; https://doi.org/10.3390/electronics11203389 - 19 Oct 2022
Viewed by 1076
Abstract
A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The [...] Read more.
A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The required chip area is estimated by the number of look-up table (LUT) elements in a particular circuit. The method is based on mutual application of two methods of structural decomposition. The first of them is based on dividing the set of outputs and using unitary-maximum encoding of collections of FSM outputs. The second method is based on dividing the set of states by classes of compatible states. The optimization is achieved by replacing the maximum binary state codes by two-part codes proposed in this article. Each two-part state code consists of a code of a class including a particular state and a maximum binary code of this state inside a particular class. The proposed approach leads to three-level LUT-based Mealy FSM circuits. The first logic level generates three types of partial functions: unitary encoded outputs, variables encoding collections of outputs, and input memory functions. Each partial function is represented by a circuit including a single LUT. The LUTs from the second logic level generate final values of these functions. The LUTs from the third level implement outputs using collections of outputs. An example of synthesis applying the proposed method is discussed. The experiments were conducted using standard benchmark FSMs. Their results showed significant improving of the area occupied by an FSM circuit. The LUT count decreased on average by 9.49%. The positive side effect of the proposed method was increasing the value of the maximum operating frequency (on average, by 8.73%). The proposed method is advisable to use if a single-level LUT-based implementation of the FSM circuit is impossible. Full article
(This article belongs to the Special Issue Computer-Aided Design for Integrated Circuits and Systems)
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