Design of Hardware Accelerators for Deep Learning and Privacy-Preserving Machine Learning

Dear Colleagues,

Deep Learning (DL) models are becoming increasingly complex and computationally demanding, straining traditional hardware. Simultaneously, the rise of privacy regulations and sensitive applications (e.g., healthcare, finance) necessitates robust Privacy-Preserving Machine Learning (PPML) techniques, which themselves impose significant computational overhead. Efficient specialized hardware accelerators are thus crucial to enable the practical deployment of powerful, privacy-conscious AI, especially in resource-constrained edge devices or large-scale cloud servers. This Special Issue thus aims to showcase cutting-edge research on novel hardware architectures and co-design methodologies that enable high-performance, energy-efficient execution of advanced DL models while integrating robust PPML techniques like Homomorphic Encryption (HE), Secure Multi-Party Computation (SMPC), and Trusted Execution Environments (TEEs).

Topics of interests include but not limited to the following:

• DL Hardware Accelerators: Novel architectures (e.g., custom ASICs, FPGAs, NPUs, in-memory computing) targeting CNNs, RNNs, transformers, etc., optimizing for throughput, latency, and energy efficiency.
• Privacy-Preserving ML (PPML) Hardware: Hardware support for cryptographic techniques like Homomorphic Encryption (HE), Secure Multi-Party Computation (SMPC), Differential Privacy (DP), and Trusted Execution Environments (TEEs) to protect sensitive training/inference data.
• Co-Design and Frameworks: Hardware/software co-design approaches, efficient mapping of DL/PPML algorithms to accelerators, and compiler/runtime support for these specialized systems.
• Emerging Technologies: Leveraging emerging memory technologies (ReRAM, PCM), 3D integration, and neuromorphic computing for next-generation acceleration.
• Efficiency and Security: Techniques balancing computational efficiency, energy consumption, and security guarantees within hardware accelerators.

Dr. Rui Wang
Dr. Javad Dogani
Guest Editors

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