CMOS Devices: Design, Applications, and Future Prospects

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Semiconductor Devices".

Deadline for manuscript submissions: closed (15 February 2026) | Viewed by 962

Special Issue Editors


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Guest Editor
Department of Electronic Engineering, Seoul National University of Science and Technology, Seoul 01811, Republic of Korea
Interests: neuromorphic devices; processing in memory devices; steep switching FET; CMOS
Special Issues, Collections and Topics in MDPI journals

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Guest Editor
Department of Electronic and Semiconductor Engineering, Gangneung-Wonju National University, Gangneung 25457, Republic of Korea
Interests: conventional and novel memory devices; neuromorphic systems; ferroelectric materials and devices

Special Issue Information

Dear Colleagues,

Complementary Metal–Oxide–Semiconductor (CMOS) technology has long been the cornerstone of modern electronics, underpinning a vast range of applications from microprocessors and memory devices to sensors and power-efficient systems. The continued scaling of CMOS transistors, aligned with Moore’s Law, has driven unprecedented advances in computational performance, energy efficiency, and miniaturization. However, as we approach the physical and economic limits of traditional CMOS scaling, new challenges and opportunities arise in device design, system integration, and functional diversification. This makes CMOS device research more critical than ever, especially in the context of emerging fields such as artificial intelligence, Internet of Things (IoT), biomedical systems, and quantum computing.

Aim of the Special Issue

The aim of this Special Issue is to provide a comprehensive platform for the latest advancements in CMOS device design, their innovative applications, and emerging directions shaping the future of the field. We welcome original research articles, reviews, and case studies that contribute to the understanding and evolution of CMOS technology. This Special Issue is aligned with the journal’s scope by promoting interdisciplinary research at the interface of materials science, electrical engineering, and system-level integration.

Suggested Themes

  • In memory computing devices;
  • Advanced CMOS transistor design (FinFET, GAAFET, and nanosheet FETs);
  • Steep switching devices for low power;
  • CMOS integration with emerging technologies (e.g., photonics, spintronics, and neuromorphic systems);
  • CMOS sensors for biomedical, environmental, and industrial applications;
  • Reliability, variability, and modeling of nanoscale CMOS devices;
  • Novel materials and processes for next-generation CMOS;
  • Prospects of CMOS beyond Moore’s Law

We look forward to receiving your contributions. 

Dr. Min-Woo Kwon
Dr. Myung-Hyun Baek
Guest Editors

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Keywords

  • advanced CMOS transistor
  • low-power and high-performance CMOS
  • CMOS integration with emerging technologies
  • novel materials for next-generation CMOS beyond Moore’s law
  • FinFET, GAAFET, and nanosheet FETs

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Published Papers (1 paper)

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Research

12 pages, 1846 KB  
Article
Implementation of Boolean Logic Operations and Refresh Circuit for 2T DRAM-Based PIM Architecture
by Yeon-Seok Kim and Min-Woo Kwon
Electronics 2025, 14(22), 4483; https://doi.org/10.3390/electronics14224483 - 17 Nov 2025
Viewed by 743
Abstract
The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed PIM design performs Boolean [...] Read more.
The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed PIM design performs Boolean operations directly within the 2T DRAM array, thereby minimizing data movement between the CPU and DRAM and effectively alleviating the bottleneck. The 2T DRAM array was implemented using the mixed-mode simulation capability of SILVACO TCAD, and its read, write, and hold operations were successfully verified. Building on this foundation, OR and AND logic operations were realized by modulating the gate voltages of MOSFETs within the 2T DRAM array. To enable XNOR functionality, an auxiliary circuit consisting of three additional MOSFETs was integrated. Furthermore, as the ultimate goal of PIM is to enable memory to perform computational tasks, support for MAC operations becomes essential. To facilitate this, we designed a refresh circuit capable of maintaining multi-state data, which is critical for MAC operations. This circuit, also composed of three MOSFETs, functions as a key component for multi-state data retention within the 2T DRAM array. In summary, we demonstrate the implementation of Boolean logic operations using the 2T DRAM array and a three-MOSFET auxiliary circuit and propose a compact refresh circuit to support MAC operations, advancing the potential of PIM architectures. Full article
(This article belongs to the Special Issue CMOS Devices: Design, Applications, and Future Prospects)
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