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Electronics
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Modern Circuits and Systems Technologies (MOCAST 2024)
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Modern Circuits and Systems Technologies (MOCAST 2024)

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 31 May 2025 | Viewed by 6995

Special Issue Editors

Prof. Dr. Valeri Mladenov

E-Mail Website
Guest Editor
Department Fundamentals of Electrical Engineering, Technical University of Sofia, Kliment Ohridski St. 8, 1000 Sofia, Bulgaria
Interests: electrical engineering; electronics; artificial intelligence; neural networks; power systems; applied mathematics; signal processing
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Spyridon Nikolaidis

E-Mail Website
Guest Editor
Physics Department, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece
Interests: digital design; low-power design techniques; applications development on embedded systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The 13th International Conference on Modern Circuit and System Technologies on Electronics and Communications (MOCAST 2024) will be held in Sofia, Bulgaria, from 26 to 28 June 2024. The MOCAST technical program includes all aspects of circuit and system technologies, from modeling to design, verification, implementation, and application. This Special Issue aims to publish extended versions of top-ranking papers at the conference. The topics of MOCAST include the following:

  • Analog/RF and Mixed Signal Circuits;
  • Digital Circuits and Systems Design;
  • Nonlinear Circuits and Systems;
  • Device and Circuit Modeling;
  • High-Performance Embedded Systems;
  • Systems and Applications;
  • Sensors and Systems;
  • Communication Systems;
  • Network Systems;
  • Power Management;
  • Imagers, MEMS, Medical & Displays;
  • Radiation Front Ends (Nuclear and Space Application);
  • Education in Circuits, Systems and Communications.

Please learn more about the conference at http://www.mocast.eu.

Prof. Dr. Valeri Mladenov
Prof. Dr. Spyridon Nikolaidis
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • electronic circuit technologies
  • electronic system technologies
  • modeling, design and implementation of circuits and systems
  • systems and applications

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Related Special Issues

Published Papers (6 papers)

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Research

11 pages, 2022 KiB  
Article
Optimization of CMOS Decoders Using Three-Transistor Logic
by Dimitrios Balobas and Nikos Konofaos
Electronics 2025, 14(5), 914; https://doi.org/10.3390/electronics14050914 - 25 Feb 2025
Viewed by 466
Abstract
Decoders are among the most fundamental components in digital circuit design. They are widely used in combinational logic to convert and route binary data, as well as in memory array logic, for decoding binary addresses that point to the memory locations to be [...] Read more.
Decoders are among the most fundamental components in digital circuit design. They are widely used in combinational logic to convert and route binary data, as well as in memory array logic, for decoding binary addresses that point to the memory locations to be accessed. Due to their extensive utilization, optimizing decoder cells can potentially yield perceivable improvements in a digital system. This paper introduces 3-Transistor Logic (3TL), a new design approach for the optimization of CMOS decoder circuits, which combines static CMOS, Transmission-Gate Logic, and Dual-Value Logic. A complete transistor-level design methodology is demonstrated for decoder sizes from 2×4 up to 8×256, using 15 nm FinFET technology. Furthermore, an extensive comparative analysis is conducted with transistor-level simulations, evaluating the new circuits against conventional static CMOS and other previously proposed designs. The results show that 3TL circuits offer the best overall performance in terms of active power consumption, standby power consumption, and delay, owing largely to the fact that they are designed with logic efficiency and the minimum possible number of transistors. Full article
(This article belongs to the Special Issue Modern Circuits and Systems Technologies (MOCAST 2024))
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24 pages, 3556 KiB  
Article
Designing Approximate Reduced Complexity Wallace Multipliers
by Ioannis Rizos, Georgios Papatheodorou and Aristides Efthymiou
Electronics 2025, 14(2), 333; https://doi.org/10.3390/electronics14020333 - 16 Jan 2025
Viewed by 800
Abstract
In the nano-scale era, enhancing speed while minimizing power consumption and area is a key objective in integrated circuits. This demand has motivated the development of approximate computing, particularly useful in error-tolerant applications such as multimedia, machine learning, signal processing, and scientific computing. [...] Read more.
In the nano-scale era, enhancing speed while minimizing power consumption and area is a key objective in integrated circuits. This demand has motivated the development of approximate computing, particularly useful in error-tolerant applications such as multimedia, machine learning, signal processing, and scientific computing. In this research, we present a novel method to create approximate integer multiplier circuits. This work is based on a modification of the well-known Wallace tree multiplier, called the Reduced Complexity Wallace Multiplier (RCWM). Approximation is introduced by replacing conventional Full Adders with approximate ones during the partial product reduction phase. This research investigates the characteristics of 8×8-, 16×16-, and 32×32-bit Approximate Reduced Complexity Wallace Multipliers (ARCWM), evaluating their accuracy, area usage, delay, and power consumption. Given the vast search space created by different combinations and placements of these approximate Adders, a Genetic Algorithm was used to efficiently explore this space and optimize the ARCWMs. The resulting ARCWMs have an area reduction of up to 65% and a power consumption reduction of up to 70%, with no worse delay than the RCWM. Multipliers created with this method can be used in any application that requires parallel multiplication, such as neural accelerators, trading accuracy for area and power reduction. Additionally, an ARCWM can be used alongside a slow shift-and-accumulate multiplier trading off accuracy for faster calculation. This methodology provides valuable guidance for designers in selecting the optimal configuration of approximate Full Adders, tailored to the specific requirements of their applications. Alongside the methodology, we provide all of the tools used to achieve our results as open-source code, including the Register-Transfer Level (RTL) code of the 8×8-, 16×16-, and 32×32-bit Wallace Multipliers. Full article
(This article belongs to the Special Issue Modern Circuits and Systems Technologies (MOCAST 2024))
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20 pages, 6800 KiB  
Article
Dynamical Investigation of a Modified Cubic Map with a Discrete Memristor Using Microcontrollers
by Lazaros Laskaridis, Christos Volos, Aggelos Emmanouil Giakoumis, Efthymia Meletlidou and Ioannis Stouboulos
Electronics 2025, 14(2), 311; https://doi.org/10.3390/electronics14020311 - 14 Jan 2025
Viewed by 671
Abstract
This study presents a novel approach by implementing an active memristor in a hyperchaotic discrete system, based on a cubic map, which is implemented by using two different microcontrollers. The key contributions of this work are threefold. The use of two microcontrollers with [...] Read more.
This study presents a novel approach by implementing an active memristor in a hyperchaotic discrete system, based on a cubic map, which is implemented by using two different microcontrollers. The key contributions of this work are threefold. The use of two microcontrollers with improved characteristics, such as speed and memory, for faster and more accurate computations significantly improves upon previous systems. Also, for the first time, an active memristor is used in a discrete-time system, which is implemented by using a microcontroller. Furthermore, the system is compared with two different types of microcontrollers regarding the execution time and the quality of the produced bifurcation diagrams. The proposed memristive cubic map uses computationally efficient polynomial functions, which are well suited to microcontroller-based systems, in contrast to more resource-intensive trigonometric and exponential functions. Bifurcation diagrams and a Lyapunov exponent analysis from simulating the system in Mathematica revealed hyperchaotic behavior, along with other significant dynamical phenomena, such as regular orbits, chaotic trajectories, and transitions to chaos through mechanisms like period doubling and crisis phenomena. Experimental verification confirmed the consistency of the results across microcontroller platforms, underscoring the practicality and potential applications of active memristor-based chaotic systems. Full article
(This article belongs to the Special Issue Modern Circuits and Systems Technologies (MOCAST 2024))
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20 pages, 5117 KiB  
Article
Digital LDO Analysis and All-Stable High-PSR One-LSB Oscillator Design
by Utsav Vasudevan and Gabriel A. Rincón-Mora
Electronics 2024, 13(24), 5033; https://doi.org/10.3390/electronics13245033 - 21 Dec 2024
Viewed by 889
Abstract
Digital low-dropout (LDO) regulators are popular in research today as compact power supply solutions. This paper provides a unique approach to analyze digital LDO feedback mechanics and stability, to reduce voltage ripple and extend operating speed over the state-of-the-art. A novel error-subtracting counter [...] Read more.
Digital low-dropout (LDO) regulators are popular in research today as compact power supply solutions. This paper provides a unique approach to analyze digital LDO feedback mechanics and stability, to reduce voltage ripple and extend operating speed over the state-of-the-art. A novel error-subtracting counter is proposed to exponentially improve the response time of any digital LDO, to keep the loop stable outside the typical operating limits, and to increase power-supply rejection (PSR). This leverages the fact that digital LDOs are fundamentally one-bit relaxation oscillators in steady-state. Theory and simulations show how the analog-to-digital (ADC) and digital-to-analog converters (DAC) in these systems affect stability. When compromised, a digital LDO produces uncontrolled sub-clock oscillations at the output that the proposed error-subtracting counter removes. Full article
(This article belongs to the Special Issue Modern Circuits and Systems Technologies (MOCAST 2024))
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18 pages, 604 KiB  
Article
Advancing Quantum Temperature Sensors for Ultra-Precise Measurements (UPMs): A Comparative Study
by Aziz Oukaira, Ouafaa Ettahri and Ahmed Lakhssassi
Electronics 2024, 13(18), 3715; https://doi.org/10.3390/electronics13183715 - 19 Sep 2024
Cited by 1 | Viewed by 2080
Abstract
In this study, we compared the performance of quantum temperature sensors (QTSs) with conventional sensors (CSs), highlighting differences in measurement accuracy and stability. Quantum sensors (QSs), known for their ability to provide ultra-precise measurements (UPMs), were tested across a temperature range of −10 [...] Read more.
In this study, we compared the performance of quantum temperature sensors (QTSs) with conventional sensors (CSs), highlighting differences in measurement accuracy and stability. Quantum sensors (QSs), known for their ability to provide ultra-precise measurements (UPMs), were tested across a temperature range of −10 to 40 °C. The results indicate that QSs offer superior accuracy, with a lower average error and a smaller standard deviation compared to CSs, indicating better measurement stability. For this comparison, we utilized Python scripts to conduct simulations and statistical analyses, leading to precise and reproducible results. The sensor performance was simulated in a controlled environment, and the obtained data were compared with experimental results. This comparison reveals that QSs are more reliable for applications requiring high precision, such as those in the Internet of Things (IoT) domain. These findings underscore the potential advantage of QSs in critical systems where measurement accuracy is paramount. Full article
(This article belongs to the Special Issue Modern Circuits and Systems Technologies (MOCAST 2024))
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11 pages, 803 KiB  
Article
Cost-Efficient Approximation for Magnitude of a Complex Signal
by Chih-Feng Wu and Muh-Tian Shiue
Electronics 2024, 13(13), 2663; https://doi.org/10.3390/electronics13132663 - 7 Jul 2024
Viewed by 929
Abstract
In this paper, a signal model and a mathematical analysis of an efficient approach are derived to acquire the approximate magnitude of a complex signal by inducing a pre-biased or a pre-scaled factor in the design criteria. According to the deductive results, the [...] Read more.
In this paper, a signal model and a mathematical analysis of an efficient approach are derived to acquire the approximate magnitude of a complex signal by inducing a pre-biased or a pre-scaled factor in the design criteria. According to the deductive results, the pre-biased or pre-scaled factor can be 2∼3 dB, which is determined through its application. The numerical evaluations show that the mean square error (MSE) of the proposed efficient approach for the random signal is around −33 dB. Based on the design templates for the considered approaches, the occupied areas of the proposed type-1 and -2 approaches are merely 0.13 and 0.09 times the area of the direct-method, respectively. As a result, the proposed efficient approach is certainly a cost-efficient method for obtaining the approximate magnitude of a complex signal. Full article
(This article belongs to the Special Issue Modern Circuits and Systems Technologies (MOCAST 2024))
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