Special Issue "10th Anniversary of Electronics: Advances in Circuit and Signal Processing"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 December 2021).

Special Issue Editors

Prof. Dr. Paolo Colantonio
E-Mail Website
Guest Editor
Electronic Engineering Department, University of Roma Tor Vergata, 00133 Roma, Italy
Interests: RF and microwave power amplifiers; linear and nonlinear active microwave components, circuits, and subsystems, including MMICs
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Alessandro Cidronali
E-Mail Website
Guest Editor
Department of Information Engineering (DINFO), University of Florence, 50139 Florence, Italy
Interests: design of broadband microwave integrated circuits; CAD modeling for microwave devices and circuits
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

It has now been ten years since the first paper was published in Electronics back in 2011. It has been a rocky road with many highs and many lows, but we are extremely proud to have reached this very important milestone of the 10th anniversary of the journal. To celebrate this momentous occasion, a Special Issue is being prepared which invites both members of the Editorial Board and outstanding renowned authors, including past editors and authors, to submit their high-quality works on the topic of “Circuit and Signal Processing”.

Topics of interest include but are not limited to:

  • Analog and digital integrated circuits and systems
  • Nonlinear circuits and systems
  • Signal processing theory and methods
  • Analog signal processing
  • Acoustic, bio, image circuit, and signal processing
  • Nanoelectronics and cellular networks
  • Multimedia systems and signal processing
  • Power and energy circuits and systems
  • Machine learning for signal processing
  • Circuits, systems, and signal processing for communication and networking

Prof. Dr. Paolo Colantonio
Prof. Dr. Alessandro Cidronali
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (13 papers)

Order results
Result details
Select all
Export citation of selected articles as:

Research

Jump to: Review, Other

Article
Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems
Electronics 2022, 11(3), 328; https://doi.org/10.3390/electronics11030328 - 21 Jan 2022
Viewed by 227
Abstract
A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband [...] Read more.
A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage. Full article
Show Figures

Figure 1

Article
Adaptive Noise-Resistant Low-Power ASK Demodulator Design in UHF RFID Chips
Electronics 2021, 10(24), 3168; https://doi.org/10.3390/electronics10243168 - 20 Dec 2021
Viewed by 397
Abstract
This paper presents a new signal demodulator for ultra-high frequency (UHF) radio frequency identification (RFID) tag chips. The demodulator is used to demodulate amplitude shift keying (ASK) modulated signals with the advantages of high noise immunity, large input range and low power consumption. [...] Read more.
This paper presents a new signal demodulator for ultra-high frequency (UHF) radio frequency identification (RFID) tag chips. The demodulator is used to demodulate amplitude shift keying (ASK) modulated signals with the advantages of high noise immunity, large input range and low power consumption. The demodulator consists of a charge pump, an envelope detector, and a comparator. In particular, the demodulator provides a hysteresis input signal to the comparator through two envelope detectors, resulting in better noise immunity. The demodulator is based on a standard 0.13 µm CMOS process. The demodulator is suitable for demodulating high frequency signals at 900 MHz with a data rate of 128 Kbps and can operate up to 78 °C. The input signal has a peak of 1.2 V and consumes as little as 113.6 nW. The demodulator also has a noise immunity threshold of approximately 3.729 V. Full article
Show Figures

Figure 1

Article
S Band Hybrid Power Amplifier in GaN Technology with Input/Output Multi Harmonic Tuned Terminations
Electronics 2021, 10(18), 2318; https://doi.org/10.3390/electronics10182318 - 21 Sep 2021
Cited by 2 | Viewed by 538
Abstract
In this paper, the design, fabrication, and measurements of an S band multi harmonic tuned power amplifier in GaN technology is described. The amplifier has been designed by exploiting second and third harmonic tuning conditions at both input and output ports of the [...] Read more.
In this paper, the design, fabrication, and measurements of an S band multi harmonic tuned power amplifier in GaN technology is described. The amplifier has been designed by exploiting second and third harmonic tuning conditions at both input and output ports of the active device. The amplifier has been realized in a hybrid form, and characterized in terms of small and large signal performance. An operating bandwidth of 300 MHz around 3.55 GHz, with 42.3 dBm output power, 9.3 dB power gain and 53.5% power added efficiency PAE (60% drain efficiency) at 3.7 GHz are measured. Full article
Show Figures

Figure 1

Article
Towards Realization of a Low-Voltage Class-AB VCII with High Current Drive Capability
Electronics 2021, 10(18), 2303; https://doi.org/10.3390/electronics10182303 - 18 Sep 2021
Cited by 1 | Viewed by 651
Abstract
In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to [...] Read more.
In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 µm CMOS technology parameters and a supply voltage of ±0.9 V. The small signal impedance values were 973 Ω, 120 kΩ and 217 Ω at Y, X and Z ports, respectively. The maximum current at the X port was ±10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (IB) of 29 µA and output current at the X port (IX) of 10 mA, the current drive capability (IX/IB) of about 345 was achieved at the X port. The voltage swing at the Z port was (−0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 µW. Full article
Show Figures

Figure 1

Article
A Novel TDoA-Based Method for 3D Combined Localization Techniques Using an Ultra-Wideband Phase Wrapping-Impaired Switched Beam Antenna
Electronics 2021, 10(17), 2137; https://doi.org/10.3390/electronics10172137 - 02 Sep 2021
Viewed by 473
Abstract
This paper presents a novel Time Difference of Arrival-based approach suitable for single-anchor positioning systems, implemented by phase wrapping-impaired array antenna. With the latter being a typical occurrence in large Switched Beam Antenna (SBA) operating in the low microwave range. The proposed method [...] Read more.
This paper presents a novel Time Difference of Arrival-based approach suitable for single-anchor positioning systems, implemented by phase wrapping-impaired array antenna. With the latter being a typical occurrence in large Switched Beam Antenna (SBA) operating in the low microwave range. The proposed method takes advantage from the large bandwidth of radio link, established between the anchor and the positioning target, by generating an unambiguous equivalent phase relationship between antenna array elements. The technique is validated by adopting a relatively large SBA antenna operating in the 4.75–6.25 GHz bandwidth, and capable to position a target in a 3D domain. Experimental data, carried out in the 4–7 GHz frequency bandwidth, show that by dealing properly with the inherent constraint of phase wrapping issues, it is possible to get a significant improvement on the elevation angle with respect to methods not capable to deal with phase reconstruction and thus operating in a phase-less context. Combining range and angle errors, the associated cumulative distribution function error in 90% of cases shows an error of 0.13 m. Full article
Show Figures

Figure 1

Article
A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications
Electronics 2021, 10(17), 2108; https://doi.org/10.3390/electronics10172108 - 30 Aug 2021
Cited by 1 | Viewed by 438
Abstract
This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery [...] Read more.
This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off. Full article
Show Figures

Figure 1

Article
Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations
Electronics 2021, 10(15), 1784; https://doi.org/10.3390/electronics10151784 - 26 Jul 2021
Cited by 1 | Viewed by 515
Abstract
The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium [...] Read more.
The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium nitride technology, which already offers high breakdown voltages. Indeed, the stacked topology can also be advantageous in such scenarios as it can enhance gain and chip compactness. Moreover, the higher supply voltages and lower supply currents beneficially impact on reliability, thus making the stacked configuration an attractive solution for space applications. This paper details the design of two stacked cells, differing in their inter-stage matching strategy, conceived for space applications at Ka-band in 100 nm GaN-on-Si technology. In particular, the design challenges related to the thermal constraints posed by space reliability and to the electro-magnetic cross-talk issues that may arise at millimeter-wave frequencies are discussed. The best cell achieves at saturation, in simulation, 3 W of output power at 36 GHz with associated gain and efficiency in excess of 7 dB and 35%, respectively. Full article
Show Figures

Figure 1

Article
Time-Variant Front-End Read-Out Electronics for High-Data-Rate Detectors
Electronics 2021, 10(13), 1528; https://doi.org/10.3390/electronics10131528 - 24 Jun 2021
Viewed by 337
Abstract
The foreseen incremental luminosity for near-future high-energy physics experiments demands evolution for the read-out electronics in terms of event data-rate. However, the filtering necessary to reject noise and meet the signal-to-noise-ratio requirements imposes a restriction on the operational speed of the conventional read-out [...] Read more.
The foreseen incremental luminosity for near-future high-energy physics experiments demands evolution for the read-out electronics in terms of event data-rate. However, the filtering necessary to reject noise and meet the signal-to-noise-ratio requirements imposes a restriction on the operational speed of the conventional read-out electronics. The stringent trade-off between signal-to-noise-ratio and the event data-rate originates from the time-invariant behavior of the conventional systems. In this paper, the cases of time-variant systems are addressed, studying a benchmark with the RC-CR shaping function used in time-over-threshold methods. It was demonstrated that the time-variant systems enable a higher data-rate for the given noise performance. Moreover, taking advantage of time-variant systems, the proposed rising-edge method enables further data-rate enhancement with respect to the traditional time-over-threshold technique by reading the data from the rising edge of the analog output waveform. A comparison between the conventional time-invariant time-over-threshold technique, its time-variant equivalent and rising-edge method confirms the better performance of the latter one in terms of data-rate enhancement for a target noise performance. Moreover, design challenges for time-variant systems are briefly discussed, considering the ATLAS Monitored Drift Tube detector as a design case. Full article
Show Figures

Figure 1

Article
Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers
Electronics 2021, 10(9), 991; https://doi.org/10.3390/electronics10090991 - 21 Apr 2021
Viewed by 658
Abstract
Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, [...] Read more.
Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case. Full article
Show Figures

Figure 1

Article
Circuit Model and Analysis of Molded Case Circuit Breaker Interruption Phenomenon
Electronics 2020, 9(12), 2047; https://doi.org/10.3390/electronics9122047 - 02 Dec 2020
Cited by 1 | Viewed by 631
Abstract
There are complex physical phenomena for the interpretation of a molded case circuit breaker (MCCB) in a distribution system. Most of the studies of MCCB interruption phenomena were conducted with numerical analysis and experiments. This traditional approach may help improve the performance of [...] Read more.
There are complex physical phenomena for the interpretation of a molded case circuit breaker (MCCB) in a distribution system. Most of the studies of MCCB interruption phenomena were conducted with numerical analysis and experiments. This traditional approach may help improve the performance of the MCCB itself, but it is difficult to find connectivity with other systems. In this paper, the circuit model is proposed and the interruption phenomenon of MCCB is analyzed. The interruption of the MCCB is divided into three sections to deal with physical phenomena occurring in each area. A simplified model is proposed considering the characteristics of each section. Based on this model, the circuit model is proposed. To implement the features of each section, the calculation of physical phenomena is carried out, and this is expressed in the circuit model with resistance and zener diode. Comparing the results of the simulation with the experimental results is as follows. For 7-plates (basic state), the error rate is −5.6% in section II and 16.8% in section III. For 1-plate, the error rate is 36.5% in section II and −17.0% in section III. This case shows much difference from the simplified model in this paper, resulting in the largest error rate. The 7-plates and 5-plates cases, which are available in the general MCCB owing to the shortest distance from the arc, represent a relatively small error rate. Using the proposed circuit model, it is expected that the entire system, including the interruption phenomenon, can be interpreted as a single circuit model. Full article
Show Figures

Figure 1

Review

Jump to: Research, Other

Review
Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops
Electronics 2021, 10(13), 1572; https://doi.org/10.3390/electronics10131572 - 30 Jun 2021
Viewed by 493
Abstract
In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD [...] Read more.
In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design. Full article
Show Figures

Figure 1

Review
Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review
Electronics 2021, 10(10), 1174; https://doi.org/10.3390/electronics10101174 - 14 May 2021
Viewed by 501
Abstract
The review is devoted to methods of structural decomposition that are used for optimizing characteristics of circuits of finite state machines (FSMs). These methods are connected with the increasing the number of logic levels in resulting FSM circuits. They can be viewed as [...] Read more.
The review is devoted to methods of structural decomposition that are used for optimizing characteristics of circuits of finite state machines (FSMs). These methods are connected with the increasing the number of logic levels in resulting FSM circuits. They can be viewed as an alternative to methods of functional decompositions. The roots of these methods are analysed. It is shown that the first methods of structural decomposition have appeared in 1950s together with microprogram control units. The basic methods of structural decomposition are analysed. They are such methods as the replacement of FSM inputs, encoding collections of FSM outputs, and encoding of terms. It is shown that these methods can be used for any element basis. Additionally, the joint application of different methods is shown. The analysis of change in these methods related to the evolution of the logic elements is performed. The application of these methods for optimizing FPGA- based FSMs is shown. Such new methods as twofold state assignment and mixed encoding of outputs are analysed. Some methods are illustrated with examples of FSM synthesis. Additionally, some experimental results are represented. These results prove that the methods of structural decomposition really improve the characteristics of FSM circuits. Full article
Show Figures

Figure 1

Other

Jump to: Research, Review

Case Report
Experimental Study on Splitter Plate for Improving the Dielectric Recovery Strength of Low-Voltage Circuit Breaker
Electronics 2020, 9(12), 2148; https://doi.org/10.3390/electronics9122148 - 15 Dec 2020
Cited by 1 | Viewed by 559
Abstract
The low-voltage circuit breakers are widely used to protect loads in the distribution system. Interruption reliability of circuit breakers is important because they are a protective device close to the customer. In particular, the re-ignition phenomenon leads to over-current blocking failure due to [...] Read more.
The low-voltage circuit breakers are widely used to protect loads in the distribution system. Interruption reliability of circuit breakers is important because they are a protective device close to the customer. In particular, the re-ignition phenomenon leads to over-current blocking failure due to the arc re-formed between electrodes despite the normal trip of the circuit breaker. In this paper, in order to improve the interruption performance against re-ignition, the dielectric recovery voltage measurement system of the circuit breaker is used and the experiment of changing the splitter plate is carried out. Two experiments are carried out by changing the splitter plate, especially changing the material of splitter plate and the number of lower plates of the splitter plate. In the case of changing the material of the splitter plate, the analysis is conducted according to the thermal conductance. In the case of changing the number of lower plates of the splitter plate, the number of plates and their spacing are variables. Analyzing the results of the dielectric recovery voltage experiment, in the initial period, copper plates have the best value that shows 102.1% improvement compared to normal and Al shows 59.8% improvement compared to normal. These increases are related to the thermal conductivity of the three electrode materials. In the case of changing the number of lower plates of the splitter plate, the 8-plates and 9-plates show 84.5% and 36.1% increases compared to normal, respectively, in the initial period. It can be seen that too many plates interfere with heat dissipation. Since this study studies performance improvement during the initial period, there is not much difference in the later period. This is consistent with the experimental results. In this study, an experimental basis is provided for the dielectric recovery strength from a low-voltage circuit breaker. It is expected that this will contribute to the research to improve the dielectric recovery capability of the circuit breaker. Full article
Show Figures

Figure 1

Back to TopTop