Implementation of 2-Bit Channel Quantization for the STT-MRAM with Low-Reading-Margin MTJ

Abstract

As the process node is scaled down, the spin-transfer-torque magnetic random-access memory (STT-MRAM) exhibits higher memory density than the static random-access memory (SRAM), making it one of the more promising successors of the low-level on-chip cache memory. However, the low read margin (RM) of the magnetic tunnel junction (MTJ) in STT-MRAM can limit the achievable read accuracy. We implemented 2-bit channel quantization for error-correcting code (ECC) schemes and explored the trade-offs between improved read accuracy and factors such as circuit area, power consumption, and latency. The proposed quantization scheme consists of a sensing amplifier-based 2-bit quantizer and MTJ resistor-based soft-decision thresholds. Compared to 1-bit channel quantization using the Bose–Chaudhuri–Hocquenghem (BCH) code, the proposed 2-bit quantization architecture achieves a fourfold reduction in frame error rate (FER) from $8.0\times {10}^{-4}$ to $2.0\times {10}^{-4}$ when paired with polar codes and successive cancellation (SC) decoding. Additionally, this approach results in decoding complexity that is only 1/13th of that required for BCH at a 0.7 code rate.

1. Introduction

As complementary metal–oxide–semiconductor (CMOS) technology scales into the few-nanometer regime, the conventional six-transistor (6T) static random-access memory (SRAM) cell is widely regarded as increasingly area-limited for high-density on-chip cache, largely because the bitcell footprint does not scale as efficiently as logic with advanced design-rule constraints [1]. Meanwhile, spin-transfer-torque magnetic random-access memory (STT-MRAM) has been extensively studied as an embedded memory option that can provide competitive density and near-zero standby leakage compared with SRAM, making it attractive for energy-constrained cache-like applications [2,3]. Leading semiconductor companies have already demonstrated embedded STT-MRAM on 40/28/22 $\mathrm{nm}$ CMOS nodes [4], further validating its potential for commercial adoption.

Within the cell, STT-MRAM uses a magnetic tunnel junction (MTJ) resistor to store one-bit binary data. The MTJ can be in a parallel state with a resistance of $R_{MTJ}=R_P$ or in an antiparallel state with $R_{MTJ}=R_{AP}$. The tunneling magnetoresistance (TMR) of the MTJ represents the relative difference between its high- and low-resistance states and is defined as $TMR=({\mu }_1-{\mu }_0)/{\mu }_0$, where the average resistance in the high-resistance state is ${\mu }_1$ = $R_{AP}$ and in the low-resistance state is ${\mu }_0$ = $R_P$ [5]. Despite increased density, the reading accuracy of STT-MRAM decreases as the MTJ size is reduced with smaller process nodes, leading to a reduction in TMR, as shown in Figure 1a [6,7,8,9,10,11,12,13,14,15,16,17,18,19,20].

Figure 1. (a) The TMR reduces as the diameter of the MTJ decreases for both discrete MTJ devices and the MTJ in a large array, adapted from [6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. (b) The conventional SA-based 1-bit channel quantization. (c) Multi-bit channel quantization using soft-decision thresholds. (d) The proposed 2-bit channel quantization circuits using MTJ resistor-based thresholds.

STT-MRAM can be described by a combined binary asymmetric channel and asymmetric Gaussian channel (BAC-AGC) model, as shown in Figure 1b–d [21]. The variations caused by process, voltage, temperature (PVT), and other environmental noise affect the distribution of MTJ resistance. The asymmetric Gaussian channel (AGC) can describe the resistance states of MTJ as both follow a Gaussian distribution, as shown in Figure 2d [21,22]. Let ${\sigma }_0$ and ${\sigma }_1$ denote the standard deviations of the two resistance states. As the MTJ scales down, both ${\sigma }_0$ and ${\sigma }_1$ increase, with reported deviations ${\sigma }_0/{\mu }_0,{\sigma }_1/{\mu }_1$ ranging from 5 to 27% [10,23,24].

Figure 2. The diagrams of the (a) conventional SA-based 1-bit quantizer and (b) proposed SA-based 2-bit quantizers. (c) The flow chart of 2-bit channel quantization. The RM of the AGC model changes when using (d) 1-bit or (e,f) 2-bit channel quantization. AGC: Asymmetric Gaussian channel.

To read the MTJ data cells, a sense amplifier (SA) functions as a 1-bit quantizer, executing 1-bit channel quantization in conjunction with the hard decision threshold $a_2$, which is provided by the MTJ reference cell, as shown in Figure 2a. The reading margin (RM) of STT-MRAM is calculated as $min[{\displaystyle \frac{{\mu }_1-a_2}{{\sigma }_1}},{\displaystyle \frac{a_2-{\mu }_0}{{\sigma }_0}}]$ [25]. As TMR decreases, RM will also decrease. Figure 3a shows that the temperature-dependent TMR reduces by 39%. An RM of 6 is reported to be required for a 32 Mb memory array to obtain a read yield of 96.74% [25]. A low RM (<3) not only elevates the bit error rate (BER) to 0.27% but also threatens cache coherence in multi-core systems. For instance, frequent read errors may propagate corrupted data to lower cache hierarchies, triggering silent data corruption or even system-level failures due to inconsistent cache states [26]. Additionally, because the MTJs in the reference cells are the same as those in the data cells, $a_2$ also experiences fluctuations in variance $\sigma$. As shown in Figure 2d, this variance further reduces the RM. It indicates that when the process node scales down, STT-MRAM achieves increased array density but suffers from a decline in read accuracy.

Figure 3. (a) Normalized low-resistance value $R_P$ of the MTJ devices with $TMR$ = 88% @ 27 °C, ${\sigma }_0/{\mu }_0=10\%$. The normalized ideal thresholds $T{h}_{\mathsf{\Omega }}=(a_1,a_2,a_3)$ and the seven candidate thresholds ($a_1^{\prime }$∼$a_7^{\prime }$) as functions of the TMR as well as the temperature. The normalized $R_P$, $R_{AP}$ are also plotted. $T{h}_A=(a_1^{\prime },a_2^{\prime },a_3^{\prime })$ for quantizer A; $T{h}_B=(a_1^{\prime \prime },a_2^{\prime },a_3^{\prime \prime })$ for quantizer B. (b) The candidate thresholds $a_1^{\prime }$∼$a_7^{\prime }$ are determined by the MTJ resistor networks with either $R_P$ or $R_{AP}$.

Recent embedded STT-MRAM demonstrations for SRAM-like working-memory applications show that retention can be intentionally relaxed to trade for faster writing and higher endurance, while system-level mitigation is used to bound the resulting time-accumulated errors [27]. Specifically, a built-in read–modify–write scrubbing controller periodically reads the array, checks latent errors with an on-chip error-correcting code (ECC), and rewrites corrected data such that the accumulated errors stay within the ECC correction capability [27]. Under accelerated stress and conservative extrapolation models, the measured write endurance can exceed ${10}^{12}$ cycles, substantially higher than NVM-oriented STT-MRAM targets [27]. These results further motivate improving read reliability under a reduced sensing margin, as a lower raw read error rate directly reduces ECC burden and the frequency and overhead of corrective actions such as scrubbing.

This presents an opportunity to implement multi-bit channel quantization and comprehensive ECC schemes to enhance the overall read accuracy of STT-MRAM [21,22], such as fixed-code ECC [6,22,28,29] and adaptive ECC schemes [30,31]. The low-level cache applications require dual- or triple-error correction (TEC) ECC instead of the single-error correction (SEC) code for the commercial standalone STT-MRAM [6,30]. When using SA as a 1-bit quantizer, it was found that the Bose–Chaudhuri–Hocquenghem (BCH) code can significantly enhance read accuracy [29,31].

For the MTJ channel, using non-uniform multi-bit quantization can significantly improve the signal-to-noise ratio (SNR) [21]. In combination with low-density parity-check (LDPC) and polar codes, multi-bit quantization can reduce the read error rate by 1∼2 orders of magnitude compared to the SEC schemes when RM is low, as shown in Figure 1c [22,28,29]. However, algorithms like dynamic programming are still needed to find the best soft-decision thresholds [32], and multi-bit channel quantization has not been implemented in circuitry.

In this paper, we implemented 2-bit channel quantization circuits for ECC to enhance the read accuracy of STT-MRAM with low-RM MTJ by integrating an SA-based 2-bit quantizer with the MTJ resistor-based (R-based) soft-decision thresholds, as shown in Figure 1d. We compared the proposed 2-bit quantizers in terms of area, power consumption, latency, and overall read accuracy. We introduce a self-generated and adaptive threshold implementation based on an MTJ–resistor network. In this approach, non-uniform soft-decision thresholds are synthesized directly from compact combinations of $R_P$ and $R_{AP}$, eliminating the need for look-up table (LUT)-programmed threshold sets or auxiliary digital-to-analog converters (DACs). The matched resistor–MTJ structure inherently tracks resistance variations under PVT and device drift, removing the requirement for explicit PVT sensing and control logic. Additionally, a full-margin SA is employed to enhance the second-bit decision margin under low read-margin conditions. Moreover, we investigated the performance of various ECC schemes using the proposed non-uniform 2-bit quantization for the STT-MRAM with low RM. This paper is organized as follows. Section 2 introduces a modified cascaded BAC–AGC channel model that accounts for PVT-induced variations. Section 3 details the circuit implementation of the proposed 2-bit channel quantization, including the MTJ–resistor soft-decision thresholds and quantizer architectures. Section 4 assesses the ECC performance under different code rates and decoding algorithms with the proposed 2-bit quantization. Section 5 concludes the paper.

2. Modified Cascaded BAC–AGC Channel Model for STT-MRAM Under PVT-Induced Variations

In the STT-MRAM, the PVT-induced fluctuations broaden the resistance distribution and reduce the TMR of the MTJs, which prevents the sensing circuitry from achieving sufficient read yield. The overall error increase arises from the write errors, the read disturb errors, and the read decision errors [21]. Since the in-cell MTJ switching events are asymmetric and independent of each other [33], the transfer functions of the STT-MRAM induced by the write error can be described by a binary asymmetric channel (BAC). Successively, the single direction miswriting leads to the read disturb error, which is similar to the write error and can be described by the BAC. Moreover, as the reading and writing circuits share the same paths in the memory array, the read disturb error rate of $P_{r0}$ can be described by the Z channel model which can be combined into the BAC model [21]. When the reading current is set to the write-0 ($1\to 0$) direction, the crossover probability of the BAC can be written as [33]

$$\begin{array}{cc}\hfill p_0& ={\displaystyle \frac{P_0}{2}}\left(1-P_{r0}\right),q_0=\left(1-{\displaystyle \frac{P_0}{2}}\right)+{\displaystyle \frac{P_0}{2}}{P}_{r0},\hfill \\ \hfill p_1& ={\displaystyle \frac{P_1}{2}}+\left(1-{\displaystyle \frac{P_1}{2}}\right)P_{r0},q_1=\left(1-{\displaystyle \frac{P_1}{2}}\right)\left(1-P_{r0}\right).\hfill \end{array}$$

(1)

where $p_j$,$q_j$, and $P_j$, $j=0,1$, are the error rate, the correct rate, and the write error rate for transmitting $0\to 1$ and $1\to 0$, respectively. When assuming a switching probability of 50%, the crossover probabilities of BAC are $P_0/2$ for $0\to 1$ and $P_1/2$ for $1\to 0$.

Let x denote the input of the BAC, which is always $x\in \{0,1\}$. The output y is quantized as $n=2^q$ outputs ${\widehat{y}}_0,{\widehat{y}}_1,\dots ,{\widehat{y}}_{n-1}$ by a q-bit quantizer. Let $a_0,a_1,\dots ,a_n$ denote the boundaries of the quantization interval, where $a_0=-\infty$, $a_n=+\infty$. $T_j=(a_j,a_{j+1})$ denotes the j-th quantization interval, $j=0,1,\dots ,n-1$ [21].

In the BAC, we can define the averaged resistances of the low-resistance state ($R_P$) and the high-resistance state ($R_{AP}$) of the MTJ as ${\mu }_0=R_P$ and ${\mu }_1=R_{AP}$, respectively. As the resistance distributions of both states follow the Gaussian distribution [21], we use ${\sigma }_0$ and ${\sigma }_1$ to denote the variations in two resistance states which are caused by process-induced tunneling oxide thickness ($t_{ox}$) fluctuations of the MTJ. When the pitch size of the MTJ reduces, the resistance distribution broadens, which makes the ${\sigma }_0$ and ${\sigma }_1$ increase simultaneously [21,25]. In this case, the assumption of ${\sigma }_0/{\mu }_0\approx {\sigma }_1/{\mu }_1$ is feasible as well [21].

In the STT-MRAM, the SAs are used as the 1-bit quantizer and the decision threshold is given by the reference cell resistances, dividing the reading margin into two intervals. The read decision errors induced by the sensing circuitry can be modeled as an asymmetric Gaussian channel (AGC), the transfer probability of which can be cascaded after BAC, which yields [21]

$$P_r({\widehat{y}}_j\mid \widehat{x}=i)=Q\left({\displaystyle \frac{a_j-{\mu }_i}{{\sigma }_i}}\right)-Q\left({\displaystyle \frac{a_{j+1}-{\mu }_i}{{\sigma }_i}}\right)$$

(2)

with $i=0,1$, where $Q(·)$ is the right tail probability of the normal distribution. As the read decision error depends on the read accuracy of the SA, the variances in the read errors of different SA solutions can differ as much as 2.4 times [25]. Therefore, based on (1) and (2), the transfer probabilities of the cascade BAC-AGC channel can be modified as

$$\begin{array}{ccc}\hfill W({\widehat{y}}_j\mid \widehat{x}=0)& =& \left[q_0{P}_r({\widehat{y}}_j\mid \widehat{x}=0)+p_0{P}_r({\widehat{y}}_j\mid \widehat{x}=1)\right]P_{Q0},\hfill \\ \hfill W({\widehat{y}}_j\mid \widehat{x}=1)& =& \left[p_1{P}_r({\widehat{y}}_j\mid \widehat{x}=0)+q_1{P}_r({\widehat{y}}_j\mid \widehat{x}=1)\right]P_{Q1},\hfill \end{array}$$

(3)

where $W\left({\widehat{y}}_j\right|\widehat{x}=i),P_{Qi}$ are the channel transfer probabilities of the modified BAC-AGC channel and the read accuracy of the quantizer. $p_j$ and $q_j$, $j=0,1$ represent the error rate for the transmission from 0 to 1 and from 1 to 0 and the correct rate for the transmission from 0 to 0 and from 1 to 1.

3. Circuit Implementation of 2-Bit Channel Quantization Using MTJ–Resistor Soft Thresholds

The proposed 2-bit quantization implementation consists of R-based soft-decision thresholds and a 2-bit quantizer, as shown in Figure 1d.

3.1. MTJ–Resistor Network for Self-Adaptive Soft-Decision Threshold Generation

STT-MRAM requires non-uniform multi-bit quantization and adaptive thresholds to account for PVT variations. In channel quantization, the RM can be improved by using the optimal soft-decision thresholds. Current multi-bit quantization uses search algorithms to identify the optimal set that meets criteria such as maximizing the cutoff rate (MCR) [21]. Although the optimal thresholds can be implemented using a predetermined lookup table, they may require PVT sensing modules, additional control logic, and sets of reference cells. We propose using selected MTJ resistor networks to directly establish the soft-decision thresholds. The R-based thresholds are inherently non-uniformly quantized and self-adaptive to PVT changes, which enhances the compactness and power efficiency of the threshold generation circuits.

The seven possible resistor networks for the proposed 2-bit quantizer are $a_1^{\prime }=(R_P\Vert R_{AP})+(R_P\Vert R_{AP}\Vert R_{AP}), a_2^{\prime }=2(R_P\Vert R_{AP}), a_3^{\prime }=R_P+(R_P\Vert R_{AP}\Vert R_{AP}), a_4^{\prime }=(R_P+R_{AP})\Vert (R_P+R_{AP}), a_5^{\prime }=R_P+(R_P\Vert R_P\Vert R_{AP}), a_6^{\prime }=(R_P\Vert R_{AP})+R_{AP}/3$, and $a_7^{\prime }=R_{AP}/3+R_{AP}/3$. Figure 3b shows the layouts of the candidate resistor networks. To determine whether these candidate thresholds can sit close to the optimal ones in the low-TMR cases, we calculate their MCR $R_0$ in the BAC-AGC [21,22]. Then, the best candidate threshold sets can be determined when their $R_0$$I_q$ is closest to the predetermined MCR as provided by the dynamic programming algorithm [21]. Embedded STT-MRAM is designed for over 10-year retention and ${10}^{15}$-cycle endurance [34]; under such specifications, long-term drift of $R_P$ and $R_{AP}$ is negligible.

In particular, for a 2-bit quantization channel with binary input, a set of $2^2-1$ soft-decision thresholds is required. Assuming the write error rates $P_0=2\times {10}^{-6}$ and $P_1=2\times {10}^{-4}$, $TMR=88\%@27$ °C when the MTJ diameter is <40 $\mathrm{nm}$ [13], and ${\sigma }_0/{\mu }_0=10\%$ for the 28 $\mathrm{nm}$ process [23]. We first determined $R_0$ of the optimal thresholds $T{h}_{\mathsf{\Omega }}=(a_1,a_2,a_3)$ while keeping the initial conditions fixed. Secondly, for each candidate threshold ($a_1^{\prime }$∼$a_7^{\prime }$), their overall difference to $T{h}_{\mathsf{\Omega }}$ over the $K=8$ points in the range of $TMR=76$∼$106\%$ can be written as ${\Delta }_{ij}=\sqrt{{\sum }_{k=1}^K{(a_i^{\prime }-a_j)}^2}/\left(R_{P}K\right)$. Once the ith candidate threshold has the minimum ${\Delta }_{ij}$ to $a_j$, we can use the $a_i^{\prime }$ to replace the latter. Therefore, we can use the threshold set $T{h}_A=(a_1^{\prime },a_2^{\prime },a_3^{\prime })$ with ${\Delta }_{11}=1.423\%$, ${\Delta }_{22}=0.146\%$, and ${\Delta }_{33}=1.137\%$ to replace $T{h}_{\mathsf{\Omega }}$. As shown in Figure 3a, these R-based thresholds can self-adjust to match the optimal thresholds when RM decreases.

3.2. Read-Margin Expansion via Full-Margin Sense Amplifier for the Second-Bit Decision

Figure 2e shows the 2-bit channel quantization for BAC-AGC using $T{h}_A$, which can be used by 2-bit quantizer A or an analog-to-digital converter (ADC) circuit. For 2-bit quantizer A, when the first digit is “0”, the RM for the second digit quantization becomes $R{M}_A\approx min[a_2^{\prime }-a_1^{\prime },a_1^{\prime }-{\mu }_0]/{\sigma }_0$. For ${\sigma }_0/{\mu }_0=10\%$, $R{M}_A=1.34$, which is lower than 3, the lower limit for ECC decoding. To broaden the RM for the second digit quantization, we propose using the full-margin SA as the quantizer [35], denoted as 2-bit quantizer B. As shown in Figure 2f, the thresholds for quantizer B are $T{h}_B=(a_1^{\prime \prime },a_2^{\prime },a_3^{\prime \prime })$. In this case, the thresholds of quantizer B become $a_1^{\prime \prime }=(R_P+a_2^{\prime })/2$ and $a_3^{\prime \prime }=(R_{AP}+a_2^{\prime })/2$ instead of $a_1^{\prime }$ and $a_3^{\prime }$. This expands the RM for the second digit quantization, which becomes $R{M}_B=(a_2^{\prime }-{\mu }_0)/{\sigma }_0=3.05$ when the first digit is “0” and ${\sigma }_0/{\mu }_0=10\%$. As shown in Figure 3a, we note that ${\Delta }_{11}=0.923\%$ for $a_1^{\prime \prime }$, which is almost 0.65 times that of $a_1^{\prime }$.

3.3. Quantizer Architecture Comparison with R-Based Thresholds

For 2-bit channel quantization, both the SA and the ADC are candidates for implementing the quantizer circuit. The SA-based 2-bit quantizer was constructed using SA1 to quantize the first digit and SA2 to quantize the second digit, as shown in Figure 2b. Figure 2c shows the quantization process. Both SA-based 2-bit quantizers use a precharge sense amplifier (PCSA) as the SA1. The 2-bit quantizer A uses a PCSA as the SA2. The 2-bit quantizer B uses an improved multi-bit current-sensitive amplifier (IMB-CSA) as the SA2 [35]. Unlike traditional PCSAs, the IMB-CSA enhances the sensing margin through two mechanisms: (1) A symmetric current-path design eliminates charge-sharing effects during evaluation, directly boosting signal differential by 43%. (2) Negative-feedback adaptive bias compensation dynamically suppresses PVT-induced offsets, decoupling thresholds from MTJ parameter drift. This combined approach improves the read margin while maintaining accuracy under reduced TMR.

The gain in overall read accuracy involves trade-offs with the increasing circuit area, power consumption, and latency, inspired by multi-objective optimization frameworks in STT-MRAM design [22,28]. We define $FoM={(P\times T\times A\times FER)}^{-1}$ for evaluation, where P, T, and A represent power consumption, read latency, and the area, respectively. FER is defined as the single-pass post-ECC frame error rate under worst-case read conditions, used to compare quantization and ECC trade-offs. Prior FER-based studies on emerging memories use the low-FER regime ($FER<{10}^{-2}$) for design comparison, with ${10}^{-3}$∼${10}^{-4}$ as typical operating points [36,37]. Hence, the reported FER values are intended for comparative evaluation under worst-case sensing conditions, not as overall reliability targets. A larger $FoM$ indicates a better overall trade-off among power, latency, area, and FER. Figure 4a,b show that the ideal 1-bit quantizer using the polar code with successive cancellation (SC) decoding can reduce FERs by ${10}^2$∼${10}^3$ times. For the polar code using ideal 2-bit quantizers and SC decoding, the FER gains two orders of magnitude further reduction. When using R-based thresholds $T{h}_A$ and $T{h}_B$, the FER increases slightly compared to $T{h}_{\mathsf{\Omega }}$. When the quantizer takes into account the error of the actual SA, the FER will further increase. Compared to 2-bit quantizer A, 2-bit quantizer B can achieve a ≈30% lower FER due to its higher RM when the code rate is 0.7, $TMR=88\%$.

Figure 4. The FERs of the polar code with SC decoding as functions of the temperature are shown when using the 2-bit and 1-bit ideal quantizers. The code rates are 0.83 for (a) and 0.7 for (b). When considering SA-induced read errors, the FERs for those ECC schemes are also plotted. For comparison, the cases without the ECC scheme are also shown. i.Q.: ideal quantizer.

To determine the $FoM$, we simulated the P, T, and A of the proposed 2-bit quantizer circuits using the SMIC 28 $\mathrm{nm}$ CMOS process, as shown in Table 1. The $FoM$ of the proposed 2-bit quantization schemes was at least four times larger than that of the 1-bit case. The areas of both SA-based 2-bit quantizer circuits are smaller than that of a 2-bit flash ADC. However, only 2-bit quantizer A can achieve lower latency than the ADC scheme. Furthermore, the ADC scheme demonstrates the lowest power consumption. We note that the $FoM$ of 2-bit quantizer A is three times larger than that of the 2-bit ADC scheme, owing to its compact area and low latency. The 2-bit quantizer B can achieve the lowest FER, but this comes at the expense of increased area, power consumption, and latency. The energy efficiency improvement claimed in this work arises from the proposed resistance-based threshold generation method, rather than from Quantizer B alone. Quantizer B is designed to achieve extremely low FERs under low read-margin conditions, thereby reducing the need for re-reads or retries and lowering the average energy per successful read in reliability-critical scenarios. Quantizer A, meanwhile, is optimized for low-power operation. The efficiency benefit of the proposed threshold implementation applies to both quantizers.

Table 1. Comparison of different quantizer circuits ($V_{DD}=1.1V)$.

	1-b. Quan.	2-b. ADC †	2-b. Quan.A	2-b. Quan.B
A ($\mathsf{\mu }$m2)	20.32 (×1)	86.93 (×4.28)	40.64 $(\times 2)$	73.95 $(\times 3.64)$
P ($\mathsf{\mu }$W)	54.9 (×1)	43.9 $(\times 0.8)$	51.4 $(\times 0.94)$	109.7 $(\times 2)$
T (ps)	78 (×1)	218 $(\times 2.79)$	167 $(\times 2.14)$	391 $(\times 5.01)$
RM for 2nd digit quan.	N.A.	1.34	1.34	3.05
${FER}^{ ‡}$	$1.0\times {10}^{-2}$ (×1)	$9.0\times {10}^{-5}$$(\times 0.009)$	$9.0\times {10}^{-5}$$(\times 0.009)$	$8.33\times {10}^{-5}$$(\times 0.008)$
$FoM$	0.001 (×1)	0.01 $(\times 10)$	0.03 $(\times 30)$	0.004 $(\times 4)$

[†] A low-power 2-bit flash ADC consists of 3 NOT gates, 5 NAND gates, and 3 low-power comparators. [‡] When the code rate is 0.83, $TMR=88\%$, polar code with SC decoding.

4. ECC Performance with the Proposed 2-Bit Quantization

Using the proposed 2-bit channel quantization schemes, we compared the error correction performance of various ECC encoding and decoding schemes, including LDPC with reliability-based iterative min-sum (RBI-MS) decoding, the polar code with SC decoding, and the polar code with the cyclic redundancy check-successive cancellation list (CRC-SCL) algorithm. For comparison, the encoded input binary signal should pass through the same BAC-AGC. The choice of code rates $0.83$ and $0.7$ is motivated by their relevance as typical high-rate ECC regimes in embedded memory and cache contexts. Firstly, the design of cache/memory ECC involves a fundamental trade-off between reliability enhancement and redundancy-induced overhead. Consequently, high-rate codes are frequently employed as a redundancy-constrained reference in comparative evaluations [38,39]. Secondly, embedded memory ECC is commonly implemented at a predetermined access granularity, typically ranging from tens to several hundred bits, which necessitates the use of short-block code structures [40]. In line with these considerations, Table 2 presents short-block code configurations corresponding to the two selected rates, facilitating a fair and meaningful comparison. The word lengths and information bit numbers of the chosen ECC schemes at different code rates are shown in Table 2.

Table 2. The $G_K$ for ECC schemes with different decoders ^†.

Code Rate	ECC Encoder and Decoder	2-b Quan.A and ThA	2-b Quan.B and ThB	1-b Quan. and ${\mathit{a}}_{\mathsf{2}}^{\mathsf{\prime }}$	Word Length
0.83	LDPC and RBI-MS	0.180	0.0535	–	(624, 520)
	Polar and SC	0.123	0.0613	–	(128, 107)
	Polar and CRC-SCL	0.163	0.0878	–
	BCH and BM	–	–	0.303	(127, 106)
0.7	LDPC and RBI-MS	0.0930	0.0142	–	(271, 191)
	Polar and SC	0.0871	0.0216	–	(128, 90)
	Polar and CRC-SCL	0.148	0.0148	–

[†] Here, $G_K=lo{g}_{10}\left(\sqrt[K]{{\prod }_{k=1}^K{\displaystyle \frac{FE{R}_R\left(TM{R}_k\right)}{FE{R}_{\mathsf{\Omega }}\left(TM{R}_k\right)}}}\right)$, which expresses the difference between $FE{R}_R$ using R-based thresholds ($T{h}_A$ or $T{h}_B$) and $FE{R}_{\mathsf{\Omega }}$ using $T{h}_{\mathsf{\Omega }}$. Within the range of $TMR=76$∼$106\%$, there are eight $TMR$ data points $(K=8)$ as in Figure 3a.

Figure 5a compares the FERs of three different ECC schemes at a code rate of 0.83 when using the proposed 2-bit quantizers. To provide a fair comparison, we included the FER of the BCH scheme using a 1-bit quantizer, with thresholds of $a_2$ and $a_2^{\prime }$, and the Berlekamp–Massey (BM) decoding algorithm. As shown in Figure 5a, the BCH scheme with 1-bit quantization achieves the lowest FER among the ECC schemes when the RM is high $(TMR>94\%)$. However, its FER increases rapidly as the RM decreases. In such cases, the polar code schemes using SC decoding or the CRC-SCL algorithm perform better than the BCH schemes. As shown in Figure 5b, when the code rate is 0.7, under low RM $(TMR<82\%)$, the polar code with CRC-SCL can achieve the lowest FER among all the schemes. In Table 2, the different $G_K$s of $T{h}_B$ are 1.9 and 4 times lower than those of $T{h}_A$ at code rates of 0.83 and 0.7, respectively. As the FER of $T{h}_B$ is closer to that of $T{h}_{\mathsf{\Omega }}$, the $FoM$ of 2-bit quantizer B shown in Table 1 reduces less than the other non-ideal thresholds. As shown in Figure 5a, in the low-RM case with a code rate of 0.83, the polar code scheme using the SC decoder, 2-bit quantizer A, and $T{h}_A$ can achieve an FER that is four times lower than that of the BCH schemes.

Figure 5. The output FER of the LDPC code with RBI-MS and the polar code with SC or CRC-SCL decoding as functions of TMR when using different 2-bit quantizers are presented for code rates of (a) 0.83 and (b) 0.7, respectively. Here, ${\sigma }_0/{\mu }_0=10\%$ and $P_1=2\times {10}^{-4}$. For comparison, the FERs of BCH code schemes when using the ideal 1-bit quantizer are also shown.

Commercial memory products require ECC schemes with high code rates and low-complexity encoders and decoders. Since complexity is correlated with P, T, and A of the read circuits, the choice of encoder and decoder schemes also depends on the $PTA$ margin offered by the high-density STT-MRAM array in comparison to SRAM. Table 3 lists the encoding and decoding complexities for the BCH, LDPC, and polar codes [22,28,41]. The corresponding encoding and decoding complexities at different code rates are compared in Figure 6a,b. Given N and t, the complexity of the BM decoding algorithm remains constant for the specified code rate. Therefore, the complexities shown in Figure 6a,b were normalized by that of the BCH. When the code rate is 0.83, the encoding complexity of the polar code is 1/17th of BCH, and the decoding complexity of the SC decoder is 1/7th of BM. When the code rate is 0.7, the decoding complexity of the former is 1/13th of BM.

Table 3. The complexity of different ECC decoding algorithms ^†.

Encoder	Encoding Complexity	Decoder	Decoding Complexity	CR = 0.83	CR = 0.7
LDPC	$O\left[NK\right]$	RBI-MS	$O[I_m(2M{d}_c+N-M)/4F+I_{m}M{d}_c]$	$I_m=2.72$ $M=104$ $d_c=44$	$I_m=1.55$ $M=82$ $d_c=17$
Polar	$O\left[Nlo{g}_{2}N\right]$	SC	$O\left[Nlo{g}_{2}N\right]$	–	–
		CRC-SCL	$O\left[LNlo{g}_{2}N\right]$
BCH	$O\left[NK\right]$	BM	$O\left[\right(10mNt+45m^2{t}^2+20m^{2}t$ $-73m{t}^2+24t^2+4m^{2}Nt)/4F]$	$m=7$ $t=3$	$m=7$ $t=5$

[†] N: code length; K: information bits; $I_m$: the maximum iteration; M: number of rows; $d_c$: average row weight of the check matrix; L: the width of the search path list; m: the order of polynomials; t: error-correcting capability; F: times of binary add operations, $CR$ = code rate.

Figure 6. The encoding complexities (upper, normalized to BCH code ) and the decoding complexities (lower, normalized to BM) are presented for code rates of (a) 0.83 and (b) 0.7. Here, T = 27 °C, ${\sigma }_0/{\mu }_0=10\%$ and the corresponding word lengths are shown in Table 2.

5. Conclusions

We implemented 2-bit channel quantization to improve read accuracy in low-RM STT-MRAM. The trade-offs between the overall improvement in read accuracy and the area, power consumption, and latency of the 2-bit quantizers have been investigated. By using these 2-bit quantizers along with an R-based threshold set, polar codes, and SC decoders, 2-bit channel quantization can be achieved with minimal encoding/decoding complexity, while maintaining high read accuracy for short-code-length applications, such as lower-level caches.