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Innovation in Advanced Integrated Circuit Design and Application

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 August 2026 | Viewed by 858

Editors


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Guest Editor
School of Electronic Science and Engineering, Xiamen University, Xiamen 361005, China
Interests: integrated circuit design; artificial intelligent; smart embedded system

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Guest Editor
College of Physics and Information Engineering, Fuzhou University, Fuzhou 350108, China
Interests: emerging memory technologies; DTCO for lower-power TFT memory

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Guest Editor
School of Electronic Science and Engineering, Xiamen University, Xiamen 361005, China
Interests: AI-based speech processing; AI-based analog circuit designs; machine learning

Special Issue Information

Dear Colleagues,

The semiconductor industry is currently undergoing a trend known as More than Moore’s Law, which is unlocking new scaling horizons with advanced integrated circuit designs and applications. These new technologies emphasize heterogeneous integration, system-level co-design, and innovations as critical enablers of future performance and functionality.

The Special Issue is dedicated to publishing recent research and innovations in advanced integrated circuit designs, AI-based methodologies, WBG devices and processes, circuit architectures, and system-level applications that address the growing performance, efficiency, and functionality demands of modern electronic systems.

The scope of this Special Issue covers advanced IC design across analog, mixed-signal, RF, digital, power domains, device fabrication or process technology, photonic-integrated circuits, and emerging technology circuits.

Dr. Xiaochao Li
Prof. Dr. Shaohao Wang
Prof. Dr. Lin Li
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-anonymized peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • integrated circuit design
  • AI-assisted methodology
  • wide-bandgap semiconductors

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Published Papers (1 paper)

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Research

14 pages, 2629 KB  
Article
Implementation of 2-Bit Channel Quantization for the STT-MRAM with Low-Reading-Margin MTJ
by Yecheng Yang, Yitong Lai, Pingping Chen and Shaohao Wang
Electronics 2026, 15(6), 1250; https://doi.org/10.3390/electronics15061250 - 17 Mar 2026
Viewed by 479
Abstract
As the process node is scaled down, the spin-transfer-torque magnetic random-access memory (STT-MRAM) exhibits higher memory density than the static random-access memory (SRAM), making it one of the more promising successors of the low-level on-chip cache memory. However, the low read margin (RM) [...] Read more.
As the process node is scaled down, the spin-transfer-torque magnetic random-access memory (STT-MRAM) exhibits higher memory density than the static random-access memory (SRAM), making it one of the more promising successors of the low-level on-chip cache memory. However, the low read margin (RM) of the magnetic tunnel junction (MTJ) in STT-MRAM can limit the achievable read accuracy. We implemented 2-bit channel quantization for error-correcting code (ECC) schemes and explored the trade-offs between improved read accuracy and factors such as circuit area, power consumption, and latency. The proposed quantization scheme consists of a sensing amplifier-based 2-bit quantizer and MTJ resistor-based soft-decision thresholds. Compared to 1-bit channel quantization using the Bose–Chaudhuri–Hocquenghem (BCH) code, the proposed 2-bit quantization architecture achieves a fourfold reduction in frame error rate (FER) from 8.0×104 to 2.0×104 when paired with polar codes and successive cancellation (SC) decoding. Additionally, this approach results in decoding complexity that is only 1/13th of that required for BCH at a 0.7 code rate. Full article
(This article belongs to the Special Issue Innovation in Advanced Integrated Circuit Design and Application)
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