Search Results (28)

Artificial intelligence (AI) has become ubiquitous in modern computing systems, from high-performance data centers to resource-constrained edge devices. As AI applications continue to expand into mobile and IoT domains, the need for energy-efficient neural network implementations has become increasingly critical. To meet this requirement of energy-efficient computing, this work presents a BWNN (binary-weighted neural network) architecture implemented using FeRAM (Ferroelectric RAM)-based synaptic arrays. By leveraging the non-volatile nature and low-power computing of FeRAM-based CIM (computing in memory), the proposed CIM architecture indicates significant reductions in both dynamic and standby power consumption. Simulation results in this paper demonstrate that scaling the ferroelectric capacitor size can reduce dynamic power by up to 6.5%, while eliminating DRAM-like refresh cycles allows standby power to drop by over 258× under typical conditions. Furthermore, the combination of binary weight quantization and in-memory computing enables energy-efficient inference without significant loss in recognition accuracy, as validated using MNIST datasets. Compared to prior CIM architectures of SRAM-CIM, DRAM-CIM, and STT-MRAM-CIM, the proposed FeRAM-CIM exhibits superior energy efficiency, achieving 230–580 TOPS/W in a 45 nm process. These results highlight the potential of FeRAM-based BWNNs as a compelling solution for edge-AI and IoT applications where energy constraints are critical. Full article

With the rise of the Internet of Things (IoT), smart sensors are increasingly being deployed as compact edge processing units, necessitating continuously writable memory with low power consumption and fast access times. Magnetic random-access memory (MRAM) has emerged as a promising non-volatile alternative to conventional DRAM and SDRAM, offering advantages such as faster access speeds, reduced power consumption, and enhanced endurance. However, MRAM is subject to challenges including process variations and thermal fluctuations, which can induce random bit errors and result in imbalanced probabilities of 0 and 1 bits. To address these issues, we propose a novel sparse coding scheme characterized by a minimum Hamming distance of three. During the encoding process, three check bits are appended to the user data and processed using a generator matrix. If the resulting codeword fails to satisfy the sparsity constraint, it is inverted to comply with the coding requirement. This method is based on the error characteristics inherent in MRAM to facilitate effective error correction. Furthermore, we introduce a dynamic threshold detection technique that updates bit probability estimates in real time during data transmission. Simulation results demonstrate substantial improvements in both error resilience and decoding accuracy, particularly as MRAM density increases. Full article

This paper presents a novel transposed MRAM architecture (WinEdge) specifically optimized for Winograd convolution acceleration in edge computing devices. Leveraging Magnetic Tunnel Junctions (MTJs) with Spin Hall Effect (SHE)-assisted Spin-Transfer Torque (STT) writing, the proposed design enables a single SHE current to simultaneously write data to four MTJs, substantially reducing power consumption. Additionally, the integration of stacked MTJs significantly improves storage density. The proposed WinEdge efficiently supports both standard and transposed data access modes regardless of bit-width, achieving up to 36% lower power, 47% reduced energy consumption, and 28% faster processing speed compared to existing designs. Simulations conducted in 45 nm CMOS technology validate its superiority over conventional SRAM-based solutions for convolutional neural network (CNN) acceleration in resource-constrained edge environments. Full article

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures. Full article

With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards for cryptographic algorithms are not suitable for constrained environments. In this context, the National Institute of Standards and Technology (NIST) started a lightweight cryptography (LWC) competition to develop new algorithm standards that can be fit into small devices. In 2023, NIST has decided to standardize the Ascon family for LWC. This algorithm has been designed to be more resilient to side-channel and fault-based analysis. Nonetheless, hardware implementations of Ascon have been broken by multiple statistical fault analysis and power analysis. These attacks have underlined the necessity to develop adapted countermeasures to side-channel and perturbation-based attacks. However, existing countermeasures are power and area consuming. In this article, we propose a new countermeasure for the Ascon cipher that does not significantly increase the area and power consumption. Our architecture relies on the nonvolatile feature of the Magnetic Tunnel Junction (MTJ) that is the single element of the emerging Magnetic Random Access Memories (MRAM). The proposed circuit removes the bias exploited by statistical attacks. In addition, we have duplicated and complemented the permutation of Ascon to enhance the power analysis robustness of the circuit. Besides the security aspect, our circuit can save current manipulated data, ensuring energy saving from 11% to 32.5% in case of power failure. The area overhead, compared to an unprotected circuit, is $\times 2.43$. Full article

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM) has been proposed to address the sensing reliability issues caused by the single-ended sensing of STT-MRAM. However, it results in a three-fold increase in the free layer (FL) area compared to STT-MRAM, leading to a higher write current. Moreover, the read and write current paths in this memory are the same, thus preventing the optimization of each operation. To address these, in this study, we proposed a complementary polarized spin-orbit torque MRAM (CPSOT-MRAM), which tackles these issues through the SOT mechanism. This CPSOT-MRAM retains the advantages of CPSTT-MRAM while significantly alleviating the high write current requirement issue. Furthermore, the separation of the read and write current paths enables the optimization of each operation. Compared to CPSTT-MRAM, the proposed CPSOT-MRAM achieves a 4.0× and 2.8× improvement in write and read power, respectively, and a 20% reduction in layout area. Full article

In advancing the study of magnetization dynamics in STT-MRAM devices, we employ the spin drift–diffusion model to address the back-hopping effect. This issue manifests as unwanted switching either in the composite free layer or in the reference layer in synthetic antiferromagnets—a challenge that becomes more pronounced with device miniaturization. Although this miniaturization aims to enhance memory density, it inadvertently compromises data integrity. Parallel to this examination, our investigation of the interface exchange coupling within multilayer structures unveils critical insights into the efficacy and dependability of spintronic devices. We particularly scrutinize how exchange coupling, mediated by non-magnetic layers, influences the magnetic interplay between adjacent ferromagnetic layers, thereby affecting their magnetic stability and domain wall movements. This investigation is crucial for understanding the switching behavior in multi-layered structures. Our integrated methodology, which uses both charge and spin currents, demonstrates a comprehensive understanding of MRAM dynamics. It emphasizes the strategic optimization of exchange coupling to improve the performance of multi-layered spintronic devices. Such enhancements are anticipated to encourage improvements in data retention and the write/read speeds of memory devices. This research, thus, marks a significant leap forward in the refinement of high-capacity, high-performance memory technologies. Full article

In this work, we present an efficient Processing in MRAM-Accelerated De Bruijn Graph-based DNA Assembly platform, named PANDA, based on an optimized and hardware-friendly genome assembly algorithm. PANDA is able to assemble large-scale DNA sequence datasets from all-pair overlaps. We first design a PANDA platform that exploits MRAM as computational memory and converts it to a potent processing unit for genome assembly. PANDA can not only execute efficient bulk bit-wise X(N)OR-based comparison/addition operations heavily required for the genome assembly task but also a full set of 2-/3-input logic operations inside the MRAM chip. We then develop a highly parallel and step-by-step hardware-friendly DNA assembly algorithm for PANDA that only requires the developed in-memory logic operations. The platform is then configured with a novel data partitioning and mapping technique that provides local storage and processing to utilize the algorithm level’s parallelism fully. The cross-layer simulation results demonstrate that PANDA reduces the run time and power by a factor of 18 and 11, respectively, compared with CPU. Moreover, speed-ups of up to 2.5 to 10× can be obtained over other recent processing in-memory platforms to perform the same task, like STT-MRAM, ReRAM, and DRAM. Full article

Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation. Full article

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin. Full article

The writing performance of the easy-cone magnetic tunnel junction (MTJ) and perpendicularly magnetized MTJ (pMTJ) under various temperatures was investigated based on the macrospin model. When the temperature is changed from 273 K to 373 K, the switching current density of the pMTJ changes by 56%, whereas this value is only 8% in the easy-cone MTJ. Similarly, the temperature-induced variation of the switching delay is more significant in the pMTJ. This indicates that the easy-cone MTJ has a more stable writing performance under temperature variations, resulting in a wider operating temperature range. In addition, these two types of MTJs exhibit opposite temperature dependence in the current overdrive and write error rate. In the easy cone MTJ, these two performance metrics will reduce as temperature is increased. The results shown in this work demonstrate that the easy-cone MTJ is more suitable to work at high temperatures compared with the pMTJ. Our work provides a guidance for the design of STT-MRAM that is required to operate at high temperatures. Full article

Spin-transfer torque magnetic random-access memory (STT-MRAM) has several desirable features, such as non-volatility, high integration density, and near-zero leakage power. However, it is challenging to adopt STT-MRAM in a wide range of memory applications owing to the long write latency and a tradeoff between read stability and write ability. To mitigate these issues, an STT-MRAM bit cell can be designed with two transistors to support multiple ports, as well as the independent optimization of read stability and write ability. The multi-port STT-MRAM, however, is achieved at the expense of a higher area requirement due to an additional transistor per cell. In this work, we propose an area-efficient design of 1R/1W dual-port STT-MRAM that shares a bitline between two adjacent bit cells. We identify that the bitline sharing may cause simultaneous access conflicts, which can be effectively alleviated by using the bit-interleaving architecture with a long interleaving distance and the sufficient number of word lines per memory bank. We report various metrics of the proposed design based on the bit cell design using a 45 nm process. Compared to a standard single-port STT-MRAM, the proposed design shows a 15% lower read power and a 19% higher read-disturb margin. Compared with prior work on the 1R/1W dual-port STT-MRAM, the proposed design improves the area by 25%. Full article

Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead. Full article

Today’s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizing a spintronic device viz. magnetic tunnel junction (MTJ). Further, area and energy can be reduced through approximate computation. We present a circuit design based on the logic-in-memory computing paradigm on voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM). During the computation, multiple bit cells within the memory array are selected that are in parallel by activating multiple word lines. The designed circuit performs all logic operations-Read/NOT, AND/NAND, OR/NOR, and arithmetic SUM operation (1-bit approximate adder with 75% accuracy for SUM and accurate carry out) by slight modification using control signals. All the simulations have been performed at a 45 nm CMOS technology node with VCMA-MTJ compact model by using the HSPICE simulator. Simulation results show that the proposed circuit’s approximate adder consumes about 300% less energy and 2.3 times faster than its counterpart exact adder. Full article

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (V_DD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal V_DD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time. Full article