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J. Low Power Electron. Appl., Volume 8, Issue 2 (June 2018)

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Open AccessReview
A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things
J. Low Power Electron. Appl. 2018, 8(2), 21; https://doi.org/10.3390/jlpea8020021 - 15 Jun 2018
Cited by 1 | Viewed by 3501
Abstract
This paper presents a top-down methodology for designing battery-less systems for the Internet-of-Things (IoT). We start by extracting features from a target IoT application and the environment in which it will be deployed. We then present strategies to translate these features into design [...] Read more.
This paper presents a top-down methodology for designing battery-less systems for the Internet-of-Things (IoT). We start by extracting features from a target IoT application and the environment in which it will be deployed. We then present strategies to translate these features into design choices that optimize the system and improve its reliability. We look into how to use these features to build the digital sub-system by determining the blocks to implement, the digital architecture, the clock rate of the system, the memory capacity, and the low power states. We also review how these features impact the choice of energy harvesting power management units. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessReview
Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules
J. Low Power Electron. Appl. 2018, 8(2), 20; https://doi.org/10.3390/jlpea8020020 - 14 Jun 2018
Viewed by 2869
Abstract
The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and [...] Read more.
The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 μm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations. Full article
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Open AccessArticle
A Low-Power Voltage Reference Cell with a 1.5 V Output
J. Low Power Electron. Appl. 2018, 8(2), 19; https://doi.org/10.3390/jlpea8020019 - 14 Jun 2018
Cited by 1 | Viewed by 3164
Abstract
A low-power voltage reference cell for system-on-a-chip applications is presented in this paper. The proposed cell uses a combination of standard transistors and thick-oxide transistors to generate a voltage above 1 V. A design procedure is also presented for minimizing the temperature coefficient [...] Read more.
A low-power voltage reference cell for system-on-a-chip applications is presented in this paper. The proposed cell uses a combination of standard transistors and thick-oxide transistors to generate a voltage above 1 V. A design procedure is also presented for minimizing the temperature coefficient (TC) of the reference voltage. This circuit was fabricated in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. It generates a 1.52 V output with a TC of 42 ppm/C from −70 C to 85 C while consuming only 1.11 μW. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors
J. Low Power Electron. Appl. 2018, 8(2), 18; https://doi.org/10.3390/jlpea8020018 - 11 Jun 2018
Cited by 1 | Viewed by 2880
Abstract
Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most [...] Read more.
Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this work, we focus on the computing and energy performance of the Knights Landing Xeon Phi, the latest Intel many-core architecture processor for HPC applications. We consider the 64-core Xeon Phi 7230 and profile its performance and energy efficiency using both its on-chip MCDRAM and the off-chip DDR4 memory as the main storage for application data. As a benchmark application, we use a lattice Boltzmann code heavily optimized for this architecture and implemented using several different arrangements of the application data in memory (data-layouts, in short). We also assess the dependence of energy consumption on data-layouts, memory configurations (DDR4 or MCDRAM) and the number of threads per core. We finally consider possible trade-offs between computing performance and energy efficiency, tuning the clock frequency of the processor using the Dynamic Voltage and Frequency Scaling (DVFS) technique. Full article
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Open AccessArticle
Security Implications for Ultra-Low Power Configurable SoC FPAA Embedded Systems
J. Low Power Electron. Appl. 2018, 8(2), 17; https://doi.org/10.3390/jlpea8020017 - 05 Jun 2018
Cited by 2 | Viewed by 3025
Abstract
We discuss the impact of physical computing techniques to classifying network security issues for ultra-low power networked IoT devices. Physical computing approaches enable at least a factor of 1000 improvement in computational energy efficiency empowering a new generation of local computational structures for [...] Read more.
We discuss the impact of physical computing techniques to classifying network security issues for ultra-low power networked IoT devices. Physical computing approaches enable at least a factor of 1000 improvement in computational energy efficiency empowering a new generation of local computational structures for embedded IoT devices. These techniques offer computational capability to address network security concerns. This paper begins the discussion of security opportunities for, and issues using, FPAA devices for small embedded IoT platforms. These FPAAs enable devices often utilized for low-power context aware computation. Embedded FPAA devices have both positive Security attributes, as well as potential vulnerabilities. FPAA devices can be part of the resulting secure computation, such as implementing unique functions. FPAA devices can be used investigate security of analog/mixed signal capabilities. The paper concludes with summarizing key improvements for secure ultra-low power embedded FPAA devices. Full article
(This article belongs to the Special Issue Low Power Hardware Security)
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Open AccessArticle
A Sub-50 µm2, Voltage-Scalable, Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring
J. Low Power Electron. Appl. 2018, 8(2), 16; https://doi.org/10.3390/jlpea8020016 - 30 May 2018
Viewed by 2930
Abstract
This paper presents an on-chip temperature sensor circuit for dynamic thermal management in VLSI systems. The sensor directly senses the threshold voltage that contains temperature information using a single PMOS device. This simple structure enables the sensor to achieve an ultra-compact footprint. The [...] Read more.
This paper presents an on-chip temperature sensor circuit for dynamic thermal management in VLSI systems. The sensor directly senses the threshold voltage that contains temperature information using a single PMOS device. This simple structure enables the sensor to achieve an ultra-compact footprint. The sensor also exhibits high accuracy and voltage-scalability down to 0.4 V, allowing the sensor to be used in dynamic voltage frequency scaling systems without requiring extra power distribution or regulation. The compact footprint and voltage scalability enables our proposed sensor to be implemented in a digital standard-cell format, allowing aggressive sensor placement very close to target hotspots in digital blocks. The proposed sensor frontend prototyped in a 65 nm CMOS technology has a footprint of 30.1 µm2, 3σ-error of ±1.1 °C across 0 to 100 °C after one temperature point calibration, marking a significant improvement over existing sensors designed for dynamic thermal management in VLSI systems. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
Optimization of Finite-Differencing Kernels for Numerical Relativity Applications
J. Low Power Electron. Appl. 2018, 8(2), 15; https://doi.org/10.3390/jlpea8020015 - 25 May 2018
Cited by 1 | Viewed by 2985
Abstract
A simple optimization strategy for the computation of 3D finite-differencing kernels on many-cores architectures is proposed. The 3D finite-differencing computation is split direction-by-direction and exploits two level of parallelism: in-core vectorization and multi-threads shared-memory parallelization. The main application of this method is to [...] Read more.
A simple optimization strategy for the computation of 3D finite-differencing kernels on many-cores architectures is proposed. The 3D finite-differencing computation is split direction-by-direction and exploits two level of parallelism: in-core vectorization and multi-threads shared-memory parallelization. The main application of this method is to accelerate the high-order stencil computations in numerical relativity codes. Our proposed method provides substantial speedup in computations involving tensor contractions and 3D stencil calculations on different processor microarchitectures, including Intel Knight Landing. Full article
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Open AccessArticle
0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)
J. Low Power Electron. Appl. 2018, 8(2), 14; https://doi.org/10.3390/jlpea8020014 - 09 May 2018
Viewed by 3207
Abstract
An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core [...] Read more.
An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312 K–80 MHz. A number of unique low voltage digital libraries, comprising of approximately 300 logic cells and sequential elements, were used for the MCU SOC design. On-die silicon sensors were utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions, and also to resolve yield and life time problems, while operating at low voltages. A First Fail (FFail) mechanism, which can be digitally and linearly controlled with up to 8 bits, detects the failing SOC voltage at a given frequency. The core operates between 0.45–1.1 V volts with a direct battery connection for an input voltage of 1.6–3.6 V. Measurement results show that the peak energy efficiency is 18μW/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3–5× improved current/DMIPS (Dhrystone Million Instructions per second) compared to the next best chip. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2017)
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Open AccessArticle
Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters
J. Low Power Electron. Appl. 2018, 8(2), 13; https://doi.org/10.3390/jlpea8020013 - 04 May 2018
Cited by 10 | Viewed by 3395
Abstract
Performance analysis tools allow application developers to identify and characterize the inefficiencies that cause performance degradation in their codes, allowing for application optimizations. Due to the increasing interest in the High Performance Computing (HPC) community towards energy-efficiency issues, it is of paramount importance [...] Read more.
Performance analysis tools allow application developers to identify and characterize the inefficiencies that cause performance degradation in their codes, allowing for application optimizations. Due to the increasing interest in the High Performance Computing (HPC) community towards energy-efficiency issues, it is of paramount importance to be able to correlate performance and power figures within the same profiling and analysis tools. For this reason, we present a performance and energy-efficiency study aimed at demonstrating how a single tool can be used to collect most of the relevant metrics. In particular, we show how the same analysis techniques can be applicable on different architectures, analyzing the same HPC application on a high-end and a low-power cluster. The former cluster embeds Intel Haswell CPUs and NVIDIA K80 GPUs, while the latter is made up of NVIDIA Jetson TX1 boards, each hosting an Arm Cortex-A57 CPU and an NVIDIA Tegra X1 Maxwell GPU. Full article
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Open AccessReview
Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters
J. Low Power Electron. Appl. 2018, 8(2), 12; https://doi.org/10.3390/jlpea8020012 - 30 Apr 2018
Cited by 3 | Viewed by 3916
Abstract
This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of [...] Read more.
This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessCorrection
Correction: Alateeq, A. et al. Performance of the Soft-Charging Operation in Series of Step-Up Power Switched-Capacitor Converters. J. Low Power Electron. Appl. 2018, 8, 8
J. Low Power Electron. Appl. 2018, 8(2), 11; https://doi.org/10.3390/jlpea8020011 - 19 Apr 2018
Viewed by 3261
Abstract
After publication of the research paper [1] (https://www.mdpi.com/2079-9268/8/1/8/htm), a confusion of the charge flow direction in Section 2 makes some analysis unclear and confusing [...] Full article
Open AccessArticle
An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis
J. Low Power Electron. Appl. 2018, 8(2), 10; https://doi.org/10.3390/jlpea8020010 - 16 Apr 2018
Cited by 1 | Viewed by 4014
Abstract
This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the [...] Read more.
This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessFeature PaperArticle
Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications
J. Low Power Electron. Appl. 2018, 8(2), 9; https://doi.org/10.3390/jlpea8020009 - 21 Mar 2018
Cited by 1 | Viewed by 3679
Abstract
The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to [...] Read more.
The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques. Full article
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