#
A Sub-50 µm^{2}, Voltage-Scalable, Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring

^{*}

## Abstract

**:**

^{2}, 3σ-error of ±1.1 °C across 0 to 100 °C after one temperature point calibration, marking a significant improvement over existing sensors designed for dynamic thermal management in VLSI systems.

## 1. Introduction

^{2}) is ideal to closely monitor hotspots.

_{DD}). DVFS systems can achieve low power by scaling V

_{DD}down to near threshold voltage when the workload is moderate or low. For the sensors to be employed without extra voltage distribution or local regulation in such systems, they need to operate across a wide range of V

_{DD}.

^{2}[17]) while meeting a relaxed accuracy requirement for DTM application. However, BJT based sensor designs have limited voltage scalability (e.g., minimum V

_{DD}> 1 V) and their size is still one or two orders of magnitude larger than digital standard cells (e.g., 10’s of µm

^{2}or less). Also, BJT is not available in many advanced technologies. As compared to the standard BJT sensors, MOSFET threshold voltage (V

_{TH}) based sensors typically achieve a smaller footprint and better voltage scalability [10,11,12,13,14,15,16,17,18]. However, the linearity of V

_{TH}against temperature is dependent on the characteristics of the process technology which raises the concern on technology portability of such design. Contrarily, BJT based sensors are less dependent on process technology. As presented in [19,20], thermal-diffusivity (TD) sensors that use diffusivity of bulk silicon for temperature sensing can also achieve less dependency on process technology. Another possible challenge for MOSFET based sensor is aging effects (e.g., negative biasing temperature instability [NBTI]) which can cause long-term accuracy degradation.

^{2}per frontend area (or die photos from which the frontend areas are estimated to that level) and (ii) reports accuracy with OPC or no calibration. Note that, the frontend area is the area of the sensing element only and excludes the read-out circuitries (i.e., backend). As shown in the figure, those sensors indeed pose a trade-off between frontend area and accuracy. In [15], the MOSFET based sensor achieves among the smallest 279 µm

^{2}footprint and the voltage-scalability down to 0.6 V with the acceptable (<8 °C error, according to the typical requirement outlined in [12]) 3σ-error of +3.4 °C/−3.2 °C after OPC. In [16], the MOSFET based sensor achieves among the lowest supply voltage scaling down to 0.45 V with the acceptable (<8 °C error, according to the typical requirement outlined in [12]) 3σ-error of ±2 °C. However, each frontend footprint is 1058 µm

^{2}. On the other hand, the TD sensor [19] demonstrates improved area and accuracy trade-off: 400 µm

^{2}frontend footprint (the area is estimated from the die photo) and 3σ-error of ±0.75 °C after OPC. To meet the emerging demands, however, we need a sensor that is smaller, more voltage scalable, and more accurate.

_{TH}which is typically linear to temperature. Since the sensor uses only one transistor for sensing, the sensor area is extremely compact.

^{2}footprint and achieves ±1.1 °C 3σ-error after OPC. The proposed sensor also achieves near-constant accuracy across V

_{DD}= 0.4 V to 1 V. The proposed sensor is 9× smaller than the previous smallest sensor [15] while achieving 3× higher accuracy (Figure 1). The sensor also demonstrates among the lowest voltage scalability down to 0.4 V. As compared to the sensor with lowest voltage scalability [16], it achieves 35× smaller area, 1.4× lower error, and 50 mV lower minimum V

_{DD}.

## 2. Proposed Temperature Sensor Design

#### 2.1. Operating Principle

_{TH}of a PMOS device P1 (Figure 2). V

_{TH}is well-known to have a strong and well-defined linear relationship with temperature and can be formulated as:

_{room}is 300 K, and K

_{VTH}is the first-order temperature coefficient (TC) of V

_{TH}[28]. This is also confirmed with our SPICE simulation results showing a high linearity of R

^{2}> 0.9999 and strong temperature coefficient (K

_{VTH}) of −1.12 mV/°C across process corner variation (Figure 3). The manufacturing process variation mostly modulates the offset of V

_{TH}curves and makes little impact on K

_{VTH}. This characteristic is well-suited for OPC.

_{TH}of P1, we propose to use the discharging behavior of a PMOS device, also known as V

_{TH}drop. This can be simply done by pre-charging the source voltage of P1 (V

_{SENSOR}in Figure 2), followed by discharging operation. Specifically, as shown in the waveform of Figure 2, we first use the shared pre-charging device P2 to pre-charge the shared sampling capacitor C

_{sample}(V

_{SENSOR}node) to V

_{DD}. Once the node is fully charged, we turn off P2 and turn on our sensing device P1 at time = 0 (in Figure 2). The P1 device starts to discharge V

_{SENSOR}node rapidly as it is initially in the strong-inversion region. At time = t

_{weak}, P1 gradually enters the weak-inversion region, and the discharging rate of V

_{SENSOR}node is largely reduced. This is known as the V

_{TH}drop phenomenon. Finally, we sample the voltage of V

_{SENSOR}node at the optimal sampling time (t

_{sample}).

#### 2.2. Optimal t_{sample}

_{SENSOR}node at the optimal sampling time (t

_{sample}). This provides mainly four benefits, namely (i) good linearity of sampled V

_{SENSOR}values over temperature, (ii) robustness against leakage current of P1, (iii) robustness of TC of V

_{SENSOR}values against process variations, and (iv) robustness against pre-charged level (i.e., V

_{DD}) variations.

_{SENSOR}value. Intuitively, if we sample too late, the leakage current of P1 will modulate the V

_{SENSOR}value away from the V

_{TH}value of P1. In such case, the sampled V

_{SENSOR}value can be determined by V

_{TH}of P1 and will also be impacted by the leakage current of P1. Since leakage current has an exponential relationship with V

_{TH}of P1 (or temperature), the linearity of sampled V

_{SENSOR}over temperature can be deteriorated.

_{SENSOR}node is relatively high and sampling time variation can largely degrade the accuracy of the sensor.

^{2}> 0.9999 across worst-case process corners, we set the upper bound of t

_{sample}to 80 µs. On the other hand, the discharging rate exponentially increases if t

_{sample}is too small (Figure 4b). A t

_{sample}that is larger than 1 µs can significantly reduce the discharging rate to <30 µV/ns since P1 is surely in weaker inversion. These set the optimal sampling time window to be between 1 µs to 80 µs after P1 is turned on. In modern IC technology, this range of time window is easy to locate since system clock has a much finer resolution.

_{sample}. To understand the dependency of sampled V

_{SENSOR}values on temperature just after P1 enters weak inversion, we derive its equation to

_{sample}which is the moment to sample the V

_{SENSOR}node is more than 10× larger than t

_{weak}which is the time when P1 enters weak inversion region (e.g., t

_{weak}= 100 ns, t

_{sample}= 1 µs to 80 µs in the optimal sampling time window). Therefore, t

_{weak}can be ignored. I

_{weak}, which is the sub-threshold leakage current of P1 when it just enters weak inversion region can be formulated as

_{u}is the TC of the mobility (µ) and K

_{0}= −K

_{u}+ 2. A key point in the derivation is that V

_{GS}is close to V

_{TH}(T) and thus the exponential term in Equation (3a) becomes 1. In addition, another high-order temperature dependent term, $1+\text{}\frac{\mathrm{T}-{\mathrm{T}}_{\mathrm{room}}}{{\mathrm{T}}_{\mathrm{room}}}$ in Equation (3b), can be approximated to a linear function via the Taylor series since $\frac{\mathrm{T}-{\mathrm{T}}_{\mathrm{room}}}{{\mathrm{T}}_{\mathrm{room}}}$ is much smaller than 1 for the temperature range of interest. For example, for temperature range of 0 °C to 100 °C, this term is in the range of −0.09 and 0.24. Therefore, as shown in Equation (3c), I

_{weak}also becomes a linear function of temperature. After plugging Equation (3c) and Equations (1) and (2), the value of V

_{SENSOR}node sampled at t

_{sample}can be formulated as

_{SENSOR}value is a linear combination of the two parameters, V

_{TH}and I

_{weak}, which are linear to temperature, and thus is also linear to temperature. If V

_{SENSOR}node is sampled after the optimal window, the assumption that V

_{GS}is close to V

_{TH}(T) used in deriving Equation (3a) becomes invalid, and thus the exponential term cannot be eliminated. This makes the sampled V

_{SENSOR}value exhibit poor linearity which matches our simulation results shown in Figure 4a.

_{sample}value. As shown in Equation (4), the TC of the sampled V

_{SENSOR}values is formulated as ${\mathrm{K}}_{\mathrm{VTH}}-\frac{{\mathrm{K}}_{\mathrm{weak}}\xb7{\mathrm{t}}_{\mathrm{sample}}}{{\mathrm{C}}_{\mathrm{sample}}}$. In simulation, we saw that K

_{VTH}is well-maintained across process variation (Figure 3). However, the capacitance value of sampling capacitor (C

_{sample}) can have large variation across the process (e.g., Metal-Insulator-Metal capacitors have ~15% 3σ/µ variation). Also, K

_{weak}value can also vary across the process variation depending on P1 sizing (i.e., W, L). Therefore, it is critical to minimize the impact of C

_{sample}and K

_{weak}variation, which can be achieved by using the smallest allowable t

_{sample}value. We use t

_{sample}= 10 µs, so that K

_{VTH}(−1.12 mV/°C) can be more than 50× larger than the $\frac{{\mathrm{K}}_{\mathrm{weak}}\xb7{\mathrm{t}}_{\mathrm{sample}}}{{\mathrm{C}}_{\mathrm{sample}}}$ term.

#### 2.3. Pre-Charge Level Variation

_{sample}also makes the proposed sensor robust against pre-charge level variation incurred by V

_{DD}noise. After the sensing device P1 turns on, if the pre-charge level varies, it can change t

_{weak}, i.e., the time P1 enters the weak inversion region. However, as shown in Equation (2), the t

_{weak}(100 ns) is two orders of magnitude smaller than optimal t

_{sample}(10 µs). Therefore, the t

_{weak}variation makes minimal impact on the accuracy. As shown in Figure 5, the simulation results show that the pre-charge level variation of 100 mV causes a negligible error increase of <0.02 °C. For the same reason, V

_{TH}offset variation due to process variation (i.e., V

_{TH}(T

_{room}) in Equation (1)) also has a negligible impact on accuracy. The V

_{TH}(T

_{room}) variation only affects the offset of the sampled V

_{SENSOR}value in Equation (4) and can be calibrated out via OPC. As a result, process variation also has a negligible impact on the optimal t

_{sample}found in Section 2.2.

#### 2.4. Sensor Device Type and Body Connection

_{TH}s (i.e., high-V

_{TH}, standard-V

_{TH}, and low-V

_{TH}). We choose the optimal sensor size and t

_{sample}value for each device types while sweeping the length by 1–10× of the minimum, width by 1–30× of the minimum, and the t

_{sample}value from 1 µs to 100 µs. For all the device types, the sample capacitor (C

_{sample}) value is fixed to 1 pF. The results are summarized in Table 1. All the device types achieve the 3σ-error of <2.72 °C while the 2.5 V thick-oxide device achieves the best 3σ-error of 0.93 °C.

_{DD}or V

_{SENSOR}(Figure 6). As shown in Table 2, the sensor with body connected to V

_{DD}achieved better accuracy. However, if V

_{DD}is susceptible to large noise, the body can be connected to V

_{SENSOR}or a separate clean bias voltage with <0.06 °C nominal accuracy degradation.

#### 2.5. V_{DD} Scalability and Noise

_{DD}. We perform OPC and calculate the accuracy across 0.4 to 1 V using (i) V

_{DD}specific TC and (ii) the fixed TC found at V

_{DD}= 1 V. Using the single TC found at 1 V, the downscaling to 0.4 V incurs additional 0.98 °C error for the 3σ case. If V

_{DD}specific TCs are used, the additional error is reduced to 0.33 °C. Using V

_{DD}specific TCs achieves better accuracy. However, it requires to add a lookup table storing those TC values in the DVS/UDVS control systems.

_{DD}noise. If the body of our frontend (P1) is connected to V

_{DD}, V

_{DD}change during the t

_{sample}period could affect the output voltage. The result of the second case (the fixed TC) shows that even with 100 mV V

_{DD}variation during the t

_{sample}period, the accuracy is only degraded by 0.05 °C (Figure 7). Another potential concern for the remote thermal sensing approach is substrate noise in the hotpot location since hotspots are likely to have higher switching activity and thereby have more substrate noise. However, the proposed sensor does not have any direct connection to substrate and thus mostly immune from substrate noise.

## 3. Test Chip Details

_{DD}. We used this device and configuration since it achieves the best accuracy as discussed in Section 2.4. The reference voltage (V

_{CM}) for the S&H and DSADC can be generated by e.g., an accurate bandgap voltage reference (not included in this test chip). Such bandgap circuits may require vertical BJT devices, limiting area and voltage scalability. However, as the voltage reference is shared by multiple frontends, its overhead can be amortized. Also, in the remote sensing architecture, the backend circuitries including the voltage reference are placed in a location away from main digital circuits, which can relax its requirement on area and voltage scalability. We implement a 1 pF capacitor for C

_{sample}. Further investigation on the different sizes for C

_{sample}will be presented in Section 5.

#### 3.1. P2 and C_{sample} Sharing

_{sample}), and the S&H are shared by multiple frontends, providing mainly three benefits. First, each frontend sees the identical load capacitance which is the sum of C

_{sample}and the capacitance of all wires connecting C

_{sample}and the frontends. This makes the TC of sampled V

_{SENSOR}value (i.e., ${\mathrm{K}}_{\mathrm{VTH}}-\frac{{\mathrm{K}}_{\mathrm{weak}}\xb7{\mathrm{t}}_{\mathrm{sample}}}{{\mathrm{C}}_{\mathrm{sample}}})$ to be the same. Second, the manufacturing variation of C

_{sample}makes little impact on accuracy since each frontend sees the same variation, which then is calibrated out by OPC. Last but not the least, the sharing can save the area.

_{DD}on their gates. This forms negative V

_{GS}in the frontends and suppresses the leakage of the inactive sensors. Also, if no temperature sensing is requested, all frontends receive V

_{DD}. This helps prevent aging effects such as NBTI from degrading the long-term accuracy of frontends.

#### 3.2. Operating Principle

_{1}, the V

_{SENSOR}node is pre-charged to V

_{DD}by P2. Then, during period t

_{2}(which is our t

_{sample}), P2 is turned off, and one of the selected sensor is turned on and discharges the V

_{SENSOR}node. During this t

_{1}+ t

_{2}period, the S&H is in the sampling mode. At last, during period t

_{3}, S&H captures the V

_{SENSOR}value on V

_{OUT}and enters hold mode. The V

_{OUT}value which is the sum of V

_{CM}(=0.8 V) and V

_{SENSOR}at the time t

_{sample}is digitized by an off-chip ADC (16 bit, ±5 V) or by on-chip DSADC.

#### 3.3. On-Chip DSADC

_{OUT}32 times and store them in the digital memory (FIFO) (Figure 9). The average of the 32 values is used for the temperature measurement. The DSADC digitization process is as follows. First, ADC

_{OUT}resets to V

_{CM}for 1 μs. The DSADC counter also resets to zero. Second, ADC

_{OUT}is discharged for a fixed period of 1 μs at the rate of V

_{SENSOR}(t

_{sample})/R

_{1}C

_{2}. Third, the DSADC counter starts, and ADC

_{OUT}is charged with a fixed rate of V

_{CM}/R

_{1}C

_{2}. In the course of charging, the comparator finds the moment when the ADC

_{OUT}becomes larger than V

_{CM}and stops the counter. The digital counter output (count), which is formulated as V

_{SENSOR}(t

_{sample}) × 1 μs/V

_{CM}, represents the temperature that the sensor core measures. The counter operates at 1.5GHz with a resolution of 0.5 °C/count.

#### 3.4. Noise Simulation

_{MIN}and F

_{MAX}is set to 0.1 Hz and 1 MHz, respectively. In this simulation, the noise on the two output nodes V

_{SENSOR}and V

_{OUT}(Figure 9) is examined (Figure 10). The 3σ voltage noise (V

_{NOISE}) on node V

_{SENSOR}is 0.44 mV, translated to 0.35 °C error. The 3σ V

_{NOISE}on V

_{OUT}is 0.97 mV (=0.76 °C).

## 4. Measurement Results

#### 4.1. Sensor Accuracy Measurement

^{2}. The V

_{OUT}s of the 40 SS16 sensors after OPC is shown in Figure 12a. The average TC is measured to be −1.27 mV/°C. The measured error is shown in Figure 12b. We also perform two temperature point calibration (TPC) at 20 °C and 80 °C (Figure 13). The TPC can further reduce error down to −0.4 °C/+0.6 °C.

_{sample}on accuracy (Figure 14). As expected from discussion in Section 2.2, the worst-case error (i.e., max.(+)error–max.(−)error) exhibits a bathtub-shape curve with an optimal t

_{sample}appearing between 1µs and 100µs, which achieves the worst-case error of less than 2 °C.

#### 4.2. Supply Voltage Scalability Measurement

_{DD}scalability of the sensors (Figure 15). The same measurement methodology described in Section 4.1 is used for the SS16 frontends except V

_{DD}is swept from 0.4 V to 1 V. The measurements across 20 instances across 5 chips show that the worst-case errors are found nearly constant, around 1.8 °C across V

_{DD}s.

#### 4.3. On-Chip DSADC Measurement

#### 4.4. Comparisons

^{2}area and <±1.1 °C 3σ-error across 40 instances in 10 dies. As shown in Figure 1, the proposed frontend significantly advances the existing area and accuracy trade-off among the MOSFET based designs: the proposed sensor achieves 9× smaller area and 3× higher accuracy than the previous smallest design [15]. The proposed sensor frontend also achieves the voltage scalability down to 0.4 V, which is 50 mV lower than [16], while achieving 35× smaller area and 1.4× higher accuracy.

## 5. Digital Standard-Cell-Compatible Sensor Experiment

^{2}(Figure 17). Then, we use a commercial place and route tool and place one frontend in the center of the multiplier circuits. We use four different-size multipliers, each having the input data widths of 8, 16, 32, or 64 bits. All the multipliers are synthesized with the standard cells using 1V thin-oxide standard-V

_{TH}devices.

_{SENSOR}) using the SPICE simulation with the parasitic-extracted netlists and V

_{DD}= 1 V. Specifically, we simulate the V

_{SENSOR}node while the multiplier actively switches. To extract the inaccuracy only incurred by digital noise, we run two simulations with and without multiplier switching activities and take the difference between them. We also take 1000 samples across varying input vectors for 100 multiplier-clock (CLK) cycles. Figure 18a shows the worst-case coupling noise found in the simulation. It shows that the coupling-induced error increases with larger multipliers since the wire of the V

_{SENSOR}node becomes longer and thus exposed to more of digital circuits.

_{DD}or V

_{SS}). For example, as shown in Figure 18a, shielding the V

_{SENSOR}node with V

_{SS}reduces the worst-case error by ~2× in the 64-bit multiplier.

_{SENSOR}node being shielded, 10× larger sampling capacitor (i.e., 10 pF) reduces the worst-case error proportionally by 10× to 0.44 °C (the 1 pF sampling capacitor can incur the worst-case error of 4.04 °C). Large sampling capacitors, however, can increase backend area, reduce sampling speed (see Section 4 for details) and increase energy dissipation per sampling.

_{SENSOR}node voltage while the multiplier is computing random input vectors at every CLK cycle. We sample the V

_{SENSOR}node multiple times uniformly (every 10 CLK cycle) after an optimal t

_{sample}, and then we average 10 samples. The results show that the averaging technique can reduce coupling induced error by 2.6× as compared to the worst case. To implement the averaging operation, we can use the local FIFO in the on-chip DSADC (discussed in Section 3.3)

## 6. Conclusions

_{TH}sensing. The proposed frontend achieves compact footprint (30.1 µm

^{2}), low 3σ-error (±1.1 °C; across 0 to 100 °C; after OPC), and good voltage scalability (1 to 0.4 V) without losing much accuracy. This is 9× smaller and 3× more accurate than the prior art [15]. It also operates at 50 mV lower than the prior art while achieving while achieving 35× smaller area and 1.4× higher accuracy [16]. The proposed sensor frontend is in the scale of a digital standard cell, which enables an aggressive sensor placement, virtually on a target hotspot. The proposed sensor can enable accurate dense thermal monitoring in modern VLSI systems.

## Author Contributions

## Acknowledgments

## Conflicts of Interest

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**Figure 4.**(

**a**) Linearity of the sampled V

_{SENSOR}values across t

_{sample}; (

**b**) Discharging rate of the V

_{SENSOR}node voltage across t

_{sample}.

**Figure 7.**Simulated accuracy across supply voltage where OPC is performed with (i) V

_{DD}specific TCs and (ii) the fixed TC found at 1 V.

**Figure 10.**Simulated voltage noise histogram from Monte-Carlo based transient noise simulation on (

**a**) the node V

_{SENSOR}and (

**b**) the node V

_{OUT}.

**Figure 12.**(

**a**) Measured V

_{OUT}s of SS16 after one temperature point calibration (OPC) at 50 °C; (

**b**) Errors across temperatures.

**Figure 18.**(

**a**) The worst-case coupling noise error across the V

_{SENSOR}wire lengths; (

**b**) The worst-case coupling noise error across sampling capacitor sizes.

Device Type | Optimal Sizing (µm) | Optimal t_{sample} (µs) | +3σ/−3σ Error (°C) | TC (mV/°C) |
---|---|---|---|---|

2.5 V thick-oxide | L = 0.28 W = 3.6 | 100 | 0.17/−0.76 | −1.50 |

1.0 V thin-oxide high-V _{TH} | L = 0.54 W = 3.0 | 10 | −0.06/−2.20 | −0.87 |

1.0 V thin-oxide standard-V _{TH} | L = 0.54 W = 3.0 | 10 | −0.03/−1.85 | −0.85 |

1.0 V thin-oxide low-V _{TH} | L = 0.54 W = 3.6 | 1 | −0.24/−2.48 | −0.70 |

Body Connection | Optimal Sizing (µm) | Optimal t_{sample} (µs) | +3σ/−3σ Error (°C) | TC (mV/°C) |
---|---|---|---|---|

V_{DD} | L = 0.28 W = 3.6 | 100 | 0.17/−0.76 | −1.50 |

V_{SENSOR} | L = 2.52 W = 12 | 100 | 0.29/−0.70 | −1.64 |

[7] | [17] | [9] | [10] | [13] | [14] | [15] Balanced | [16] | [18] | [20] | Proposed | |
---|---|---|---|---|---|---|---|---|---|---|---|

Tech. | 14 nm | 180 nm | 28 nm | 65 nm | 65 nm | 44 nm | 65 nm | 90 nm | 40 nm | 40 nm | 65 nm |

Type | BJT | BJT | BJT | MOS | MOS | MOS | MOS | MOS | MOS | TD | MOS |

Front end Area ^{1} (${\mathsf{\mu}\mathrm{m}}^{2}$) | 2900 | 360 | - | 1255 | 2000 * | 1725 | 279 | 1058 | 240 | 400 * | 30.1 |

Total Area ^{2} (${\mathsf{\mu}\mathrm{m}}^{2}$) | 8700 | - | 3800 | 5000 * | 8000 | 41,300 | - | - | - | 1650 | 30.1 + 1693 (=6770/4) ^{+} |

VDD (V) | 1.35 | 1~1.8 | 1.1~2 | 1.1 | 1 | 1.1 | 0.6~1 | 0.45~1.5 | 0.5~1 | 0.9~1.2 | 0.4~1 |

Temperature Coefficient (mV/°C) | - | - | - | - | - | 3.2 | 0.57 | - | - | - | 1.27 |

Range ($\xb0\mathrm{C}$) | 0~100 | −55~125 | −20~130 | 40~90 | 0~110 | 0~110 | 0~100 | −55~105 | −40~100 | −40~125 | 0~100 |

Error ^{3} ($\xb0\mathrm{C}$) | - | ±0.6 (3σ) | ±1.8 (3σ) | - | - | - | - | ±3.5 (3σ) | - | ±1.4 (3σ) | - |

Error ^{4} ($\xb0\mathrm{C}$) (on-chip ADC) | - | - | ±0.8 (3σ) | <3.1 | ±1.5 (3σ) | −1.4~2.7 | - | ±2.0 (3σ) ^{+} | - | ±0.75 (3σ) | ±1.4 |

Error ^{4} ($\xb0\mathrm{C}$) (off-chip ADC) | - | - | - | - | - | - | -3.4~3.2 | - | - | - | ±1.1(3σ) |

Error ^{5} ($\xb0\mathrm{C}$) | 3.3 | - | - | - | - | - | −1.5~1.6 ^{+} | - | −0.95~0.97 | - | −0.4~0.6 ^{+} |

Sensor power | - | - | - | - | - | 0.92 µW | - | 17 µW | - | 1 pJ ** | |

Total power | 1.11 mW | - | 16 µA | - | 0.5 mW | 0.4 µW | - | - | - | 2.5 mW | - |

Samples | 52 | 318 | 630 | - | 20 | 61 | 64 | 27 | 30 | 144 | 40 |

^{1}: area of single front end circuitry,

^{2}: area including back end read-out circuitry,

^{3}: error without calibration,

^{4}: error after OPC,

^{5}: error after TPC, *: estimated from die photo, **: energy per sensing from simulation at 1V,

^{+}: read-out-circuit shared by 4 SS16.

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Kim, S.; Seok, M.
A Sub-50 µm^{2}, Voltage-Scalable, Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring. *J. Low Power Electron. Appl.* **2018**, *8*, 16.
https://doi.org/10.3390/jlpea8020016

**AMA Style**

Kim S, Seok M.
A Sub-50 µm^{2}, Voltage-Scalable, Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring. *Journal of Low Power Electronics and Applications*. 2018; 8(2):16.
https://doi.org/10.3390/jlpea8020016

**Chicago/Turabian Style**

Kim, Seongjong, and Mingoo Seok.
2018. "A Sub-50 µm^{2}, Voltage-Scalable, Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring" *Journal of Low Power Electronics and Applications* 8, no. 2: 16.
https://doi.org/10.3390/jlpea8020016