A Sub-50 μm2, Voltage-Scalable, Digital-Standard- Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring

This paper presents an on-chip temperature sensor circuit for dynamic thermal management in VLSI systems. The sensor directly senses the threshold voltage that contains temperature information using a single PMOS device. This simple structure enables the sensor to achieve an ultra-compact footprint. The sensor also exhibits high accuracy and voltage-scalability down to 0.4 V, allowing the sensor to be used in dynamic voltage frequency scaling systems without requiring extra power distribution or regulation. The compact footprint and voltage scalability enables our proposed sensor to be implemented in a digital standard-cell format, allowing aggressive sensor placement very close to target hotspots in digital blocks. The proposed sensor frontend prototyped in a 65 nm CMOS technology has a footprint of 30.1 μm2, 3σ-error of ±1.1 ◦C across 0 to 100 ◦C after one temperature point calibration, marking a significant improvement over existing sensors designed for dynamic thermal management in VLSI systems.

First, ultra-compact sensors are required to monitor the increasing number of hotspots and to improve flexibility in placement.The number of thermal hotspots and the degree of thermal gradients have increased with a higher level of transistor integration.This has led modern high-performance microprocessors to embed tens of temperature sensors (e.g., 48 sensors in [21][22][23]).The emerging technology trends toward multicore architectures and 3D-IC can create even more hotspots due to the thermal coupling between cores and 3D layers [1].To monitor all of hotspots at low hardware overhead, sensor footprint needs to be extremely small [1][2][3].Further on, the hotspots are often only identified in the later stages of design.Thus, it is highly desirable to make sensors small for maximal flexibility in placement.
The remote sensing approach, as proposed in [8, 16,17], can help meet this size requirement.In this approach, each frontend is remotely placed very close to hotspots, yet the backend is shared by multiple frontends and placed in a location away from hot digital-heavy area, the latter being able to simplify the design of the backend as well.In this approach, a frontend of the size of digital standard cells (e.g., 10s of µm 2 ) is ideal to closely monitor hotspots.
Second, while minimizing the sensor size, the sensors need to maintain a small circuit-level error across process and voltage variations to improve thermal sensing accuracy.Overestimating the temperature of the system can cause unnecessary performance throttling.On the other hand, underestimating can raise a reliability concern.This demands high accuracy temperature sensor circuits.Furthermore, such high accuracy is desired to require simple and inexpensive post-silicon calibration, e.g., one temperature point calibration (OPC).
Finally, voltage scalability is important for supporting dynamic voltage frequency scaling (DVFS) systems [24,25].DVFS systems can provide peak performance when workload is heavy by operating a processor at nominal supply voltage (V DD ).DVFS systems can achieve low power by scaling V DD down to near threshold voltage when the workload is moderate or low.For the sensors to be employed without extra voltage distribution or local regulation in such systems, they need to operate across a wide range of V DD .
Classical BJT based sensors [4,5] targeting general temperature sensing applications (e.g., RFID tags) achieves high accuracy (e.g., ±0.15 • C 3σ-error), however, their large area and high supply voltage requirement limit their usage in DTM.Recent BJT based sensor designs [6][7][8][9]17] successfully miniaturize their frontend footprint (as low as 360 µm 2 [17]) while meeting a relaxed accuracy requirement for DTM application.However, BJT based sensor designs have limited voltage scalability (e.g., minimum V DD > 1 V) and their size is still one or two orders of magnitude larger than digital standard cells (e.g., 10's of µm 2 or less).Also, BJT is not available in many advanced technologies. A compared to the standard BJT sensors, MOSFET threshold voltage (V TH ) based sensors typically achieve a smaller footprint and better voltage scalability [10][11][12][13][14][15][16][17][18].However, the linearity of V TH against temperature is dependent on the characteristics of the process technology which raises the concern on technology portability of such design.Contrarily, BJT based sensors are less dependent on process technology.As presented in [19,20], thermal-diffusivity (TD) sensors that use diffusivity of bulk silicon for temperature sensing can also achieve less dependency on process technology.Another possible challenge for MOSFET based sensor is aging effects (e.g., negative biasing temperature instability [NBTI]) which can cause long-term accuracy degradation.
In Figure 1, we choose the recent designs from [26], which (i) report less than or close to 1000 µm 2 per frontend area (or die photos from which the frontend areas are estimated to that level) and (ii) reports accuracy with OPC or no calibration.Note that, the frontend area is the area of the sensing element only and excludes the read-out circuitries (i.e., backend).As shown in the figure, those sensors indeed pose a trade-off between frontend area and accuracy.In [15], the MOSFET based sensor achieves among the smallest 279 µm 2 footprint and the voltage-scalability down to 0.6 V with the acceptable (<8 • C error, according to the typical requirement outlined in [12]) 3σ-error of +3.4 • C/−3.2 • C after OPC.In [16], the MOSFET based sensor achieves among the lowest supply voltage scaling down to 0.45 V with the acceptable (<8 • C error, according to the typical requirement outlined in [12]) 3σ-error of ±2 • C.However, each frontend footprint is 1058 µm 2 .On the other hand, the TD sensor [19] demonstrates improved area and accuracy trade-off: 400 µm 2 frontend footprint (the area is estimated from the die photo) and 3σ-error of ±0.75 • C after OPC.To meet the emerging demands, however, we need a sensor that is smaller, more voltage scalable, and more accurate.
In this work, we propose a MOSFET-based temperature frontend circuit for remote sensing that meets the aforementioned requirements [27].Our proposed sensor uses a single sensing PMOS device and directly samples its V TH which is typically linear to temperature.Since the sensor uses only one transistor for sensing, the sensor area is extremely compact.
We design and prototype 8 × 8 array of sensor frontends together with a readout circuitry in 65 nm CMOS.Multiple sensor frontends can be combined to experiment different sensor sizes.The measurement of our proposed sensor with an optimal configuration, called SS16 or Sensor-Size-16, has a 30.1 µm 2 footprint and achieves ±1.1 • C 3σ-error after OPC.The proposed sensor also achieves near-constant accuracy across V DD = 0.4 V to 1 V.The proposed sensor is 9× smaller than the previous smallest sensor [15] while achieving 3× higher accuracy (Figure 1).The sensor also demonstrates among the lowest voltage scalability down to 0.4 V.As compared to the sensor with lowest voltage scalability [16], it achieves 35× smaller area, 1.4× lower error, and 50 mV lower minimum V DD .
J. Low Power Electron.Appl.2018, 8, x 3 of 17 has a 30.1 µm 2 footprint and achieves ±1.1 °C 3σ-error after OPC.The proposed sensor also achieves near-constant accuracy across VDD = 0.4 V to 1 V.The proposed sensor is 9× smaller than the previous smallest sensor [15] while achieving 3× higher accuracy (Figure 1).The sensor also demonstrates among the lowest voltage scalability down to 0.4 V.As compared to the sensor with lowest voltage scalability [16], it achieves 35× smaller area, 1.4× lower error, and 50 mV lower minimum VDD.Additionally, we experiment the robustness of our sensor operation while being embedded in digital circuits.Embedding sensors inside digital blocks raises the concern on coupling noise incurred by nearby gates that are actively-switching.We layout our proposed sensor in a digital standard-cell format and place and route it in a digital multiplier.Then, we simulate the parasitic-extracted netlists of the sensor and multiplier.The results show that it is feasible to mitigate the impact of coupling noise of digital gates with the design efforts such as shielding, larger sampling capacitors, and postmeasurement data processing (e.g., averaging).
The paper is organized as follows.In Section 2, we discuss the operating principle of the proposed sensor and the design methodology to optimize accuracy.In Section 3, we discuss the test chip design and noise simulation results.We then discuss the measurement results of the test chip in Section 4. In Section 5, the experiment with the proposed sensor in digital standard-cell format is described.Also, techniques to mitigate the effect of coupling noise are presented.Finally, we conclude the paper in Section 6.

Operating Principle
The proposed frontend directly samples the VTH of a PMOS device P1 (Figure 2).VTH is well-known to have a strong and well-defined linear relationship with temperature and can be formulated as: where T is temperature, Troom is 300 K, and KVTH is the first-order temperature coefficient (TC) of VTH [28].This is also confirmed with our SPICE simulation results showing a high linearity of R 2 > 0.9999 and strong temperature coefficient (KVTH) of −1.12 mV/°C across process corner variation (Figure 3).The manufacturing process variation mostly modulates the offset of VTH curves and makes little impact on KVTH.This characteristic is well-suited for OPC.Additionally, we experiment the robustness of our sensor operation while being embedded in digital circuits.Embedding sensors inside digital blocks raises the concern on coupling noise incurred by nearby gates that are actively-switching.We layout our proposed sensor in a digital standard-cell format and place and route it in a digital multiplier.Then, we simulate the parasitic-extracted netlists of the sensor and multiplier.The results show that it is feasible to mitigate the impact of coupling noise of digital gates with the design efforts such as shielding, larger sampling capacitors, and post-measurement data processing (e.g., averaging).
The paper is organized as follows.In Section 2, we discuss the operating principle of the proposed sensor and the design methodology to optimize accuracy.In Section 3, we discuss the test chip design and noise simulation results.We then discuss the measurement results of the test chip in Section 4. In Section 5, the experiment with the proposed sensor in digital standard-cell format is described.Also, techniques to mitigate the effect of coupling noise are presented.Finally, we conclude the paper in Section 6.

Operating Principle
The proposed frontend directly samples the V TH of a PMOS device P1 (Figure 2).V TH is well-known to have a strong and well-defined linear relationship with temperature and can be formulated as: where T is temperature, T room is 300 K, and K VTH is the first-order temperature coefficient (TC) of V TH [28].This is also confirmed with our SPICE simulation results showing a high linearity of R 2 > 0.9999 and strong temperature coefficient (K VTH ) of −1.12 mV/ • C across process corner variation (Figure 3).The manufacturing process variation mostly modulates the offset of V TH curves and makes little impact on K VTH .This characteristic is well-suited for OPC.To capture the VTH of P1, we propose to use the discharging behavior of a PMOS device, also known as VTH drop.This can be simply done by pre-charging the source voltage of P1 (VSENSOR in Figure 2), followed by discharging operation.Specifically, as shown in the waveform of Figure 2, we first use the shared pre-charging device P2 to pre-charge the shared sampling capacitor Csample (VSENSOR node) to VDD.Once the node is fully charged, we turn off P2 and turn on our sensing device P1 at time = 0 (in Figure 2).The P1 device starts to discharge VSENSOR node rapidly as it is initially in the strong-inversion region.At time = tweak, P1 gradually enters the weak-inversion region, and the discharging rate of VSENSOR node is largely reduced.This is known as the VTH drop phenomenon.Finally, we sample the voltage of VSENSOR node at the optimal sampling time (tsample).

Optimal tsample
In the proposed sensor design, it is important to sample VSENSOR node at the optimal sampling time (tsample).This provides mainly four benefits, namely (i) good linearity of sampled VSENSOR values over temperature, (ii) robustness against leakage current of P1, (iii) robustness of TC of VSENSOR values against process variations, and (iv) robustness against pre-charged level (i.e., VDD) variations.
The optimal sampling time can be determined based on the two constraints that set the upper and lower bound.The upper bound is set by the leakage current of P1, which perturbs the desired sampled VSENSOR value.Intuitively, if we sample too late, the leakage current of P1 will modulate the VSENSOR value away from the VTH value of P1.In such case, the sampled VSENSOR value can be determined by VTH of P1 and will also be impacted by the leakage current of P1.Since leakage current has an exponential relationship with VTH of P1 (or temperature), the linearity of sampled VSENSOR over temperature can be deteriorated.
On the other hand, the lower bound is set by the fact that we need to wait until P1 surely enters weak inversion.In the boundary between strong and weak inversion, the discharging rate of VSENSOR node is relatively high and sampling time variation can largely degrade the accuracy of the sensor.
We perform circuit simulation to find the optimal range of sampling time.As expected, the linearity  To capture the VTH of P1, we propose to use the discharging behavior of a PMOS device, also known as VTH drop.This can be simply done by pre-charging the source voltage of P1 (VSENSOR in Figure 2), followed by discharging operation.Specifically, as shown in the waveform of Figure 2, we first use the shared pre-charging device P2 to pre-charge the shared sampling capacitor Csample (VSENSOR node) to VDD.Once the node is fully charged, we turn off P2 and turn on our sensing device P1 at time = 0 (in Figure 2).The P1 device starts to discharge VSENSOR node rapidly as it is initially in the strong-inversion region.At time = tweak, P1 gradually enters the weak-inversion region, and the discharging rate of VSENSOR node is largely reduced.This is known as the VTH drop phenomenon.Finally, we sample the voltage of VSENSOR node at the optimal sampling time (tsample).

Optimal tsample
In the proposed sensor design, it is important to sample VSENSOR node at the optimal sampling time (tsample).This provides mainly four benefits, namely (i) good linearity of sampled VSENSOR values over temperature, (ii) robustness against leakage current of P1, (iii) robustness of TC of VSENSOR values against process variations, and (iv) robustness against pre-charged level (i.e., VDD) variations.
The optimal sampling time can be determined based on the two constraints that set the upper and lower bound.The upper bound is set by the leakage current of P1, which perturbs the desired sampled VSENSOR value.Intuitively, if we sample too late, the leakage current of P1 will modulate the VSENSOR value away from the VTH value of P1.In such case, the sampled VSENSOR value can be determined by VTH of P1 and will also be impacted by the leakage current of P1.Since leakage current has an exponential relationship with VTH of P1 (or temperature), the linearity of sampled VSENSOR over temperature can be deteriorated.
On the other hand, the lower bound is set by the fact that we need to wait until P1 surely enters weak inversion.In the boundary between strong and weak inversion, the discharging rate of VSENSOR node is relatively high and sampling time variation can largely degrade the accuracy of the sensor.
We perform circuit simulation to find the optimal range of sampling time.As expected, the linearity To capture the V TH of P1, we propose to use the discharging behavior of a PMOS device, also known as V TH drop.This can be simply done by pre-charging the source voltage of P1 (V SENSOR in Figure 2), followed by discharging operation.Specifically, as shown in the waveform of Figure 2, we first use the shared pre-charging device P2 to pre-charge the shared sampling capacitor C sample (V SENSOR node) to V DD .Once the node is fully charged, we turn off P2 and turn on our sensing device P1 at time = 0 (in Figure 2).The P1 device starts to discharge V SENSOR node rapidly as it is initially in the strong-inversion region.At time = t weak , P1 gradually enters the weak-inversion region, and the discharging rate of V SENSOR node is largely reduced.This is known as the V TH drop phenomenon.Finally, we sample the voltage of V SENSOR node at the optimal sampling time (t sample ).

Optimal t sample
In the proposed sensor design, it is important to sample V SENSOR node at the optimal sampling time (t sample ).This provides mainly four benefits, namely (i) good linearity of sampled V SENSOR values over temperature, (ii) robustness against leakage current of P1, (iii) robustness of TC of V SENSOR values against process variations, and (iv) robustness against pre-charged level (i.e., V DD ) variations.
The optimal sampling time can be determined based on the two constraints that set the upper and lower bound.The upper bound is set by the leakage current of P1, which perturbs the desired sampled V SENSOR value.Intuitively, if we sample too late, the leakage current of P1 will modulate the V SENSOR value away from the V TH value of P1.In such case, the sampled V SENSOR value can be determined by V TH of P1 and will also be impacted by the leakage current of P1.Since leakage current has an exponential relationship with V TH of P1 (or temperature), the linearity of sampled V SENSOR over temperature can be deteriorated.
On the other hand, the lower bound is set by the fact that we need to wait until P1 surely enters weak inversion.In the boundary between strong and weak inversion, the discharging rate of V SENSOR node is relatively high and sampling time variation can largely degrade the accuracy of the sensor.
We perform circuit simulation to find the optimal range of sampling time.As expected, the linearity of sampled VSENSOR values rapidly degrades due to leakage when sampled too late (Figure 4a).To maintain the linearity R 2 > 0.9999 across worst-case process corners, we set the upper bound of t sample to 80 µs.On the other hand, the discharging rate exponentially increases if t sample is too small (Figure 4b).A t sample that is larger than 1 µs can significantly reduce the discharging rate to <30 µV/ns since P1 is surely in weaker inversion.These set the optimal sampling time window to be between 1 µs to 80 µs after P1 is turned on.In modern IC technology, this range of time window is easy to locate since system clock has a much finer resolution.
of sampled VSENSOR values rapidly degrades due to leakage when sampled too late (Figure 4a).To maintain the linearity R 2 > 0.9999 across worst-case process corners, we set the upper bound of tsample to 80 µs.On the other hand, the discharging rate exponentially increases if tsample is too small (Figure 4b).A tsample that is larger than 1 µs can significantly reduce the discharging rate to <30 µV/ns since P1 is surely in weaker inversion.These set the optimal sampling time window to be between 1 µs to 80 µs after P1 is turned on.In modern IC technology, this range of time window is easy to locate since system clock has a much finer resolution.Furthermore, we analytically confirm the validity of our intuition and simulation results on the optimal tsample.To understand the dependency of sampled VSENSOR values on temperature just after P1 enters weak inversion, we derive its equation to In Equation ( 2), tsample which is the moment to sample the VSENSOR node is more than 10× larger than tweak which is the time when P1 enters weak inversion region (e.g., tweak = 100 ns, tsample = 1 µs to 80 µs in the optimal sampling time window).Therefore, tweak can be ignored.Iweak, which is the subthreshold leakage current of P1 when it just enters weak inversion region can be formulated as where Ku is the TC of the mobility (µ) and K0 = −Ku + 2. A key point in the derivation is that VGS is close to VTH(T) and thus the exponential term in Equation (3a) becomes 1.In addition, another highorder temperature dependent term, 1 + in Equation (3b), can be approximated to a linear function via the Taylor series since is much smaller than 1 for the temperature range of interest.For example, for temperature range of 0 °C to 100 °C, this term is in the range of −0.09 and 0.24.Therefore, as shown in Equation (3c), Iweak also becomes a linear function of temperature.After plugging Equation (3c) and Equations ( 1) and ( 2), the value of VSENSOR node sampled at tsample can be Furthermore, we analytically confirm the validity of our intuition and simulation results on the optimal t sample .To understand the dependency of sampled V SENSOR values on temperature just after P1 enters weak inversion, we derive its equation to In Equation (2), t sample which is the moment to sample the V SENSOR node is more than 10× larger than t weak which is the time when P1 enters weak inversion region (e.g., t weak = 100 ns, t sample = 1 µs to 80 µs in the optimal sampling time window).Therefore, t weak can be ignored.I weak , which is the sub-threshold leakage current of P1 when it just enters weak inversion region can be formulated as where K u is the TC of the mobility (µ) and K 0 = −K u + 2. A key point in the derivation is that V GS is close to V TH (T) and thus the exponential term in Equation (3a) becomes 1.In addition, another high-order temperature dependent term, 1 + T−T room T room in Equation (3b), can be approximated to a linear function via the Taylor series since T−T room T room is much smaller than 1 for the temperature range of interest.For example, for temperature range of 0 • C to 100 • C, this term is in the range of −0.09 and 0.24.Therefore, as shown in Equation (3c), I weak also becomes a linear function of temperature.After plugging Equation (3c) and Equations ( 1) and ( 2), the value of V SENSOR node sampled at t sample can be formulated as where •T K u +K 0 room .The sampled V SENSOR value is a linear combination of the two parameters, V TH and I weak , which are linear to temperature, and thus is also linear to temperature.If V SENSOR node is sampled after the optimal window, the assumption that V GS is close to V TH (T) used in deriving Equation (3a) becomes invalid, and thus the exponential term cannot be eliminated.This makes the sampled V SENSOR value exhibit poor linearity which matches our simulation results shown in Figure 4a.
From the above analytical study, we can find another important consideration on choosing the optimal t sample value.As shown in Equation ( 4), the TC of the sampled V SENSOR values is formulated . In simulation, we saw that K VTH is well-maintained across process variation (Figure 3).However, the capacitance value of sampling capacitor (C sample ) can have large variation across the process (e.g., Metal-Insulator-Metal capacitors have ~15% 3σ/µ variation).Also, K weak value can also vary across the process variation depending on P1 sizing (i.e., W, L).Therefore, it is critical to minimize the impact of C sample and K weak variation, which can be achieved by using the smallest allowable t sample value.We use t sample = 10 µs, so that K VTH (−1.12 mV/ • C) can be more than 50× larger than the

Pre-Charge Level Variation
The optimal t sample also makes the proposed sensor robust against pre-charge level variation incurred by V DD noise.After the sensing device P1 turns on, if the pre-charge level varies, it can change t weak , i.e., the time P1 enters the weak inversion region.However, as shown in Equation ( 2), the t weak (100 ns) is two orders of magnitude smaller than optimal t sample (10 µs).Therefore, the t weak variation makes minimal impact on the accuracy.As shown in Figure 5, the simulation results show that the pre-charge level variation of 100 mV causes a negligible error increase of <0.02 • C. For the same reason, V TH offset variation due to process variation (i.e., V TH (T room ) in Equation ( 1)) also has a negligible impact on accuracy.The V TH (T room ) variation only affects the offset of the sampled V SENSOR value in Equation ( 4) and can be calibrated out via OPC.As a result, process variation also has a negligible impact on the optimal t sample found in Section 2.2.
J. Low Power Electron.Appl.2018, 8, x 6 of 17 formulated as where The sampled VSENSOR value is a linear combination of the two parameters, VTH and Iweak, which are linear to temperature, and thus is also linear to temperature.If VSENSOR node is sampled after the optimal window, the assumption that VGS is close to VTH(T) used in deriving Equation (3a) becomes invalid, and thus the exponential term cannot be eliminated.This makes the sampled VSENSOR value exhibit poor linearity which matches our simulation results shown in Figure 4a.
From the above analytical study, we can find another important consideration on choosing the optimal tsample value.As shown in Equation ( 4), the TC of the sampled VSENSOR values is formulated as K − • .In simulation, we saw that KVTH is well-maintained across process variation (Figure 3).However, the capacitance value of sampling capacitor (Csample) can have large variation across the process (e.g., Metal-Insulator-Metal capacitors have ~15% 3σ/µ variation).Also, Kweak value can also vary across the process variation depending on P1 sizing (i.e., W, L).Therefore, it is critical to minimize the impact of Csample and Kweak variation, which can be achieved by using the smallest allowable tsample value.We use tsample = 10 µs, so that KVTH (−1.12 mV/°C) can be more than 50× larger than the • term.

Pre-Charge Level Variation
The optimal tsample also makes the proposed sensor robust against pre-charge level variation incurred by VDD noise.After the sensing device P1 turns on, if the pre-charge level varies, it can change tweak, i.e., the time P1 enters the weak inversion region.However, as shown in Equation ( 2), the tweak (100 ns) is two orders of magnitude smaller than optimal tsample (10 µs).Therefore, the tweak variation makes minimal impact on the accuracy.As shown in Figure 5, the simulation results show that the pre-charge level variation of 100 mV causes a negligible error increase of <0.02 °C.For the same reason, VTH offset variation due to process variation (i.e., VTH(Troom) in Equation ( 1)) also has a negligible impact on accuracy.The VTH(Troom) variation only affects the offset of the sampled VSENSOR value in Equation ( 4) and can be calibrated out via OPC.As a result, process variation also has a negligible impact on the optimal tsample found in Section 2.2.

Sensor Device Type and Body Connection
We explore various device types provided in the 65 nm process for the proposed sensor frontend.We simulate the accuracy by running 100 Monte-Carlo simulations with process variation and

Sensor Device Type and Body Connection
We explore various device types provided in the 65 nm process for the proposed sensor frontend.We simulate the accuracy by running 100 Monte-Carlo simulations with process variation and performing OPC.In the simulation, we compare 2.5 V thick-oxide device and 1 V thin-oxide device with different V TH s (i.e., high-V TH , standard-V TH , and low-V TH ).We choose the optimal sensor size and t sample value for each device types while sweeping the length by 1-10× of the minimum, width by 1-30× of the minimum, and the t sample value from 1 µs to 100 µs.For all the device types, the sample capacitor (C sample ) value is fixed to 1 pF.The results are summarized in Table 1.All the device types achieve the 3σ-error of <2.72 • C while the 2.5 V thick-oxide device achieves the best 3σ-error of 0.93 • C. We also simulate the sensor circuits using 2.5 V thick-oxide devices across two different body connections, i.e., connected to V DD or V SENSOR (Figure 6).As shown in Table 2, the sensor with body connected to V DD achieved better accuracy.However, if V DD is susceptible to large noise, the body can be connected to V SENSOR or a separate clean bias voltage with <0.06 • C nominal accuracy degradation.performing OPC.In the simulation, we compare 2.5 V thick-oxide device and 1 V thin-oxide device with different VTHs (i.e., high-VTH, standard-VTH, and low-VTH).We choose the optimal sensor size and tsample value for each device types while sweeping the length by 1-10× of the minimum, width by 1-30× of the minimum, and the tsample value from 1 µs to 100 µs.For all the device types, the sample capacitor (Csample) value is fixed to 1 pF.The results are summarized in Table 1.All the device types achieve the 3σ-error of <2.72 °C while the 2.5 V thick-oxide device achieves the best 3σ-error of 0.93 °C.We also simulate the sensor circuits using 2.5 V thick-oxide devices across two different body connections, i.e., connected to VDD or VSENSOR (Figure 6).As shown in Table 2, the sensor with body connected to VDD achieved better accuracy.However, if VDD is susceptible to large noise, the body can be connected to VSENSOR or a separate clean bias voltage with <0.06 °C nominal accuracy degradation.

VDD Scalability and Noise
We experiment voltage scalability of the proposed frontends.To evaluate this, we simulate the 3σ-error of the sensor frontend whose body is connected to VDD.We perform OPC and calculate the accuracy across 0.4 to 1 V using (i) VDD specific TC and (ii) the fixed TC found at VDD = 1 V.Using the single TC found at 1 V, the downscaling to 0.4 V incurs additional 0.98 °C error for the 3σ case.If VDD specific TCs are used, the additional error is reduced to 0.33 °C.Using VDD specific TCs achieves better accuracy.However, it requires to add a lookup table storing those TC values in the DVS/UDVS control systems.
One of the challenges in the remote sensing approach is VDD noise.If the body of our frontend (P1) is connected to VDD, VDD change during the tsample period could affect the output voltage.The

V DD Scalability and Noise
We experiment voltage scalability of the proposed frontends.To evaluate this, we simulate the 3σ-error of the sensor frontend whose body is connected to V DD .We perform OPC and calculate the accuracy across 0.4 to 1 V using (i) V DD specific TC and (ii) the fixed TC found at V DD = 1 V.Using the single TC found at 1 V, the downscaling to 0.4 V incurs additional 0.98 • C error for the 3σ case.If V DD specific TCs are used, the additional error is reduced to 0.33 • C. Using V DD specific TCs achieves better accuracy.However, it requires to add a lookup table storing those TC values in the DVS/UDVS control systems.
One of the challenges in the remote sensing approach is V DD noise.If the body of our frontend (P1) is connected to V DD , V DD change during the t sample period could affect the output voltage.The result of the second case (the fixed TC) shows that even with 100 mV V DD variation during the t sample period, the accuracy is only degraded by 0.05 • C (Figure 7).Another potential concern for the remote thermal sensing approach is substrate noise in the hotpot location since hotspots are likely to have higher switching activity and thereby have more substrate noise.However, the proposed sensor does not have any direct connection to substrate and thus mostly immune from substrate noise.
J. Low Power Electron.Appl.2018, 8, x 8 of 17 period, the accuracy is only degraded by 0.05 °C (Figure 7).Another potential concern for the remote thermal sensing approach is substrate noise in the hotpot location since hotspots are likely to have higher switching activity and thereby have more substrate noise.However, the proposed sensor does not have any direct connection to substrate and thus mostly immune from substrate noise.

Test Chip Details
The test chip is designed and fabricated in a 65 nm general-purpose CMOS process.Figure 8 shows the die photo of the test chip.The test chip consists of (i) an 8 × 8 frontends, each frontend being able to be configured from Sensor-Size-1 to Sensor-Size-64 (SS1 to SS64); (ii) shared sample and hold circuits (S&H); and (iii) on-chip read-out circuitry using the dual-slope analog-to-digital converter (DSADC) topology (Figure 9).We assume those are a part of the remote sensing architecture.Each unit-size sensor is a 3× minimum-sized 2.5 V thick-oxide PMOS device with its body tied to VDD.We used this device and configuration since it achieves the best accuracy as discussed in Section 2.4.The reference voltage (VCM) for the S&H and DSADC can be generated by e.g., an accurate bandgap voltage reference (not included in this test chip).Such bandgap circuits may require vertical BJT devices, limiting area and voltage scalability.However, as the voltage reference is shared by multiple frontends, its overhead can be amortized.Also, in the remote sensing architecture, the backend circuitries including the voltage reference are placed in a location away from main digital circuits, which can relax its requirement on area and voltage scalability.We implement a 1 pF capacitor for Csample.Further investigation on the different sizes for Csample will be presented in Section 5.

Test Chip Details
The test chip is designed and fabricated in a 65 nm general-purpose CMOS process.Figure 8 shows the die photo of the test chip.The test chip consists of (i) an 8 × 8 frontends, each frontend being able to be configured from Sensor-Size-1 to Sensor-Size-64 (SS1 to SS64); (ii) shared sample and hold circuits (S&H); and (iii) on-chip read-out circuitry using the dual-slope analog-to-digital converter (DSADC) topology (Figure 9).We assume those are a part of the remote sensing architecture.Each unit-size sensor is a 3× minimum-sized 2.5 V thick-oxide PMOS device with its body tied to V DD .We used this device and configuration since it achieves the best accuracy as discussed in Section 2.4.The reference voltage (V CM ) for the S&H and DSADC can be generated by e.g., an accurate bandgap voltage reference (not included in this test chip).Such bandgap circuits may require vertical BJT devices, limiting area and voltage scalability.However, as the voltage reference is shared by multiple frontends, its overhead can be amortized.Also, in the remote sensing architecture, the backend circuitries including the voltage reference are placed in a location away from main digital circuits, which can relax its requirement on area and voltage scalability.We implement a 1 pF capacitor for C sample .Further investigation on the different sizes for C sample will be presented in Section 5.
J. Low Power Electron.Appl.2018, 8, x 8 of 17 period, the accuracy is only degraded by 0.05 °C (Figure 7).Another potential concern for the remote thermal sensing approach is substrate noise in the hotpot location since hotspots are likely to have higher switching activity and thereby have more substrate noise.However, the proposed sensor does not have any direct connection to substrate and thus mostly immune from substrate noise.

Test Chip Details
The test chip is designed and fabricated in a 65 nm general-purpose CMOS process.Figure 8 shows the die photo of the test chip.The test chip consists of (i) an 8 × 8 frontends, each frontend being able to be configured from Sensor-Size-1 to Sensor-Size-64 (SS1 to SS64); (ii) shared sample and hold circuits (S&H); and (iii) on-chip read-out circuitry using the dual-slope analog-to-digital converter (DSADC) topology (Figure 9).We assume those are a part of the remote sensing architecture.Each unit-size sensor is a 3× minimum-sized 2.5 V thick-oxide PMOS device with its body tied to VDD.We used this device and configuration since it achieves the best accuracy as discussed in Section 2.4.The reference voltage (VCM) for the S&H and DSADC can be generated by e.g., an accurate bandgap voltage reference (not included in this test chip).Such bandgap circuits may require vertical BJT devices, limiting area and voltage scalability.However, as the voltage reference is shared by multiple frontends, its overhead can be amortized.Also, in the remote sensing architecture, the backend circuitries including the voltage reference are placed in a location away from main digital circuits, which can relax its requirement on area and voltage scalability.We implement a 1 pF capacitor for Csample.Further investigation on the different sizes for Csample will be presented in Section 5.

P2 and Csample Sharing
The pre-charge PMOS device (P2), the sampling capacitor (Csample), and the S&H are shared by multiple frontends, providing mainly three benefits.First, each frontend sees the identical load capacitance which is the sum of Csample and the capacitance of all wires connecting Csample and the frontends.This makes the TC of sampled VSENSOR value (i.e., K − • ) to be the same.Second, the manufacturing variation of Csample makes little impact on accuracy since each frontend sees the same variation, which then is calibrated out by OPC.Last but not the least, the sharing can save the area.When a frontend is sensing, all the other sensors receive VDD on their gates.This forms negative VGS in the frontends and suppresses the leakage of the inactive sensors.Also, if no temperature sensing is requested, all frontends receive VDD.This helps prevent aging effects such as NBTI from degrading the long-term accuracy of frontends.

Operating Principle
The operational waveform of a test chip is shown in Figure 9.During period t1, the VSENSOR node is pre-charged to VDD by P2.Then, during period t2 (which is our tsample), P2 is turned off, and one of the selected sensor is turned on and discharges the VSENSOR node.During this t1 + t2 period, the S&H is in the sampling mode.At last, during period t3, S&H captures the VSENSOR value on VOUT and enters hold mode.The VOUT value which is the sum of VCM (=0.8 V) and VSENSOR at the time tsample is digitized by an off-chip ADC (16 bit, ±5 V) or by on-chip DSADC.

On-Chip DSADC
We design an on-chip DSADC to digitize VOUT 32 times and store them in the digital memory (FIFO) (Figure 9).The average of the 32 values is used for the temperature measurement.The DSADC

P2 and C sample Sharing
The pre-charge PMOS device (P2), the sampling capacitor (C sample ), and the S&H are shared by multiple frontends, providing mainly three benefits.First, each frontend sees the identical load capacitance which is the sum of C sample and the capacitance of all wires connecting C sample and the frontends.This makes the TC of sampled V SENSOR value (i.e., K VTH − ) to be the same.Second, the manufacturing variation of C sample makes little impact on accuracy since each frontend sees the same variation, which then is calibrated out by OPC.Last but not the least, the sharing can save the area.
When a frontend is sensing, all the other sensors receive V DD on their gates.This forms negative V GS in the frontends and suppresses the leakage of the inactive sensors.Also, if no temperature sensing is requested, all frontends receive V DD .This helps prevent aging effects such as NBTI from degrading the long-term accuracy of frontends.

Operating Principle
The operational waveform of a test chip is shown in Figure 9.During period t 1 , the V SENSOR node is pre-charged to V DD by P2.Then, during period t 2 (which is our t sample ), P2 is turned off, and one of the selected sensor is turned on and discharges the V SENSOR node.During this t 1 + t 2 period, the S&H is in the sampling mode.At last, during period t 3 , S&H captures the V SENSOR value on V OUT and enters hold mode.The V OUT value which is the sum of V CM (=0.8 V) and V SENSOR at the time t sample is digitized by an off-chip ADC (16 bit, ±5 V) or by on-chip DSADC.

On-Chip DSADC
We design an on-chip DSADC to digitize V OUT 32 times and store them in the digital memory (FIFO) (Figure 9).The average of the 32 values is used for the temperature measurement.The DSADC digitization process is as follows.First, ADC OUT resets to V CM for 1 µs.The DSADC counter also resets to zero.Second, ADC OUT is discharged for a fixed period of 1 µs at the rate of V SENSOR (t sample )/R 1 C 2 .Third, the DSADC counter starts, and ADC OUT is charged with a fixed rate of V CM /R 1 C 2 .In the course of charging, the comparator finds the moment when the ADC OUT becomes larger than V CM and stops the counter.The digital counter output (count), which is formulated as V SENSOR (t sample ) × 1 µs/V CM , represents the temperature that the sensor core measures.The counter operates at 1.5GHz with a resolution of 0.5 • C/count.

Noise Simulation
The impact of flicker and thermal noise on the accuracy of the proposed frontend is investigated using the transient noise analysis methodology outlined in [29].Specifically, 10 k Monte-Carlo simulation with transient noise analyses is performed, and noise statistics is gathered.The F MIN and F MAX is set to 0.1 Hz and 1 MHz, respectively.In this simulation, the noise on the two output nodes V SENSOR and V OUT (Figure 9) is examined (Figure 10).The 3σ voltage noise (V NOISE ) on node V SENSOR is 0.44 mV, translated to 0.35 • C error.The 3σ V NOISE on V OUT is 0.97 mV (=0.76 • C). digitization process is as follows.First, ADCOUT resets to VCM for 1 µs.The DSADC counter also resets to zero.Second, ADCOUT is discharged for a fixed period of 1 µs at the rate of VSENSOR(tsample)/R1C2.Third, the DSADC counter starts, and ADCOUT is charged with a fixed rate of VCM/R1C2.In the course of charging, the comparator finds the moment when the ADCOUT becomes larger than VCM and stops the counter.The digital counter output (count), which is formulated as VSENSOR(tsample) × 1 µs/VCM, represents the temperature that the sensor core measures.The counter operates at 1.5GHz with a resolution of 0.5 °C/count.

Noise Simulation
The impact of flicker and thermal noise on the accuracy of the proposed frontend is investigated using the transient noise analysis methodology outlined in [29].Specifically, 10 k Monte-Carlo simulation with transient noise analyses is performed, and noise statistics is gathered.The FMIN and FMAX is set to 0.1 Hz and 1 MHz, respectively.In this simulation, the noise on the two output nodes VSENSOR and VOUT (Figure 9) is examined (Figure 10).The 3σ voltage noise (VNOISE) on node VSENSOR is 0.44 mV, translated to 0.35 °C error.The 3σ VNOISE on VOUT is 0.97 mV (=0.76 °C).

Sensor Accuracy Measurement
Each of the randomly chosen 10 test chips is placed in a temperature chamber and measured while the temperature is swept from 0 °C to 100 °C with 10 °C steps.We measure the sensors across 10 dies (total 40 SS16 frontends) using off-chip ADC (±5 V, 16b in a National Instruments data-acquisition PCI card) and the on-chip DSADC.The sensor reading is calibrated with OPC at 50 °C and the error is calculated using a fixed TC for all the sensors in 10 dies.In all the measurement, the t1 and t2 in Figure 9 are set to be 1 µs and 10 µs, respectively.Therefore, the raw sampling rate is 91 kS/s.
To study the impact of sensor area on accuracy, multiple unit-size sensors are combined and measured with the off-chip ADC.As more unit-size sensors are combined to form a larger sensor, the accuracy is improved (Figure 11).When 16 of unit-size sensors are combined (i.e., SS16), it achieves the 3σ-error of ±1.1 °C post OPC.The footprint is 30.1 µm 2 .The VOUTs of the 40 SS16 sensors after OPC is shown in Figure 12a.The average TC is measured to be −1.27mV/°C.The measured error is shown in Figure 12b.We also perform two temperature point calibration (TPC) at 20 °C and 80 °C (Figure 13).The TPC can further reduce error down to −0.4 °C/+0.6 °C.
We also investigate the impact of tsample on accuracy (Figure 14).As expected from discussion in Section 2.2, the worst-case error (i.e., max.(+)error-max.(−)error)exhibits a bathtub-shape curve with an optimal tsample appearing between 1µs and 100µs, which achieves the worst-case error of less than 2 °C.

Sensor Accuracy Measurement
Each of the randomly chosen 10 test chips is placed in a temperature chamber and measured while the temperature is swept from 0 • C to 100 • C with 10 • C steps.We measure the sensors across 10 dies (total 40 SS16 frontends) using off-chip ADC (±5 V, 16b in a National Instruments data-acquisition PCI card) and the on-chip DSADC.The sensor reading is calibrated with OPC at 50 • C and the error is calculated using a fixed TC for all the sensors in 10 dies.In all the measurement, the t1 and t2 in Figure 9 are set to be 1 µs and 10 µs, respectively.Therefore, the raw sampling rate is 91 kS/s.
To study the impact of sensor area on accuracy, multiple unit-size sensors are combined and measured with the off-chip ADC.As more unit-size sensors are combined to form a larger sensor, the accuracy is improved (Figure 11).When 16 of unit-size sensors are combined (i.e., SS16), it achieves the 3σ-error of ±1.1 • C post OPC.The footprint is 30.1 µm 2 .The V OUT s of the 40 SS16 sensors after OPC is shown in Figure 12a.The average TC is measured to be −1.27mV/ • C. The measured error is shown in Figure 12b.We also perform two temperature point calibration (TPC) at 20 • C and 80 • C (Figure 13).The TPC can further reduce error down to −0.4 • C/+0.6 • C.
We also investigate the impact of t sample on accuracy (Figure 14).As expected from discussion in Section 2.2, the worst-case error (i.e., max.(+)error-max.(−)error)exhibits a bathtub-shape curve with an optimal t sample appearing between 1µs and 100µs, which achieves the worst-case error of less than 2 • C.

Supply Voltage Scalability Measurement
We also measure VDD scalability of the sensors (Figure 15).The same measurement methodology described in Section 4.1 is used for the SS16 frontends except VDD is swept from 0.4 V to 1 V.The measurements across 20 instances across 5 chips show that the worst-case errors are found nearly constant, around 1.8 °C across VDDs.

On-Chip DSADC Measurement
We repeat the measurement in Section 4.1 using on-chip DSADC (Figure 16).The measurement across 5 chips shows the worst-case error increase by 1.1 °C, as compared to the measurement using the off-chip ADC.The increased error is mainly due to the resolution limitation (0.5 °C) of the DSADC.

Supply Voltage Scalability Measurement
We also measure V DD scalability of the sensors (Figure 15).The same measurement methodology described in Section 4.1 is used for the SS16 frontends except V DD is swept from 0.4 V to 1 V.The measurements across 20 instances across 5 chips show that the worst-case errors are found nearly constant, around 1.8 • C across V DD s.

Supply Voltage Scalability Measurement
We also measure VDD scalability of the sensors (Figure 15).The same measurement methodology described in Section 4.1 is used for the SS16 frontends except VDD is swept from 0.4 V to 1 V.The measurements across 20 instances across 5 chips show that the worst-case errors are found nearly constant, around 1.8 °C across VDDs.

On-Chip DSADC Measurement
We repeat the measurement in Section 4.1 using on-chip DSADC (Figure 16).The measurement across 5 chips shows the worst-case error increase by 1.1 °C, as compared to the measurement using the off-chip ADC.The increased error is mainly due to the resolution limitation (0.5 °C) of the DSADC.

On-Chip DSADC Measurement
We repeat the measurement in Section 4.1 using on-chip DSADC (Figure 16).The measurement across 5 chips shows the worst-case error increase by 1.1 • C, as compared to the measurement using the off-chip ADC.The increased error is mainly due to the resolution limitation (0.5 • C) of the DSADC.8, 16, 32, or 64 bits.All the multipliers are synthesized with the standard cells using 1V thin-oxide standard-V TH devices.

Digital Standard-Cell-Compatible Sensor Experiment
In this section, we investigate the placement of our proposed frontend in digital circuits that are designed and laid out in the automatic standard cell design flow.First, we layout the proposed SS16 frontend in the same digital standard-cell format.This takes the area of 3.6 × 9.2 = 33.12µm 2 (Figure 17).Then, we use a commercial place and route tool and place one frontend in the center of the multiplier circuits.We use four different-size multipliers, each having the input data widths of 8, 16, 32, or 64 bits.All the multipliers are synthesized with the standard cells using 1V thin-oxide standard-VTH devices.We study the impact of coupling noise of digital circuits on the sensor output (VSENSOR) using the SPICE simulation with the parasitic-extracted netlists and VDD = 1 V. Specifically, we simulate the VSENSOR node while the multiplier actively switches.To extract the inaccuracy only incurred by digital noise, we run two simulations with and without multiplier switching activities and take the difference between them.We also take 1000 samples across varying input vectors for 100 multiplierclock (CLK) cycles.Figure 18a shows the worst-case coupling noise found in the simulation.It shows that the coupling-induced error increases with larger multipliers since the wire of the VSENSOR node becomes longer and thus exposed to more of digital circuits.One technique to reduce coupling noise is to shield the sensitive node with stable voltage (e.g., VDD or VSS).For example, as shown in Figure 18a, shielding the VSENSOR node with VSS reduces the worst-case error by ~2× in the 64-bit multiplier.We study the impact of coupling noise of digital circuits on the sensor output (V SENSOR ) using the SPICE simulation with the parasitic-extracted netlists and V DD = 1 V. Specifically, we simulate the V SENSOR node while the multiplier actively switches.To extract the inaccuracy only incurred by digital noise, we run two simulations with and without multiplier switching activities and take the difference between them.We also take 1000 samples across varying input vectors for 100 multiplier-clock (CLK) cycles.Figure 18a shows the worst-case coupling noise found in the simulation.It shows that the coupling-induced error increases with larger multipliers since the wire of the V SENSOR node becomes longer and thus exposed to more of digital circuits.

Digital Standard-Cell-Compatible Sensor Experiment
In this section, we investigate the placement of our proposed frontend in digital circuits that are designed and laid out in the automatic standard cell design flow.First, we layout the proposed SS16 frontend in the same digital standard-cell format.This takes the area of 3.6 × 9.2 = 33.12µm 2 (Figure 17).Then, we use a commercial place and route tool and place one frontend in the center of the multiplier circuits.We use four different-size multipliers, each having the input data widths of 8, 16, 32, or 64 bits.All the multipliers are synthesized with the standard cells using 1V thin-oxide standard-VTH devices.We study the impact of coupling noise of digital circuits on the sensor output (VSENSOR) using the SPICE simulation with the parasitic-extracted netlists and VDD = 1 V. Specifically, we simulate the VSENSOR node while the multiplier actively switches.To extract the inaccuracy only incurred by digital noise, we run two simulations with and without multiplier switching activities and take the difference between them.We also take 1000 samples across varying input vectors for 100 multiplierclock (CLK) cycles.Figure 18a shows the worst-case coupling noise found in the simulation.It shows that the coupling-induced error increases with larger multipliers since the wire of the VSENSOR node becomes longer and thus exposed to more of digital circuits.One technique to reduce coupling noise is to shield the sensitive node with stable voltage (e.g., VDD or VSS).For example, as shown in Figure 18a, shielding the VSENSOR node with VSS reduces the worst-case error by ~2× in the 64-bit multiplier.One technique to reduce coupling noise is to shield the sensitive node with stable voltage (e.g., V DD or V SS ).For example, as shown in Figure 18a, shielding the V SENSOR node with V SS reduces the worst-case error by ~2× in the 64-bit multiplier.
Another technique is to use a larger sampling capacitor.This increases the capacitance of a victim wire relative to coupling capacitance.As shown in Figure 18b, larger sampling capacitors proportionally reduce the worst-case error.For example, in the experiment with the 64-bit multiplier and the V SENSOR node being shielded, 10× larger sampling capacitor (i.e., 10 pF) reduces the worst-case error proportionally by 10× to 0.44 • C (the 1 pF sampling capacitor can incur the worst-case error of 4.04 • C).Large sampling capacitors, however, can increase backend area, reduce sampling speed (see Section 4 for details) and increase energy dissipation per sampling.
Finally, we study the last technique-averaging-to mitigate coupling noise impact.Figure 19 shows the V SENSOR node voltage while the multiplier is computing random input vectors at every CLK cycle.We sample the V SENSOR node multiple times uniformly (every 10 CLK cycle) after an optimal t sample , and then we average 10 samples.The results show that the averaging technique can reduce coupling induced error by 2.6× as compared to the worst case.To implement the averaging operation, we can use the local FIFO in the on-chip DSADC (discussed in Section 3.3) Another technique is to use a larger sampling capacitor.This increases the capacitance of a victim wire relative to coupling capacitance.As shown in Figure 18b, larger sampling capacitors proportionally reduce the worst-case error.For example, in the experiment with the 64-bit multiplier and the VSENSOR node being shielded, 10× larger sampling capacitor (i.e., 10 pF) reduces the worst-case error proportionally by 10× to 0.44 °C (the 1 pF sampling capacitor can incur the worst-case error of 4.04 °C).Large sampling capacitors, however, can increase backend area, reduce sampling speed (see Section 4 for details) and increase energy dissipation per sampling.
Finally, we study the last technique-averaging-to mitigate coupling noise impact.Figure 19 shows the VSENSOR node voltage while the multiplier is computing random input vectors at every CLK cycle.We sample the VSENSOR node multiple times uniformly (every 10 CLK cycle) after an optimal tsample, and then we average 10 samples.The results show that the averaging technique can reduce coupling induced error by 2.6× as compared to the worst case.To implement the averaging operation, we can use the local FIFO in the on-chip DSADC (discussed in Section 3. In larger designs, the impact of coupling noise on sensor accuracy can become significant.Also, as the metal wire network connecting frontends becomes larger, the resistance and capacitance of the metal wire can make more prominent impact on delay and sensor accuracy.To mitigate these problems, one can consider hierarchical networks which disable the unused part of networks, and potentially have multiple backends [8,16,17].

Conclusions
In this paper, we propose a temperature sensor frontend based on a novel mechanism of direct VTH sensing.The proposed frontend achieves compact footprint (30.1 µm 2 ), low 3σ-error (±1.1 °C; across 0 to 100 °C; after OPC), and good voltage scalability (1 to 0.4 V) without losing much accuracy.This is 9× smaller and 3× more accurate than the prior art [15].It also operates at 50 mV lower than the prior art while achieving while achieving 35× smaller area and 1.4× higher accuracy [16].The proposed sensor frontend is in the scale of a digital standard cell, which enables an aggressive sensor placement, virtually on a target hotspot.The proposed sensor can enable accurate dense thermal monitoring in modern VLSI systems.

Figure 1 .
Figure 1.Area, error, and VDD,min comparisons of recent compact thermal sensors.

Figure 1 .
Figure 1.Area, error, and V DD,min comparisons of recent compact thermal sensors.

Figure 2 .
Figure 2. Schematic and operation of the proposed sensor frontend that directly samples VTH.

Figure 3 .
Figure 3. VTH over temperature across process corner variations.

Figure 2 .Figure 2 .
Figure 2. Schematic and operation of the proposed sensor frontend that directly samples V TH .

Figure 3 .
Figure 3. VTH over temperature across process corner variations.

Figure 3 .
Figure 3. V TH over temperature across process corner variations.

Figure 4 .
Figure 4. (a) Linearity of the sampled VSENSOR values across tsample; (b) Discharging rate of the VSENSOR node voltage across tsample.

Figure 4 .
Figure 4. (a) Linearity of the sampled V SENSOR values across t sample ; (b) Discharging rate of the V SENSOR node voltage across t sample .

Figure 5 .
Figure 5. Impact of the pre-charge level (VDD) variation on accuracy.

Figure 5 .
Figure 5. Impact of the pre-charge level (V DD ) variation on accuracy.

BodyFigure 6 .
Figure 6.Two different possible body connections of the sensing device P1.

Figure 6 .
Figure 6.Two different possible body connections of the sensing device P1.

Figure 7 .
Figure 7. Simulated accuracy across supply voltage where OPC is performed with (i) VDD specific TCs and (ii) the fixed TC found at 1 V.

Figure 7 .
Figure 7. Simulated accuracy across supply voltage where OPC is performed with (i) V DD specific TCs and (ii) the fixed TC found at 1 V.

Figure 7 .
Figure 7. Simulated accuracy across supply voltage where OPC is performed with (i) VDD specific TCs and (ii) the fixed TC found at 1 V.

Figure 9 .
Figure 9. Test chip block diagram and its operational waveform.

Figure 10 .
Figure 10.Simulated voltage noise histogram from Monte-Carlo based transient noise simulation on (a) the node VSENSOR and (b) the node VOUT.

Figure 10 .
Figure 10.Simulated voltage noise histogram from Monte-Carlo based transient noise simulation on (a) the node V SENSOR and (b) the node V OUT .

Figure 11 .
Figure 11.Accuracy and area trade-off across sensor sizes.

Figure 13 .
Figure 13.Measured error after two temperature point calibration (TPC) at 20 °C and 80 °C.Figure 13.Measured error after two temperature point calibration (TPC) at 20 • C and 80 • C.

Figure 14 .
Figure 14.The worst-case error of multiple SS16s across t samples .

Figure 15 .
Figure 15.The worst-case error across V DD s.

Figure 17 .
Figure 17.A layout of a 32-bit multiplier and SS16 embedded in the multiplier.

Figure 18 .
Figure 18.(a) The worst-case coupling noise error across the VSENSOR wire lengths; (b) The worst-case coupling noise error across sampling capacitor sizes.

Figure 17 .
Figure 17.A layout of a 32-bit multiplier and SS16 embedded in the multiplier.

Figure 17 .
Figure 17.A layout of a 32-bit multiplier and SS16 embedded in the multiplier.

Figure 18 .
Figure 18.(a) The worst-case coupling noise error across the VSENSOR wire lengths; (b) The worst-case coupling noise error across sampling capacitor sizes.

Figure 18 .
Figure 18.(a) The worst-case coupling noise error across the V SENSOR wire lengths; (b) The worst-case coupling noise error across sampling capacitor sizes.

Figure 19 .
Figure 19.Coupling noise induced error and its reduction via averaging.

Table 1 .
Comparisons of the proposed sensors in different device types.

Table 2 .
Comparison of the proposed sensors with different body connection.

Table 1 .
Comparisons of the proposed sensors in different device types.

Table 2 .
Comparison of the proposed sensors with different body connection.