# A Low-Power Voltage Reference Cell with a 1.5 V Output

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## Abstract

**:**

## 1. Introduction

## 2. Principle of Operation

#### 2.1. Reference Current Generator

#### 2.2. Start-Up Circuit

#### 2.3. Temperature-Independent Voltage Reference Cell

## 3. Design Procedure for Low TC ${\mathit{V}}_{\mathit{out}}$

- Set $\frac{{S}_{11}}{{S}_{10}}\gg 1$, and choose a proper size for ${R}_{C}$ to bias the current reference cell in subthreshold. Note that increasing $\frac{{S}_{11}}{{S}_{10}}$ will necessitate a larger ${R}_{C}$ in order to bias the circuit in subthreshold, so area limitation requirements for the circuit can be used to set a maximum value of $\frac{{S}_{11}}{{S}_{10}}$.
- Ensure that all transistor lengths are large enough to neglect the effects of channel-length modulation.
- Choose the midpoint, ${T}_{0}$, of the desired temperature range, and use Equation (22) to solve for $y\frac{{R}_{out}}{{R}_{C}}$.
- If the midpoint of the ${V}_{out}$ vs. T curve is not at the desired location, then, according to Equation (22), we can adjust ${R}_{C}$ to move ${T}_{0}$ to higher or lower temperatures. In addition, ${R}_{out}$ must be adjusted, accordingly, to keep the resistive ratio at a reasonable value, based on Equation (22).

## 4. Experimental Results

## 5. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**Schematic diagram of the proposed voltage reference cell. ${M}_{t1}$ and ${M}_{t2}$ are thick-oxide transistors (5 V I/O devices).

**Figure 2.**(

**a**) A PTAT voltage generator; (

**b**) generating a higher voltage through stacking PTAT voltage generators; (

**c**) a CTAT voltage generator.

**Figure 3.**Die photograph of the proposed circuit. The single capacitor (${C}_{s}$), the thick-oxide transistors, and the thin-oxide transistors are all delineated in this die photograph. The two resistors were included as off-chip components. The size of this voltage reference cell (excluding the resistors) was 300 $\mathsf{\mu}$m × 110 $\mathsf{\mu}$m.

**Figure 4.**Measured TC of the proposed circuit under three different supply values for multiple conditions. (

**a**) ${R}_{out}/{R}_{C}$ = 3 M$\Omega $/500 k$\Omega $ from −70 to +125 °C; (

**b**) ${R}_{out}/{R}_{C}$ = 3 M$\Omega $/500 k$\Omega $ from −70 to +85 °C; (

**c**) ${R}_{out}/{R}_{C}$ = 2 M$\Omega $/400 k$\Omega $ from +10 to +155 °C.

Device (s) | Size |
---|---|

${M}_{1}-{M}_{5}$ | 5 $\mathsf{\mu}$m × 1 $\mathsf{\mu}$m |

${M}_{6}-{M}_{7}$ | 20 $\mathsf{\mu}$m × 20 $\mathsf{\mu}$m |

${M}_{8}-{M}_{10}$ | 4 $\mathsf{\mu}$m × 2 $\mathsf{\mu}$m |

${M}_{11}$ | 40 $\mathsf{\mu}$m × 2 $\mathsf{\mu}$m |

${M}_{12}$ | 20 $\mathsf{\mu}$m × 20 $\mathsf{\mu}$m |

${M}_{13}$ | 40 $\mathsf{\mu}$m × 20 $\mathsf{\mu}$m |

${M}_{14}$ | 4 $\mathsf{\mu}$m × 20 $\mathsf{\mu}$m |

${M}_{t1}-{M}_{t2}$ | 200 $\mathsf{\mu}$m × 10 $\mathsf{\mu}$m |

${C}_{S}$ | 3.1 pF |

Process | Temperature Coefficient (ppm/${}^{\circ}$C) | Temperature Range | ${\mathit{V}}_{\mathit{REF}}$ | Line Regulation (mV/V) | PSRR (dB) | ${\mathit{V}}_{\mathit{DD}}$ | Power | Area (mm${}^{2}$) | Comments | |
---|---|---|---|---|---|---|---|---|---|---|

[8] | 0.6 $\mathsf{\mu}$m | 14.36 | [0 100] | 1.2525 V | 5.5 | −42 dB @ 10 MHz | 1.5∼2 | 40 $\mathsf{\mu}$W | 0.11 | - |

[9] | 0.35 $\mathsf{\mu}$m | 12.85 | [5 95] | 1.2 V | 28 | −26.2 dB @ 100 Hz | 1.75∼3.5 | 35.7 $\mathsf{\mu}$W | 0.0206 | - |

[13] | 0.18 $\mathsf{\mu}$m | 8–73 | [0 100] | 1.25 V | 0.31 | −41 dB @ 100 Hz | 1.4∼3.6 | 35 pW | 0.0025 | Native NFETs |

[15] | 0.18 $\mathsf{\mu}$m | 4.1 | [−55 125] | 1.1402 V | 0.3 | −54 dB @ 100 Hz | 1.3∼2.6 | 11.18 $\mathsf{\mu}$W | 0.05 | NPN BJTs |

[19] | 0.35 $\mathsf{\mu}$m | 215–394 | [−20 80] | 1.18V | 4.5 | - | 1.3∼3.3 | 0.108 $\mathsf{\mu}$W | 0.21 | - |

[24] | 0.25 $\mathsf{\mu}$m | 627 | [20 50] | 0.71–1.03 V | 0.2 | −51 dB @ 100 Hz | 1.5∼3.5 | 0.12 $\mathsf{\mu}$W | 0.011 | - |

[25] | 0.18 $\mathsf{\mu}$m | 147 | [−40 120] | 1.09 V | - | −62 dB @ 100 Hz | 1.2∼1.8 | 0.1 $\mathsf{\mu}$W | 0.0294 | - |

[26] | 0.18 $\mathsf{\mu}$m | 4 | [0 100] | 1.012 V | 0.5 | −66 dB @ 1 kHz | 1.1∼1.8 | 21 $\mathsf{\mu}$W | - | - |

This work #1 | 0.35 $\mathsf{\mu}$m | 110 @ 3.3 V | [−70 125] | 1.52 V | 10 | −44 dB @ 1 MHz | 1.7∼3.3 | 1.11 $\mathsf{\mu}$W | 0.06 | - |

This work $\#1$ | 0.35 $\mathsf{\mu}$m | 42 @ 3.3V | [−70 85] | 1.52 V | 10 | −44 dB @ 1 MHz | 1.7∼3.3 | 1.11 $\mathsf{\mu}$W | 0.06 | - |

This work $\#2$ | 0.35 $\mathsf{\mu}$m | 70 @ 3.3 V | [10 160] | 1.395 V | 9.33 | −44.8 dB @ 1 MHz | 1.6∼3.3 | 1.34 $\mathsf{\mu}$W | 0.044 | - |

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**MDPI and ACS Style**

Navidi, M.M.; Graham, D.W.
A Low-Power Voltage Reference Cell with a 1.5 V Output. *J. Low Power Electron. Appl.* **2018**, *8*, 19.
https://doi.org/10.3390/jlpea8020019

**AMA Style**

Navidi MM, Graham DW.
A Low-Power Voltage Reference Cell with a 1.5 V Output. *Journal of Low Power Electronics and Applications*. 2018; 8(2):19.
https://doi.org/10.3390/jlpea8020019

**Chicago/Turabian Style**

Navidi, Mir Mohammad, and David W. Graham.
2018. "A Low-Power Voltage Reference Cell with a 1.5 V Output" *Journal of Low Power Electronics and Applications* 8, no. 2: 19.
https://doi.org/10.3390/jlpea8020019