Selected Papers from IEEE S3S Conference 2017

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Guest Editor
ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
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Special Issue Information

Dear Colleagues,

For more than two decades, low-power consumption has been paramount for integrated circuits (ICs) and systems-on-a-chip (SoCs). In modern sub-100 nm technologies, low-power design flows have matured with techniques, such as clock/power gating, multi-Vt/Vdd assignment, and dynamic frequency/voltage scaling, being considered as mainstream. However, further power savings are still needed for extremely power-constrained applications, such as green computing, mobile wireless communications, IoT sensor nodes, and biomedical devices. Feasible ways of achieving further power savings include, for example, sub-threshold and ultra-low-voltage operation, SOI technology and circuits, and 3-D and heterogeneous integration. The 2017 IEEE Unified S3S (SOI-3D-SubVt) Conference event gathered researchers studying the aforementioned three topics to share their views and advances regarding lower-power and more efficient ICs and SoCs.

This Special Issue of JLPEA is the seventh Special Issue dedicated to selected papers from the IEEE S3S Conference 2017 held in Hyatt Regency, San Francisco Airport, CA, 16–19 October, 2017. Extended versions of papers presented at the conference will be invited for submission to this special issue. A selection of the invited papers will be made based on their low-power content and their scientific/technical excellence.

Prof. Dr. David Bol
Dr. Steven A. Vitale
Guest Editors

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

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Keywords

  • ultra-low voltage circuits and design techniques
  • SOI-specific circuits and design techniques
  • 3-D and heterogeneous system integration
  • memory design
  • analog and RF technologies and circuits
  • transistor mitigation
  • ultra-low-power computation
  • energy harvesting techniques
  • implantable and handheld biomedical devices
  • IoT sensor nodes

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Published Papers (1 paper)

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Research

16 pages, 4820 KiB  
Article
0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)
by Uzi Zangi, Neil Feldman, Tzach Hadas, Noga Dayag, Joseph Shor and Alexander Fish
J. Low Power Electron. Appl. 2018, 8(2), 14; https://doi.org/10.3390/jlpea8020014 - 9 May 2018
Cited by 5 | Viewed by 8807
Abstract
An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core [...] Read more.
An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312 K–80 MHz. A number of unique low voltage digital libraries, comprising of approximately 300 logic cells and sequential elements, were used for the MCU SOC design. On-die silicon sensors were utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions, and also to resolve yield and life time problems, while operating at low voltages. A First Fail (FFail) mechanism, which can be digitally and linearly controlled with up to 8 bits, detects the failing SOC voltage at a given frequency. The core operates between 0.45–1.1 V volts with a direct battery connection for an input voltage of 1.6–3.6 V. Measurement results show that the peak energy efficiency is 18μW/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3–5× improved current/DMIPS (Dhrystone Million Instructions per second) compared to the next best chip. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2017)
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