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Open AccessArticle

Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters

1
Barcelona Supercomputing Center, Barcelona 08034, Spain
2
Department of Physics and Earth Sciences, University of Ferrara and INFN, Ferrara 44122, Italy
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Author to whom correspondence should be addressed.
This paper is an extended version of our paper published in the Proceedings of the ParCo 2017: Mini-symposium on Energy Aware Scientific Computing on Low Power and Heterogeneous Architectures, Bologna, Italy, 12–15 September 2017.
J. Low Power Electron. Appl. 2018, 8(2), 13; https://doi.org/10.3390/jlpea8020013
Received: 31 March 2018 / Revised: 29 April 2018 / Accepted: 3 May 2018 / Published: 4 May 2018
Performance analysis tools allow application developers to identify and characterize the inefficiencies that cause performance degradation in their codes, allowing for application optimizations. Due to the increasing interest in the High Performance Computing (HPC) community towards energy-efficiency issues, it is of paramount importance to be able to correlate performance and power figures within the same profiling and analysis tools. For this reason, we present a performance and energy-efficiency study aimed at demonstrating how a single tool can be used to collect most of the relevant metrics. In particular, we show how the same analysis techniques can be applicable on different architectures, analyzing the same HPC application on a high-end and a low-power cluster. The former cluster embeds Intel Haswell CPUs and NVIDIA K80 GPUs, while the latter is made up of NVIDIA Jetson TX1 boards, each hosting an Arm Cortex-A57 CPU and an NVIDIA Tegra X1 Maxwell GPU. View Full-Text
Keywords: performance analysis tools; power drain; energy to solution; paraver; GPU; cluster, High-Performance Computing performance analysis tools; power drain; energy to solution; paraver; GPU; cluster, High-Performance Computing
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Mantovani, F.; Calore, E. Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters. J. Low Power Electron. Appl. 2018, 8, 13.

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