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JLPEA
Special Issues
Energy Aware Scientific Computing on Low Power and Heterogeneous Architectures
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Energy Aware Scientific Computing on Low Power and Heterogeneous Architectures

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 March 2018) | Viewed by 25721

Special Issue Editors

Prof. Dr. Daniele Cesini

E-Mail Website
Guest Editor
INFN-CNAF, 40127 Bologna, Italy
Interests: distributed architectures; low power processors; HPC hybrid systems
Prof. Dr. Schifano Sebastiano Fabio

E-Mail Website
Guest Editor
Dipartimento di Matematica e Informatica, Università di Ferrara, 44122 Ferrara, Italy
Interests: computer science; high performance computing; computational physics; big data; data acquisition and processing

Special Issue Information

Dear colleagues,

Energy consumption is becoming one of the most relevant issue for computing platforms running scientific applications and workloads. The use of energy-efficient processors, ranging from many-core architectures, like GP-GPU and Xeon-Phi, to Systems-on-Chip (SoCs) is required to obtain a high performance-per-watt ratio. However, on such systems, careful programming and optimization are needed to reach a high level of computing performances. The driving forces of high computational power demands, power consumption limitations and cost effectiveness are, in fact, leading to a convergence of the scientific computing and mobile/embedded sectors, historically very isolated and confined to specific markets. This Special Issue provides a selection of papers concerning energy aware computing (and storage) on high-end heterogeneous systems, as well as on off-the-shelf low-power Systems-on-Chip, originally designed for the embedded and mobile markets.

Prof. Dr. Daniele Cesini
Prof. Dr. Schifano Sebastiano Fabio
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

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Published Papers (3 papers)

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Research

15 pages, 1832 KiB  
Article
Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors
by Enrico Calore, Alessandro Gabbana, Sebastiano Fabio Schifano and Raffaele Tripiccione
J. Low Power Electron. Appl. 2018, 8(2), 18; https://doi.org/10.3390/jlpea8020018 - 11 Jun 2018
Cited by 9 | Viewed by 7886
Abstract
Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most [...] Read more.
Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this work, we focus on the computing and energy performance of the Knights Landing Xeon Phi, the latest Intel many-core architecture processor for HPC applications. We consider the 64-core Xeon Phi 7230 and profile its performance and energy efficiency using both its on-chip MCDRAM and the off-chip DDR4 memory as the main storage for application data. As a benchmark application, we use a lattice Boltzmann code heavily optimized for this architecture and implemented using several different arrangements of the application data in memory (data-layouts, in short). We also assess the dependence of energy consumption on data-layouts, memory configurations (DDR4 or MCDRAM) and the number of threads per core. We finally consider possible trade-offs between computing performance and energy efficiency, tuning the clock frequency of the processor using the Dynamic Voltage and Frequency Scaling (DVFS) technique. Full article
(This article belongs to the Special Issue Energy Aware Scientific Computing on Low Power and Heterogeneous Architectures)
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13 pages, 569 KiB  
Article
Optimization of Finite-Differencing Kernels for Numerical Relativity Applications
by Roberto Alfieri, Sebastiano Bernuzzi, Albino Perego and David Radice
J. Low Power Electron. Appl. 2018, 8(2), 15; https://doi.org/10.3390/jlpea8020015 - 25 May 2018
Cited by 4 | Viewed by 7876
Abstract
A simple optimization strategy for the computation of 3D finite-differencing kernels on many-cores architectures is proposed. The 3D finite-differencing computation is split direction-by-direction and exploits two level of parallelism: in-core vectorization and multi-threads shared-memory parallelization. The main application of this method is to [...] Read more.
A simple optimization strategy for the computation of 3D finite-differencing kernels on many-cores architectures is proposed. The 3D finite-differencing computation is split direction-by-direction and exploits two level of parallelism: in-core vectorization and multi-threads shared-memory parallelization. The main application of this method is to accelerate the high-order stencil computations in numerical relativity codes. Our proposed method provides substantial speedup in computations involving tensor contractions and 3D stencil calculations on different processor microarchitectures, including Intel Knight Landing. Full article
(This article belongs to the Special Issue Energy Aware Scientific Computing on Low Power and Heterogeneous Architectures)
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14 pages, 667 KiB  
Article
Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters
by Filippo Mantovani and Enrico Calore
J. Low Power Electron. Appl. 2018, 8(2), 13; https://doi.org/10.3390/jlpea8020013 - 4 May 2018
Cited by 27 | Viewed by 9420
Abstract
Performance analysis tools allow application developers to identify and characterize the inefficiencies that cause performance degradation in their codes, allowing for application optimizations. Due to the increasing interest in the High Performance Computing (HPC) community towards energy-efficiency issues, it is of paramount importance [...] Read more.
Performance analysis tools allow application developers to identify and characterize the inefficiencies that cause performance degradation in their codes, allowing for application optimizations. Due to the increasing interest in the High Performance Computing (HPC) community towards energy-efficiency issues, it is of paramount importance to be able to correlate performance and power figures within the same profiling and analysis tools. For this reason, we present a performance and energy-efficiency study aimed at demonstrating how a single tool can be used to collect most of the relevant metrics. In particular, we show how the same analysis techniques can be applicable on different architectures, analyzing the same HPC application on a high-end and a low-power cluster. The former cluster embeds Intel Haswell CPUs and NVIDIA K80 GPUs, while the latter is made up of NVIDIA Jetson TX1 boards, each hosting an Arm Cortex-A57 CPU and an NVIDIA Tegra X1 Maxwell GPU. Full article
(This article belongs to the Special Issue Energy Aware Scientific Computing on Low Power and Heterogeneous Architectures)
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