Special Issue "CMOS Low Power Design"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 July 2018).

Special Issue Editors

Dr. Aatmesh Shrivastava
E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
Interests: ultra low power; mixed signal circuits; power management; clock sources; i/o
Special Issues and Collections in MDPI journals
Dr. Jie Gu
E-Mail Website
Guest Editor
Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA
Interests: VLSI Design; Mixed-signal Design; Emerging Technology Integration; Computer Architecture

Special Issue Information

Dear Colleagues,

The exponential growth of interconnected devices in the age internet-of-things (IoT) is leading to a significant research challenges to develop new ultra-low power devices that reside at the edge. These devices need to have ultra-low power sensing capability, need to operate from harvested energy, need to have compute ability at the edge to reduce the amount of data, and need robust security features to prevent data theft and malicious hardware attacks.

At circuit level, new ultra-low power circuit design techniques for a variety of circuit blocks such as Analog front-end (AFE), Analog-to-digital converter (ADC), filter design etc. The new energy harvesting and power management techniques are leading to the development ultra-low power, lower voltage, energy harvesting circuits, new circuit design of analog and digital LDOs, current and reference voltage design. At system level, we need to incorporate compute ability to extract relevant information to cut down the deluge of data as cut down power spent in RF communication.

Further, IoT devices are widely distributed in our environment and are easy to access which makes them vulnerable to security risks. Various ultra-low power circuits and system design techniques with counter measures such as physically unclonable functions (PUF), side-channel leakage resilient circuit techniques are being discussed and integrated in IoT devices.

Authors are invited to submit Regular papers following the JLPEA submission guidelines, within the remit of this Special Issue call. Topics include but are not limited to.

  • Energy harvesting and power management circuit for IoT devices.
  • Circuits and systems for ultra-low voltage, energy and standby power consumption.
  • Highly power-efficient circuits for digital and analog-computing elements.
  • Reconfigurable system architecture.
  • IoT security features to including encryption and authentication.
  • Circuits, systems and methods for on-chip machine learning and feature extraction.
  • Emerging Technology

Dr. Aatmesh Shrivastava
Dr. Jie Gu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Ultra-low Power
  • IoT
  • Sensing
  • Mixed-Signal
  • Energy Harvesting
  • Physically Unclonable Function
  • Encryption

Published Papers (10 papers)

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Research

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Open AccessArticle
Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors
J. Low Power Electron. Appl. 2018, 8(3), 28; https://doi.org/10.3390/jlpea8030028 - 24 Aug 2018
Abstract
Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM [...] Read more.
Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property i n near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis
J. Low Power Electron. Appl. 2018, 8(3), 27; https://doi.org/10.3390/jlpea8030027 - 17 Aug 2018
Cited by 2
Abstract
This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of [...] Read more.
This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis
J. Low Power Electron. Appl. 2018, 8(3), 25; https://doi.org/10.3390/jlpea8030025 - 30 Jul 2018
Cited by 2
Abstract
In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a [...] Read more.
In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
A Survey of Low Voltage and Low Power Amplifier Topologies
J. Low Power Electron. Appl. 2018, 8(3), 22; https://doi.org/10.3390/jlpea8030022 - 23 Jun 2018
Cited by 2
Abstract
Reducing voltage supply is one of the most effective way to reduce the power consumption, but, on the other hand it is a challenging choice for the analog designers. In this paper, different topologies, well-suited for low voltage and ultra-low voltage supply, are [...] Read more.
Reducing voltage supply is one of the most effective way to reduce the power consumption, but, on the other hand it is a challenging choice for the analog designers. In this paper, different topologies, well-suited for low voltage and ultra-low voltage supply, are depicted, investigated, designed in the same standard 180 nm technology and compared, highlighting the benefits and the possible applications. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
A Low-Power Voltage Reference Cell with a 1.5 V Output
J. Low Power Electron. Appl. 2018, 8(2), 19; https://doi.org/10.3390/jlpea8020019 - 14 Jun 2018
Cited by 1
Abstract
A low-power voltage reference cell for system-on-a-chip applications is presented in this paper. The proposed cell uses a combination of standard transistors and thick-oxide transistors to generate a voltage above 1 V. A design procedure is also presented for minimizing the temperature coefficient [...] Read more.
A low-power voltage reference cell for system-on-a-chip applications is presented in this paper. The proposed cell uses a combination of standard transistors and thick-oxide transistors to generate a voltage above 1 V. A design procedure is also presented for minimizing the temperature coefficient (TC) of the reference voltage. This circuit was fabricated in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. It generates a 1.52 V output with a TC of 42 ppm/C from −70 C to 85 C while consuming only 1.11 μW. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
A Sub-50 µm2, Voltage-Scalable, Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring
J. Low Power Electron. Appl. 2018, 8(2), 16; https://doi.org/10.3390/jlpea8020016 - 30 May 2018
Abstract
This paper presents an on-chip temperature sensor circuit for dynamic thermal management in VLSI systems. The sensor directly senses the threshold voltage that contains temperature information using a single PMOS device. This simple structure enables the sensor to achieve an ultra-compact footprint. The [...] Read more.
This paper presents an on-chip temperature sensor circuit for dynamic thermal management in VLSI systems. The sensor directly senses the threshold voltage that contains temperature information using a single PMOS device. This simple structure enables the sensor to achieve an ultra-compact footprint. The sensor also exhibits high accuracy and voltage-scalability down to 0.4 V, allowing the sensor to be used in dynamic voltage frequency scaling systems without requiring extra power distribution or regulation. The compact footprint and voltage scalability enables our proposed sensor to be implemented in a digital standard-cell format, allowing aggressive sensor placement very close to target hotspots in digital blocks. The proposed sensor frontend prototyped in a 65 nm CMOS technology has a footprint of 30.1 µm2, 3σ-error of ±1.1 °C across 0 to 100 °C after one temperature point calibration, marking a significant improvement over existing sensors designed for dynamic thermal management in VLSI systems. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle
An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis
J. Low Power Electron. Appl. 2018, 8(2), 10; https://doi.org/10.3390/jlpea8020010 - 16 Apr 2018
Cited by 1
Abstract
This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the [...] Read more.
This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Review

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Open AccessReview
Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency
J. Low Power Electron. Appl. 2018, 8(4), 34; https://doi.org/10.3390/jlpea8040034 - 02 Oct 2018
Cited by 3
Abstract
The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software [...] Read more.
The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessReview
A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things
J. Low Power Electron. Appl. 2018, 8(2), 21; https://doi.org/10.3390/jlpea8020021 - 15 Jun 2018
Cited by 1
Abstract
This paper presents a top-down methodology for designing battery-less systems for the Internet-of-Things (IoT). We start by extracting features from a target IoT application and the environment in which it will be deployed. We then present strategies to translate these features into design [...] Read more.
This paper presents a top-down methodology for designing battery-less systems for the Internet-of-Things (IoT). We start by extracting features from a target IoT application and the environment in which it will be deployed. We then present strategies to translate these features into design choices that optimize the system and improve its reliability. We look into how to use these features to build the digital sub-system by determining the blocks to implement, the digital architecture, the clock rate of the system, the memory capacity, and the low power states. We also review how these features impact the choice of energy harvesting power management units. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessReview
Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters
J. Low Power Electron. Appl. 2018, 8(2), 12; https://doi.org/10.3390/jlpea8020012 - 30 Apr 2018
Cited by 3
Abstract
This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of [...] Read more.
This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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