Search Results (16)

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article

In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (C_gd) to the gate-to-source capacitance (C_gs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and deep double-trench MOSFET (DDT-MOS), is demonstrated to have an increase of 200 V and 50 V in the breakdown voltage (BV), decreases of 21.8% and 10% in the specific on-resistance (R_on,sp), a reduction of about 1 V in the induced crosstalk voltage, and lower switching loss. Additionally, the trade-off between the resistance of the JFET region (R_JFET) and the electric field in the gate oxide (E_ox) is studied for a step trench and a deep trench. The improved performances suggest that a step trench is a competitive option in advanced device design. Full article

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (V_F) at I_S = 100 A/cm², which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (E_mox). Additionally, the gate–drain capacitance (C_gd) and gate–drain charge (Q_gd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater R_on,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications. Full article

A 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation, and reduce switching loss. An N type base region under the trench dummy gate provides a low barrier path to suppress hole injection during the reverse conduction operation. The reverse conduction voltage V_ON is reduced to 1.11 V, and the reverse recovery charge (Q_RR) is reduced to 1.22 μC/cm². The gate-to-drain capacitance (C_GD) and gate-to-source capacitance (C_GS) of the UD-MOS are also reduced to improve switching loss due to the thick oxide layer between the trench gate and dummy gate. The proposed device exhibits an excellent loss-related figure of merit (FOM). It provides a high-voltage SiC MOSFET prototype with potential performance advantages for voltage source converter-based high voltage direct current applications. Full article

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (R_on,sp). The lateral spacing between the trench sidewall and N-implanted region (W_sp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the W_sp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (C_gd) and gate-to-drain charge (Q_gd) are also investigated. It is observed that both C_gd and Q_gd decrease as the W_sp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in C_gd, a 38% decrease in Q_gd, and a 41% reduction in Q_gd × R_on,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure. Full article

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (t_sc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (R_on,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Q_gd) and gate-drain capacitance (C_gd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process. Full article

A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge (Q_GD) of the proposed device is 20 nC/cm², and the reverse-transfer capacitance (C_GD) is 14 pF/cm², which are lower than the Q_GD of 230 nC/cm² and the C_GD of 105 pF/cm² for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained. Full article

In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons appears because of the LBD; thus, a path that makes it easier for electrons to transfer from the N+ source to the drift region is provided, finally eliminating the bipolar degradation of the body diode. At the same time, the LBD integrated in the P-well region weakens the scattering effect of interface states on electrons. Compared with the gate p-shield trench 4H-SiC MOSFET (GPMOS), the reverse on-voltage (V_F) is reduced from 2.46 V to 1.54 V; the reverse recovery charge (Q_rr) and the gate-to-drain capacitance (C_gd) are 28% and 76% lower than those of the GPMOS, respectively. The turn-on and turn-off losses of the DT-LBDMOS are reduced by 52% and 35%. The specific on-resistance (R_ON,sp) of the DT-LBDMOS is reduced by 34% due to the weaker scattering effect of interface states on electrons. The HF-FOM (HF-FOM = R_ON,sp × C_gd) and the P-FOM (P-FOM = BV²/R_ON,sp) of the DT-LBDMOS are both improved. Using the unclamped inductive switching (UIS) test, we evaluate the avalanche energy of devices and the avalanche stability. The improved performances suggest that DT-LBDMOS can be harnessed in practical applications. Full article

In this paper, DC, transient, and RF performances among AlGaN/GaN HEMTs with a no field plate structure (basic), a conventional gate field plate structure (GFP), and a double floating field plate structure (2FFP) were studied by utilizing SILVACO ATLAS 2D device technology computer-aided design (TCAD). The peak electric fields under the gate in drain-side can be alleviated effectively in 2FFP devices, compared with basic and GFP devices, which promotes the breakdown voltage (BV) and suppresses the current collapse phenomenon. As a result, the ON-resistance increase caused by the current collapse phenomena is dramatically suppressed in 2FFP ~19.9% compared with GFP ~49.8% when a 1 ms duration pre-stress was applied with V_ds = 300 V in the OFF-state. Because of the discontinuous FP structure, more electric field peaks appear at the edge of the FFP stacks, which leads to a higher BV of ~454.4 V compared to the GFP ~394.3 V and the basic devices ~57.6 V. Moreover, the 2FFP structure performs lower a parasitic capacitance of C_gs = 1.03 pF and C_gd = 0.13 pF than those of the GFP structure (i.e., C_gs = 1.89 pF and C_gd = 0.18 pF). Lower parasitic capacitances lead to a much higher cut-off frequency (f_t) of 46 GHz and a maximum oscillation frequency (f_max) of 130 GHz than those of the GFP structure (i.e., f_t = 27 GHz and f_max = 93 GHz). These results illustrate the superiority of the 2FFP structure for RF GaN HEMT and open up enormous opportunities for integrated RF GaN devices. Full article

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (C_gd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (E_ox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the C_gd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (V_th) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations. Full article

A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (E_MOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (C_GD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET. Full article

In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (t_co) of MCD can be set to very thin while achieving a low maximum oxide electric field (E_MOX) under 3 MV/cm. Therefore, the turn-on voltage (V_F) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (t_rr) and the reverse recovery charge (Q_rr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (R_ON), the MCD SJ-MOSFET shows very low input capacitance (C_ISS) and gate to drain capacitance (C_GD) due to the reduced active gate. Therefore, significantly improved figures of merit R_ON × C_GD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (E_SW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (t_SC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V). Full article

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (C_gd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP₁dB of the designed mixer is 4.1 dBm and IP₁dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm${}^2$. Full article

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (C_GD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (R_ON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (C_GD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = R_ON,SP × C_GD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an E_MOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications. Full article

In this paper, the effect of electron irradiation fluence on direct current (DC) and radio frequency (RF) of InP-based high electron mobility transistors (HEMTs) was investigated comprehensively. The devices were exposed to a 1 MeV electron beam with varied irradiation fluences from 1 × 10¹⁴ cm⁻², 1 × 10¹⁵ cm⁻², to 1 × 10¹⁶ cm⁻². Both the channel current and transconductance dramatically decreased as the irradiation fluence rose up to 1 × 10¹⁶ cm⁻², whereas the specific channel on-resistance (R_on) exhibited an apparent increasing trend. These changes could be responsible for the reduction of mobility in the channel by the irradiation-induced trap charges. However, the kink effect became weaker with the increase of the electron fluence. Additionally, the current gain cut-off frequency (f_T) and maximum oscillation frequency (f_max) demonstrated a slightly downward trend as the irradiation fluence rose up to 1 × 10¹⁶ cm⁻². The degradation of frequency properties was mainly due to the increase of gate-drain capacitance (C_GD) and the ratio of gate-drain capacitance and gate-source capacitance (C_GD/C_GS). Moreover, the increase of R_on may be another important factor for f_max reduction. Full article