A Novel 6500 V SiC Trench MOSFET with Integrated Unipolar Diode for Improved Third Quadrant and Switching Characteristics

A 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation, and reduce switching loss. An N type base region under the trench dummy gate provides a low barrier path to suppress hole injection during the reverse conduction operation. The reverse conduction voltage VON is reduced to 1.11 V, and the reverse recovery charge (QRR) is reduced to 1.22 μC/cm2. The gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) of the UD-MOS are also reduced to improve switching loss due to the thick oxide layer between the trench gate and dummy gate. The proposed device exhibits an excellent loss-related figure of merit (FOM). It provides a high-voltage SiC MOSFET prototype with potential performance advantages for voltage source converter-based high voltage direct current applications.


Introduction
The voltage source converter-based high-voltage direct current (VSC-HVDC) transmission with high flexibility and controllability is a key approach to the construction of a high-proportion clean energy grid.The high-voltage (6500 V and above) SiC MOSFET is a promising candidate for VSC-HVDC transmission to increase power efficiency and reduce the volume of the system [1][2][3].In the VSC, the freewheeling diode of SiC MOS-FET operates during the dead time period.However, the utilization of the integrated PN body diode causes potential issues.Firstly, the reverse recovery charge Q RR and reverse conduction voltage V ON considerably increase loss.Secondly, the basic plane dislocations (BPDs) generate stacking faults (SFs) in the drift region by absorbing the energy from charge recombination [4], which degrades the V ON and leakage current of SiC MOSFET [5].For the 6500 V SiC MOSFET with a thicker drift region, many more SFs could be generated based on same initial BPDs density, spelling more serious bipolar degradation issues [6].
To prevent SiC MOSFET bipolar degradation issues, a common solution is utilizing the externally antiparallel Schottky barrier diode (SBD) for freewheeling operation [7], but this increases the parasitic parameters and size of the MOSFETs-based power module [8].However, for the monolithic integrated diode schemes, SBD-integrated MOSFETs have been reported [9][10][11] and the source-controlled channel-diode-embedded SiC MOSFETs have been demonstrated [12,13], whereas Schottky contact and the uneven gate oxide layer-related reliability issues have yet to be introduced [14][15][16][17].Gate-controlled channeldiode-embedded SiC MOSFETs have also been fabricated [18][19][20], which allow the forward and reverse conduction currents to share the same MOS-channel path.However, this brings a huge challenge to achieving a better trade-off between low reverse conduction voltage and reasonable threshold voltage [18].
In this paper, a 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation issue, and reduce switching loss.Compared with the asymmetric trench MOSFET (C-MOS), the performance with its operation mechanism of UD-MOS is demonstrated by numerical simulations, involving doping-dependent mobility, high-field saturation mobility, Shockley-Read-Hall (SRH) recombination, Auger recombination, incomplete ionization of impurities, and impact ionization models.

Device Structure and Mechanism
The schematic cross-section view of the 6500 V SiC C-MOS and UD-MOS is shown in Figure 1.Compared with the C-MOS, the polysilicon gate of UD-MOS splits into two parts with a thick oxide layer.The left one is the true gate electrically connected to the gate electrode, while the right one is the dummy gate electrically connected to the source electrode.An N type region (i.e., N base region) beneath the dummy gate for electrons from the CSL region to N+ region, forms a unipolar diode (UD) as illustrated in Figure 1b.
layer-related reliability issues have yet to be introduced [14][15][16][17].Gate-controlled ch diode-embedded SiC MOSFETs have also been fabricated [18][19][20], which allow t ward and reverse conduction currents to share the same MOS-channel path.Ho this brings a huge challenge to achieving a better trade-off between low reverse c tion voltage and reasonable threshold voltage [18].
In this paper, a 6500 V SiC trench MOSFET with integrated unipolar diode (UD is proposed to improve reverse conduction characteristics, suppress bipolar degra issue, and reduce switching loss.Compared with the asymmetric trench MOSF MOS), the performance with its operation mechanism of UD-MOS is demonstra numerical simulations, involving doping-dependent mobility, high-field saturati bility, Shockley-Read-Hall (SRH) recombination, Auger recombination, incomple zation of impurities, and impact ionization models.

Device Structure and Mechanism
The schematic cross-section view of the 6500 V SiC C-MOS and UD-MOS is in Figure 1.Compared with the C-MOS, the polysilicon gate of UD-MOS splits in parts with a thick oxide layer.The left one is the true gate electrically connected to t electrode, while the right one is the dummy gate electrically connected to the sour trode.An N type region (i.e., N base region) beneath the dummy gate for electron the CSL region to N+ region, forms a unipolar diode (UD) as illustrated in Figure For the zero-bias condition, the potential barrier distribution of the integrated lar diode of UD-MOS is shown in Figure 2. Compared with the body diode of C-M decrease of potential barrier from the P+ region to the SiC/SiO2 interface (i.e., alo A′-A of Figure 1) makes a relatively low potential barrier (i.e., VUD) for electrons ported from the CSL to N+ region.It should be noted that the VUD is still relatively than the potential barrier of the CSL region and the N+ region as shown in Figure other words, the electrons cannot flow through the N base region to the N+ region this condition.For the zero-bias condition, the potential barrier distribution of the integrated unipolar diode of UD-MOS is shown in Figure 2. Compared with the body diode of C-MOS, the decrease of potential barrier from the P+ region to the SiC/SiO 2 interface (i.e., along line A -A of Figure 1) makes a relatively low potential barrier (i.e., V UD ) for electrons transported from the CSL to N+ region.It should be noted that the V UD is still relatively higher than the potential barrier of the CSL region and the N+ region as shown in Figure 2d.In other words, the electrons cannot flow through the N base region to the N+ region under this condition.
When in blocking condition, although the increasing V DS lowers the barrier of the CSL region and N base region due to the drain-induced barrier lowering effect, the V UD is still high enough to ensure blocking capability, as shown in Figure 3a.When in the reverse conduction condition, the potential barrier of the CSL region is raised by the negative V DS .Once the potential barrier of the CSL region exceeds V UD , the electrons from the CSL region can flow through the N base region to the N+ region, as shown in Figure 3b.Therefore, the potential height of the N base region determines both the blocking and reverse conduction characteristics of UD-MOS.Furthermore, a barrier height analysis model is given here to inform the design of the V UD as follows, where V P is the potential barrier height of P+ region, φ Si,SiC is the work function difference between N-type polysilicon and the P+ region, ε SiC is the dielectric constant of SiC, ε ox is the dielectric constant of oxide, q is the elementary charge, t CH is the thickness of the N base region, and N CH is the doping concentration of the N base region, respectively.According to (1), even though the negative V GS can enhance blocking capability by increasing the V UD , it also results in a high reverse conduction voltage V ON of UD-MOS.Moreover, the positive V GS even reduces the V UD to make the unipolar diode turn on, causing the UD-MOS to lose gate control when in the forward conduction condition [17].Therefore, the dummy gate not controlled by the gate electrode is introduced to guarantee both the forward and reverse conduction capability.Furthermore, the thickness t CH and doping concentration N CH of the N base region also affect the V UD .With the increase of t CH and N CH , the V UD decreases, as shown in Figure 4.The influence of breakdown voltage (BV) and V ON on t CH and N CH is discussed further in the following section.When in blocking condition, although the increasing VDS lowers the barrier of the CSL region and N base region due to the drain-induced barrier lowering effect, the VUD is still high enough to ensure blocking capability, as shown in Figure 3a.When in the reverse conduction condition, the potential barrier of the CSL region is raised by the negative VDS.
Once the potential barrier of the CSL region exceeds VUD, the electrons from the CSL region can flow through the N base region to the N+ region, as shown in Figure 3b.Therefore, the potential height of the N base region determines both the blocking and reverse con- the VUD decreases, as shown in Figure 4.The influence of breakdown voltage (BV) and VON on tCH and NCH is discussed further in the following section.

Results and Discussion
With the increase of tCH and NCH, the VON (@VGS = 0 V, IDS = −3 A/cm 2 ) and BV (@IDS = 1 × 10 −8 A/cm 2 ) of UD-MOS decrease, as shown in Figure 5.It should be noted that the VON is mainly the voltage drop of the UD (i.e., VUD) and the thick epi-layer.The thicker tCH and higher NCH bring lower VON, but also lead to premature breakdown.Therefore, considering both the VON and BV of the UD-MOS, the tCH and NCH are designed to be 170 nm and 8 × 10 16 cm −3 , respectively.The key structural parameters of the C-MOS and UD-MOS are shown in Table 1.
The effect of the N base length LCH on VUD is also discussed.With the narrowness of LCH, the potential of the N+ region influences the potential barrier of the N base as shown in Figure 6a.Although the lower VUD helps to reduce the VON, the BV is weakened at the same time, as shown in Figure 6b.

Results and Discussion
With the increase of tCH and NCH, the VON (@VGS = 0 V, IDS = −3 A/cm 2 ) and BV (@IDS = 1 × 10 −8 A/cm 2 ) of UD-MOS decrease, as shown in Figure 5.It should be noted that the VON is mainly the voltage drop of the UD (i.e., VUD) and the thick epi-layer.The thicker tCH and higher NCH bring lower VON, but also lead to premature breakdown.Therefore, considering both the VON and BV of the UD-MOS, the tCH and NCH are designed to be 170 nm and 8 × 10 16 cm −3 , respectively.The key structural parameters of the C-MOS and UD-MOS are shown in Table 1.
The effect of the N base length LCH on VUD is also discussed.With the narrowness of LCH, the potential of the N+ region influences the potential barrier of the N base as shown in Figure 6a.Although the lower VUD helps to reduce the VON, the BV is weakened at the same time, as shown in Figure 6b.

Results and Discussion
With the increase of t CH and N CH , the V ON (@V GS = 0 V, I DS = −3 A/cm 2 ) and BV (@I DS = 1 × 10 −8 A/cm 2 ) of UD-MOS decrease, as shown in Figure 5.It should be noted that the V ON is mainly the voltage drop of the UD (i.e., V UD ) and the thick epi-layer.The thicker t CH and higher N CH bring lower V ON , but also lead to premature breakdown.Therefore, considering both the V ON and BV of the UD-MOS, the t CH and N CH are designed to be 170 nm and 8 × 10 16 cm −3 , respectively.The key structural parameters of the C-MOS and UD-MOS are shown in Table 1.The effect of the N base length L CH on V UD is also discussed.With the narrowness of L CH , the potential of the N+ region influences the potential barrier of the N base as shown in Figure 6a.Although the lower V UD helps to reduce the V ON , the BV is weakened at the same time, as shown in Figure 6b.

Static Characteristics
Based on optimized tCH and NCH, the SiC C-MOS and UD-MOS have a similar BV, as shown in Figure 7.The peak electric field in the gate oxide is less than 3 MV/cm, which ensures the long-term reliability of the gate oxide, as shown in the insets of Figure 7.

Static Characteristics
Based on optimized t CH and N CH , the SiC C-MOS and UD-MOS have a similar BV, as shown in Figure 7.The peak electric field in the gate oxide is less than 3 MV/cm, which ensures the long-term reliability of the gate oxide, as shown in the insets of Figure 7.Moreover, the VON of UD-MOS is −1.1 V, while the C-MOS is −2.8 V, as shown in Figure 8a.It should be noted that the integrated unipolar diode makes for lesser hole injection into the drift region when in the reverse conduction condition, as shown in Figure 8b, which effectively avoids the risk of bipolar degradation.Moreover, the V ON of UD-MOS is −1.1 V, while the C-MOS is −2.8 V, as shown in Figure 8a.It should be noted that the integrated unipolar diode makes for lesser hole injection into the drift region when in the reverse conduction condition, as shown in Figure 8b, which effectively avoids the risk of bipolar degradation.
Moreover, the VON of UD-MOS is −1.1 V, while the C-MOS is −2.8 V, as shown in Figure 8a.It should be noted that the integrated unipolar diode makes for lesser hole injection into the drift region when in the reverse conduction condition, as shown in Figure 8b, which effectively avoids the risk of bipolar degradation.
Even though the cell pitch of the UD-MOS is slightly larger than that of the C-MOS, the conduction capability of the UD-MOS is not degraded, because its channel density no longer dominates for high voltage SiC MOSFETs.The RON of UD-MOS and C-MOS are 35.48mΩ•cm 2 and 35.00 mΩ•cm 2 , respectively (@IDS = 50 A/cm 2 ), as shown in Figure 9a.The transfer characteristic of the UD-MOS is also not degraded, which shows nearly the same VTH as the C-MOS, as shown in Figure 9b.Even though the cell pitch of the UD-MOS is slightly larger than that of the C-MOS, the conduction capability of the UD-MOS is not degraded, because its channel density no longer dominates for high voltage SiC MOSFETs.The R ON of UD-MOS and C-MOS are 35.48mΩ•cm 2 and 35.00 mΩ•cm 2 , respectively (@I DS = 50 A/cm 2 ), as shown in Figure 9a.The transfer characteristic of the UD-MOS is also not degraded, which shows nearly the same V TH as the C-MOS, as shown in Figure 9b.

Dynamic Characteristics
The reverse recovery characteristics of the body diode in the SiC C-MOS and UD-MOS are compared, as shown in Figure 10.Thanks to no extraction of minority carrier during the reverse recovery process, the peak reverse recovery current (IRRM) and reverse recovery charge (QRR) of UD-MOS are 54 A/cm 2 and 1.04 µC/cm 2 , which are significantly reduced by 76% and 81%, respectively, compared to the C-MOS (IRRM =176 A/cm 2 and QRR =5 µC/cm 2 ).

Dynamic Characteristics
The reverse recovery characteristics of the body diode in the SiC C-MOS and UD-MOS are compared, as shown in Figure 10.Thanks to no extraction of minority carrier during the reverse recovery process, the peak reverse recovery current (I RRM ) and reverse recovery charge (Q RR ) of UD-MOS are 54 A/cm 2 and 1.04 µC/cm 2 , which are significantly reduced by 76% and 81%, respectively, compared to the C-MOS (I RRM =176 A/cm 2 and Q RR =5 µC/cm 2 ).
MOS are compared, as shown in Figure 10.Thanks to no extraction of m during the reverse recovery process, the peak reverse recovery current (IRR recovery charge (QRR) of UD-MOS are 54 A/cm 2 and 1.04 µC/cm 2 , which ar reduced by 76% and 81%, respectively, compared to the C-MOS (IRRM =176 A =5 µC/cm 2 ).Moreover, the dummy gate of the UD-MOS reduces the effective ove between gate and drain terminals, so that the gate-to-drain capacitance pF/cm 2 (@VDS = 3600 V), which is reduced by 9.5% compared with the C-MO due to the thick oxide layer between the trench gate and dummy gate as we smaller overlapping area, the gate-to-source capacitance (CGS) of the UD nF/cm 2 , which is reduced by 52%.Accordingly, thanks to the smaller CGD an MOS has a lower gate charge (QG) of 566 nC/cm 2 (@VGS = 0 V-18 V) and charge (QGD) of 109 nC/cm 2 , as shown in Figure 11.Furthermore, consideri and dynamic capability, the UD-MOS exhibits a better loss-related figure o i.e., RON × QGD [21]) of 3.87 mΩ•µC, which is 8.7% lower than that of the C-M The switching waveforms of the SiC C-MOS and DP-MOS are as show Benefitting from the reduced capacitances, the UD-MOS has lower turn-on turn-off loss (EOFF) of 3.80 mJ/cm 2 and 3.36 mJ/cm 2 , which are 34% and 17% l of the C-MOS, respectively.Moreover, the dummy gate of the UD-MOS reduces the effective overlapping area between gate and drain terminals, so that the gate-to-drain capacitance (C GD ) is 4.01 pF/cm 2 (@V DS = 3600 V), which is reduced by 9.5% compared with the C-MOS.Meanwhile, due to the thick oxide layer between the trench gate and dummy gate as well as a slightly smaller overlapping area, the gate-to-source capacitance (C GS ) of the UD-MOS is 18.1 nF/cm 2 , which is reduced by 52%.Accordingly, thanks to the smaller C GD and C GS , the UD-MOS has a lower gate charge (Q G ) of 566 nC/cm 2 (@V GS = 0 V-18 V) and gate-to-drain charge (Q GD ) of 109 nC/cm 2 , as shown in Figure 11.Furthermore, considering conduction and dynamic capability, the UD-MOS exhibits a better loss-related figure of merit (FOM, i.e., R ON × Q GD [21]) of 3.87 mΩ•µC, which is 8.7% lower than that of the C-MOS.The switching waveforms of the SiC C-MOS and DP-MOS are as shown in Figure 12.Benefitting from the reduced capacitances, the UD-MOS has lower turn-on loss (E ON ) and turn-off loss (E OFF ) of 3.80 mJ/cm 2 and 3.36 mJ/cm 2 , which are 34% and 17% lower than that of the C-MOS, respectively.One feasible process flow of the UD-MOS is presented, including (a) epitaxial growing, P body implantation, N+ source region implantation, trench etch and P+ region implantation, (b) N+ region and N base region implantation, (c) thermal oxidation and polysilicon gate deposition, (d) polysilicon etch, (e) isolated oxidation deposition and (f) metallization, as shown in Figure 13.Finally, Table 2 compares the main characteristics of the SiC UD-MOS and the C-MOS.The SiC UD-MOS exhibits superior performance due to the unipolar diode.

Conclusions
A novel 6500 V SiC trench UD-MOS is proposed with improved reverse conduction and switching characteristics.The grounded dummy gate causes the unipolar diode of the SiC UD-MOS to reduce V ON to 1.1 V, which avoids the risk of bipolar degradation and reduces the parasitic capacitances with lower switching loss.The proposed UD-MOS provides a promising device prototype in VSC applications for HVDC transmission.

Figure 1 .
Figure 1.Schematic cross-section view of the 6500 V SiC (a) C-MOS and (b) UD-MOS.

Figure 1 .
Figure 1.Schematic cross-section view of the 6500 V SiC (a) C-MOS and (b) UD-MOS.

Figure 2 .
Figure 2. Potential barrier distribution at zero-bias (VGS = 0 V and VDS = 0 V) condition.(a) Along line A-A′ of the SiC C-MOS, (b) along line A-A′ of the SiC UD-MOS, (c) along line B-B′ of the SiC C-MOS, and (d) along line B-B′ of the SiC UD-MOS.

Figure 2 .
Figure 2. Potential barrier distribution at zero-bias (V GS = 0 V and V DS = 0 V) condition.(a) Along line A-A of the SiC C-MOS, (b) along line A-A of the SiC UD-MOS, (c) along line B-B of the SiC C-MOS, and (d) along line B-B of the SiC UD-MOS.

Figure 3 .Figure 4 .
Figure 3. Potential barrier distribution along line B-B′ of the SiC UD-MOS.(a) The blocking condition and (b) the reverse conduction condition at VGS = 0 V.

Figure 3 .Figure 3 .Figure 4 .
Figure 3. Potential barrier distribution along line B-B of the SiC UD-MOS.(a) The blocking condition and (b) the reverse conduction condition at V GS = 0 V.

Figure 4 .
Figure 4. Effects of (a) N CH and (b) t CH on the potential barrier height along line A-A at zero-bias condition (V GS = V DS = 0 V).

Figure 5 .Figure 5 .
Figure 5. Effects of tCH and NCH on (a) VON and (b) BV of UD-MOS.

Figure 6 .
Figure 6.(a) Potential distribution in different L CH and (b) effect of L CH on V ON and BV.

Figure 7 .
Figure 7. Blocking characteristics of the SiC C-MOS and UD-MOS.The insets show the electric field distributions in SiC MOSFET at VDS = 6500 V.

Figure 7 .
Figure 7. Blocking characteristics of the SiC C-MOS and UD-MOS.The insets show the electric field distributions in SiC MOSFET at V DS = 6500 V.

Figure 8 .
Figure 8.(a) Reverse conduction characteristics and (b) hole density distribution of the SiC C-MOS and UD-MOS at VGS = 0 V and ISD = 50 A/cm 2 .

Figure 8 .
Figure 8.(a) Reverse conduction characteristics and (b) hole density distribution of the SiC C-MOS and UD-MOS at V GS = 0 V and I SD = 50 A/cm 2 .

Figure 9 .
Figure 9. (a) Output characteristics at VGS = 18 V and (b) transfer characteristics of the SiC C-MOS and UDMOS.

Figure 9 .
Figure 9. (a) Output characteristics at V GS = 18 V and (b) transfer characteristics of the SiC C-MOS and UDMOS.

Figure 10 .
Figure 10.Reverse recovery characteristics of the body diode in the SiC C-MOS and

Figure 10 .
Figure 10.Reverse recovery characteristics of the body diode in the SiC C-MOS and UD-MOS.

Figure 11 .
Figure 11.(a) Capacitance characteristics at V GS = 0 V, f = 1 MHz and (b) Q G for the SiC C-MOS and UD-MOS.

Figure 12 .
Figure 12.(a) Turn-on and (b) turn-off waveforms of the C-MOS and UD-MOS at V DS = 3600 V and I DS = 50 A/cm 2 .

Table 1 .
Key Structure Parameters of the SiC C-MOS and UD-MOS.

Table 2 .
Performance Comparison of the SiC C-MOS and UD-MOS.

Table 2 .
Performance Comparison of the SiC C-MOS and UD-MOS.