Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate–drain capacitance (Cgd) and gate–drain charge (Qgd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater Ron,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.


Introduction
Nowadays, silicon carbon (SiC) is widely used in many applications because of its high critical electric field and superior thermal conductivity [1,2].The SiC MOSFET has a lower on-resistance and a faster switch speed compared with the Si-insulated Gate Bipolar Translator (IGBT) [3,4].However, the body diode of the SiC MOSFET has a high on-state voltage drop of about 2-3 V because of its wide bandgap.Additionally, when the body diode operates in bipolar mode, basal plane dislocations (BPDs) and stacking faults (SFs) are generated because of the recombination energy of the electrons and holes, and these faults cover most of the junction area and cause conduction losses to increase [5][6][7][8].Thus, the SiC MOSFET usually reverse-parallels a freewheeling diode to suppress the body diode; this extra diode not only increases the package size but also increases the parasitic inductance, which limits the switching frequency of the MOSFET [9,10].
One possible way of solving this problem is to integrate a unipolar diode into the MOSFET cell-in particular, a Schottky Barrier Diode (SBD)/Junction Barrier Controlled Schottky Diode (JBS) [9,[11][12][13][14][15].A disadvantage of these integrated unipolar diodes is the increased leakage current in the blocking state for the MOSFET [16].The use of a built-in channel diode is another option that can improve the reverse-recovery characteristics of the MOSFET, showing better switching characteristics, but the reliability problem caused by thin gate oxide still needs further research [17,18].In recent research, low-barrier diodes (LBDs) have been adopted for their enhanced third-quadrant and switching performance in planar MOSFETs [19], but the planar structure limits the MOSFET's usage in high-power applications because of its wide cell pitch and its high specificity of resistance (R on,sp ).
This paper proposes a 1200 V L-shaped split-gate trench SiC MOSFET integrated with a low-barrier diode.This structure can inhibit the reverse conduction of the body 2 of 13 diode to avoid the effects of bipolar degradation and to extend the source to the bottom of the gate, forming a split gate to reduce the C rss [20][21][22] and to achieve a fast switching speed.This study was carried out with numerical TCAD, and some essential models were included such as the Fermi-Dirac, incomplete-ionization, Shockley-Reed-Hall and Auger combination, Lombardi (CVT), impact-ionization, and band-narrowing models [23][24][25].A channel mobility of 50 cm 2 /(Vs) was used [26].The structure achieved a lower V F , C gd , and Q gd and lower switching losses compared with a DT-MOS [27] and a DT-MOS with an MOS-channel diode (DTC-MOS) [18], and it also reduced the maximum oxide electric field (E mox ).

Device Structure and Mechanism
Figure 1 shows the schematic structures of the (a) DT-MOS, (b) DTC-MOS, and (c) proposed MOS.Based on the DTC-MOS, the proposed MOS turns part of the polysilicon gate to the source and extends to the bottom of the gate, forming an "L-shape" split gate.The gate-source connects to the source, so the overlap between the gate and drain decreases, which leads to a decrease in the C gd .Meanwhile, at the right half-cell, the p-base turns into an n-base, so a low-barrier diode is integrated into this structure to improve its reverse conduction.The P-shield extends to the current spreading layer (CSL), and it decreases the E mox in the blocking state and increases the BV, improving the device's reliability.

Device Structure and Mechanism
Figure 1 shows the schematic structures of the (a) DT-MOS, (b) DTC-MOS, and (c) proposed MOS.Based on the DTC-MOS, the proposed MOS turns part of the polysilicon gate to the source and extends to the bottom of the gate, forming an "L-shape" split gate.The gate-source connects to the source, so the overlap between the gate and drain decreases, which leads to a decrease in the Cgd.Meanwhile, at the right half-cell, the p-base turns into an n-base, so a low-barrier diode is integrated into this structure to improve its reverse conduction.The P-shield extends to the current spreading layer (CSL), and it decreases the Emox in the blocking state and increases the BV, improving the device's reliability.
This device is based on a 4H-SiC, with the doping concentration and thickness of the N-drift set at 8 × 10 15 cm −3 and 9 µm, respectively.The P-base region in all the devices had a doping concentration of 2 × 10 17 cm −3 and a thickness of 0.5 µm.The N-base had a doping concentration of 3 × 10 16 cm −3 and a thickness of 0.3 µm.The P-shield had a doping concentration of 2 × 10 18 cm −3 and a thickness of 0.3 µm.The CSL had a doping concentration of 8 × 10 16 cm −3 and a depth of 1.7 µm.The depth of the source trench and gate trench was 1.4 µm for both devices.The thickness of the gate oxide was 50 nm for both the N-base and P-base to improve the device reliability in the DT-MOS and proposed MOS.Considering the sufficient volume of the gate and the electric field, the distance of the oxide between the gate and gate-source and the thickness of the gate-source was 0.1 µm for the DTC-MOS and the proposed MOS.The cell pitch was 3.8 µm for the DT-MOS, and that of the other two devices was 4.2 µm.The main structure parameters of the DT-MOS, DTC-MOS, and proposed MOS are shown in Table 1.This device is based on a 4H-SiC, with the doping concentration and thickness of the N-drift set at 8 × 10 15 cm −3 and 9 µm, respectively.The P-base region in all the devices had a doping concentration of 2 × 10 17 cm −3 and a thickness of 0.5 µm.The N-base had a doping concentration of 3 × 10 16 cm −3 and a thickness of 0.3 µm.The P-shield had a doping concentration of 2 × 10 18 cm −3 and a thickness of 0.3 µm.The CSL had a doping concentration of 8 × 10 16 cm −3 and a depth of 1.7 µm.The depth of the source trench and gate trench was 1.4 µm for both devices.The thickness of the gate oxide was 50 nm for both the N-base and P-base to improve the device reliability in the DT-MOS and proposed MOS.Considering the sufficient volume of the gate and the electric field, the distance of the oxide between the gate and gate-source and the thickness of the gate-source was 0.1 µm for the DTC-MOS and the proposed MOS.The cell pitch was 3.8 µm for the DT-MOS, and that of the other two devices was 4.2 µm.The main structure parameters of the DT-MOS, DTC-MOS, and proposed MOS are shown in Table 1. Figure 2a shows the three-dimensional conduction band energy (E C ) distribution of the 4H-SiC in the proposed MOS structure at zero bias.The E C decreased from the P-shield to the N-base at the right half-cell.The high doping of the P-shield and the low doping of the N-base led to a rapid depletion of the N-base region at zero bias, preventing the formation of a conducting channel.Therefore, there was no impact on the BV at low doping concentrations.At zero bias, the E C of the N-base was lower than the P-base, allowing electrons to overcome the potential barrier at a low V ds .Figure 2b shows the E C distribution along the a-a' line (shown in Figure 1) at different V ds .As V ds decreased, the E C increased in both the N-base and CSL.However, the E C of the CSL increased faster than the N-base region.At V ds = −1 V, the potential barrier became very low, allowing electrons to overcome the potential barrier, turning on the low barrier diode.Figure 2a shows the three-dimensional conduction band energy (EC) distribution of the 4H-SiC in the proposed MOS structure at zero bias.The EC decreased from the P-shield to the N-base at the right half-cell.The high doping of the P-shield and the low doping of the N-base led to a rapid depletion of the N-base region at zero bias, preventing the formation of a conducting channel.Therefore, there was no impact on the BV at low doping concentrations.At zero bias, the EC of the N-base was lower than the P-base, allowing electrons to overcome the potential barrier at a low Vds. Figure 2b shows the EC distribution along the a-a' line (shown in Figure 1) at different Vds.As Vds decreased, the EC increased in both the N-base and CSL.However, the EC of the CSL increased faster than the N-base region.At Vds = −1 V, the potential barrier became very low, allowing electrons to overcome the potential barrier, turning on the low barrier diode.The potential barrier model for LBD in a planar MOSFET is given by [19]:

Ec(T) (eV)
where  _ and  _ are the work function and electron affinity difference between the Si and SiC. and  are the permittivity of the SiO2 and SiC.NNb is the doping concentration of the N-base.The WNb is the width of the N-base.The structure of the low barrier diode in a planar structure and trench structure is the same, being formed by the N+ polysilicon, oxide, the low doping concentration N region, and the high doping concentration P region.Although the formula was obtained for planar structures [19,28], it is The potential barrier model for LBD in a planar MOSFET is given by [19]: where φ Si_SiC and χ Si_SiC are the work function and electron affinity difference between the Si and SiC.ε OX and ε SiC are the permittivity of the SiO 2 and SiC.N Nb is the doping concentration of the N-base.The W Nb is the width of the N-base.The structure of the low barrier diode in a planar structure and trench structure is the same, being formed by the N+ polysilicon, oxide, the low doping concentration N region, and the high doping concentration P region.Although the formula was obtained for planar structures [19,28], it is also applicable to trench structures.The t c is the thickness of the oxide between the gate-source and the N-base, which is fixed at 50 nm in the proposed MOS, as it has a great influence on device reliability.The t c of the DTC-MOS was 20 nm, to easily turn on the built-in diode.From equation (1), N Nb and W Nb had an impact on the potential barrier of the LBD.Additionally, the thickness of the N-base (T Nb ) and the length of the P-shield (L Psh ) also influenced the resistance of the LBD, which in turn affects the V F .Therefore, these parameters were optimized.

Simulation Results and Analysis
Figure 3a illustrates the impact of W Nb and D Nb on the BV and V F .The solid circles represent BV values and the dashed circles represent V F values.The W Nb varied from 0.1 µm to 0.6 µm in steps of 0.1 µm.As W Nb increased, the reverse current path expanded, which led to a decrease in V F .However, the breakdown turned into a punch-through breakdown, which made the device unable to withstand high voltages.With increasing D Nb , the length of the potential barrier increased, leading to an increase in V F .In this case, a longer W Nb was required to trigger a punch-through breakdown.It is worth noting that when D Nb exceeded 0.3 µm, the leakage current of the proposed MOS became comparable to the DT-MOS, which will be further discussed later.To tradeoff the BV, V F , and leakage current, the optimal values of W Nb = 0.3 µm and D Nb = 0.3 µm were selected.
Micromachines 2024, 15, x FOR PEER REVIEW 4 of 13 also applicable to trench structures.The tc is the thickness of the oxide between the gatesource and the N-base, which is fixed at 50 nm in the proposed MOS, as it has a great influence on device reliability.The tc of the DTC-MOS was 20 nm, to easily turn on the built-in diode.From equation ( 1), NNb and WNb had an impact on the potential barrier of the LBD.Additionally, the thickness of the N-base (TNb) and the length of the P-shield (LPsh) also influenced the resistance of the LBD, which in turn affects the VF.Therefore, these parameters were optimized.

Simulation Results and Analysis
Figure 3a illustrates the impact of WNb and DNb on the BV and VF.The solid circles represent BV values and the dashed circles represent VF values.The WNb varied from 0.1 µm to 0.6 µm in steps of 0.1 µm.As WNb increased, the reverse current path expanded, which led to a decrease in VF.However, the breakdown turned into a punch-through breakdown, which made the device unable to withstand high voltages.With increasing DNb, the length of the potential barrier increased, leading to an increase in VF.In this case, a longer WNb was required to trigger a punch-through breakdown.It is worth noting that when DNb exceeded 0.3 µm, the leakage current of the proposed MOS became comparable to the DT-MOS, which will be further discussed later.To tradeoff the BV, VF, and leakage current, the optimal values of WNb = 0.3 µm and DNb = 0.3 µm were selected.Figure 3b shows the tradeoff between the BV and VF for the proposed MOS, considering different values of LPsh and NNb.As the LPsh increased from 1 µm to 1.5 µm in steps of 0.1 µm, the depletion region extended, leading to a decrease in Emox and an increase in BV.However, the current path became narrow, leading to an increase in Ron,sp and VF because of the change in the JFET resistance.With increasing NNb, the potential barrier of the low barrier diode reduced, leading to a decrease in VF.However, with high doping of NNb, the BV dropped below 1400 V, as shown for NNb = 3.5 × 10 16 cm −3 .At low NN values, the breakdown point occurred at the P-shield/N-drift junction, so the BV did not change with different NNb values.The change in NNb had no influence on Ron,sp.However, with increasing LPsh, the Ron,sp increased from 1.84 mΩ × cm −2 to 4.58 mΩ × cm −2 .In order to tradeoff BV, VF, and Ron,sp, LPsh = 1.3 µm and NNb = 3 × 10 16 cm −3 were selected, represented by the red circle in Figure 3b.
The main parameters of the gate trench are shown in Figure 4a.The thickness of the gate trench was fixed at 1.4 µm.Figure 4b shows the influence of the distance between the Figure 3b shows the tradeoff between the BV and V F for the proposed MOS, considering different values of L Psh and N Nb .As the L Psh increased from 1 µm to 1.5 µm in steps of 0.1 µm, the depletion region extended, leading to a decrease in E mox and an increase in BV.However, the current path became narrow, leading to an increase in R on,sp and V F because of the change in the JFET resistance.With increasing N Nb , the potential barrier of the low barrier diode reduced, leading to a decrease in V F .However, with high doping of N Nb , the BV dropped below 1400 V, as shown for N Nb = 3.5 × 10 16 cm −3 .At low N N values , the breakdown point occurred at the P-shield/N-drift junction, so the BV did not change with different N Nb values.The change in N Nb had no influence on R on,sp .However, with increasing L Psh , the R on,sp increased from 1.84 mΩ × cm −2 to 4.58 mΩ × cm −2 .In order to tradeoff BV, V F , and R on,sp , L Psh = 1.3 µm and N Nb = 3 × 10 16 cm −3 were selected, represented by the red circle in Figure 3b.
The main parameters of the gate trench are shown in Figure 4a.The thickness of the gate trench was fixed at 1.4 µm.Figure 4b shows the influence of the distance between the gate and the gate-source (D ox ) on the C gd and oxide electric field (E ox ).The voltage between the gate and the gate-source was set to 15 V.When D ox was 0.1 µm for both the bottom and side wall of the gate, the E ox was 1.5 MV/cm, which corresponds to the simulation results.The thickness of the gate-source (T GS ) was fixed at 0.1 µm, and the thickness of gate poly (T G ) changed as D ox increased or decreased.With increasing D ox , the BV and V F had no influence, so they are not included in Figure 4b.The D ox has little influence on C gd .Therefore, when D ox was greater than 0.1 µm, E ox was already less than 3 MV/cm.In order to facilitate subsequent simulations and ensure a sufficient volume of gate poly for adjusting the gate resistance, D ox = 0.1 µm was selected.
Micromachines 2024, 15, x FOR PEER REVIEW 5 of 13 gate and the gate-source (Dox) on the Cgd and oxide electric field (Eox).The voltage between the gate and the gate-source was set to 15 V.When Dox was 0.1 µm for both the bottom and side wall of the gate, the Eox was 1.5 MV/cm, which corresponds to the simulation results.The thickness of the gate-source (TGS) was fixed at 0.1 µm, and the thickness of gate poly (TG) changed as Dox increased or decreased.With increasing Dox, the BV and VF had no influence, so they are not included in Figure 4b.The Dox has little influence on Cgd.Therefore, when Dox was greater than 0.1 µm, Eox was already less than 3 MV/cm.In order to facilitate subsequent simulations and ensure a sufficient volume of gate poly for adjusting the gate resistance, Dox = 0.1 µm was selected.The influence of the device characteristics on TGS is shown in Figure 4c; the Dox was fixed at 0.1 µm.With increasing TGS, there was no influence on BV and VF, which is not shown in the figure.Ron,sp increased from 2.23 mΩ•cm 2 to 2.28 mΩ•cm 2 , because the CSL, oxide, and gate poly formed an MIS structure, which increased the electron concentration of the CSL during conduction; this effect weakened as TG decreased.

Gate
With increasing TGS, Cgd decreases; this is because the gate-source extends to the bottom of the gate poly, resulting in a significant decrease in the overlap between the gate electrode and drain electrode.In this case, the Cgd can be expressed as: As shown in Figure 4a, Cp is the oxide capacitance between the P-base and gate electrode, which is related to the thickness of the oxide and the overlap between the gate poly and the P-base.CPN is the junction capacitance, which is completely independent of the gate parameters, and the CPN decreases as Vds increases.When increasing TGS or Dox, the TG decreases, resulting in a decreased overlap between the gate poly and the P-base, thus causing a decrease in Cp .Meanwhile, the TG has no influence on CPN, so the Cgd will decrease.However, it is worth noting that the Cgd is already sufficiently small, and further decreasing Cp cannot significantly change the Cgd.To ensure a suitable gate resistance for device, a sufficient volume of gate poly must be considered, which cannot be reflected in a simulation.Therefore, TGS = 0.1 µm was selected for further simulations.According to Figure 4b,c, the internal parameters of the gate trench have little influence on the performance of the device when the resistance of the gate poly is not considered; this shows that the proposed MOS has a wide process window for forming the L-shape gate-source.
Figure 5a shows the leakage current and blocking voltage for the three devices.The DT-MOS and proposed MOS blocking voltage exceeded 1400 V.However, the BV of the The influence of the device characteristics on T GS is shown in Figure 4c; the D ox was fixed at 0.1 µm.With increasing T GS , there was no influence on BV and V F , which is not shown in the figure.R on,sp increased from 2.23 mΩ•cm 2 to 2.28 mΩ•cm 2 , because the CSL, oxide, and gate poly formed an MIS structure, which increased the electron concentration of the CSL during conduction; this effect weakened as T G decreased.
With increasing T GS , C gd decreases; this is because the gate-source extends to the bottom of the gate poly, resulting in a significant decrease in the overlap between the gate electrode and drain electrode.In this case, the C gd can be expressed as: As shown in Figure 4a, C p is the oxide capacitance between the P-base and gate electrode, which is related to the thickness of the oxide and the overlap between the gate poly and the P-base.C PN is the junction capacitance, which is completely independent of the gate parameters, and the C PN decreases as V ds increases.When increasing T GS or D ox , the T G decreases, resulting in a decreased overlap between the gate poly and the P-base, thus causing a decrease in C p .Meanwhile, the T G has no influence on C PN , so the C gd will decrease.However, it is worth noting that the C gd is already sufficiently small, and further decreasing C p cannot significantly change the C gd .To ensure a suitable gate resistance for device, a sufficient volume of gate poly must be considered, which cannot be reflected in a simulation.Therefore, T GS = 0.1 µm was selected for further simulations.According to Figure 4b,c, the internal parameters of the gate trench have little influence on the performance of the device when the resistance of the gate poly is not considered; this shows that the proposed MOS has a wide process window for forming the L-shape gate-source.
Figure 5a shows the leakage current and blocking voltage for the three devices.The DT-MOS and proposed MOS blocking voltage exceeded 1400 V.However, the BV of the DTC-MOS was only 1340 V.This indicates that a wide cell pitch results in a decrease in the BV, while the extended P+ shield helps to improve the BV.For the proposed MOS, the leakage current increased faster at D Nb = 0.2 µm.However, when D Nb = 0.3 µm, the BV was the same as D Nb = 0.2 µm, the leakage current decreased to the level of the DT-MOS.This is because the leakage current is related to the parameters of the N-base before breakdown and the blocking voltage is related to the P-shield/N-drift junction, where the electric field is highest in the SiC region and avalanche breakdown occurs.The electric field distribution of the three devices at 1200 V is shown in Figure 5b.The E mox was located at the bottom of the oxide for all the devices.Compared with the DT-MOS and DTC-MOS, the proposed MOS had an extended P-shield, which was able to expand the depletion layer and provide better protection effects to the oxide.As a result, the E mox was only 2.52 MV/cm, while the E mox of the other devices was higher than 4 MV/cm.With a high E mox , a Fowler-Nordheim tunneling current may be generated; this carries electrons through the oxide layer, breaking the Si-O bond over time and generating defects, leading to a full breakdown of the SiO 2 layer [29], which has a great influence on device reliability.
DTC-MOS was only 1340 V.This indicates that a wide cell pitch results in a decrease in the BV, while the extended P+ shield helps to improve the BV.For the proposed MOS, the leakage current increased faster at DNb = 0.2 µm.However, when DNb = 0.3 µm, the BV was the same as DNb = 0.2 µm, the leakage current decreased to the level of the DT-MOS.This is because the leakage current is related to the parameters of the N-base before breakdown and the blocking voltage is related to the P-shield/N-drift junction, where the electric field is highest in the SiC region and avalanche breakdown occurs.The electric field distribution of the three devices at 1200 V is shown in Figure 5b.The Emox was located at the bottom of the oxide for all the devices.Compared with the DT-MOS and DTC-MOS, the proposed MOS had an extended P-shield, which was able to expand the depletion layer and provide better protection effects to the oxide.As a result, the Emox was only 2.52 MV/cm, while the Emox of the other devices was higher than 4 MV/cm.With a high Emox, a Fowler-Nordheim tunneling current may be generated; this carries electrons through the oxide layer, breaking the Si-O bond over time and generating defects, leading to a full breakdown of the SiO2 layer [29], which has a great influence on device reliability.The I-V characteristic is shown in Figure 6a.In forward conduction, the Ron,sp of the DT-MOS and DTC-MOS was smaller than for the proposed MOS; this is because the DT-MOS has two channel paths for conduction, and because both DT-MOS and DTC-MOS do not extend the P-shield, which increases JFET resistance.With a low barrier diode, the VF of the proposed MOS decreased significantly.The VF was 2.85 V, 2.63 V, and 0.85 V at 100 A/cm 2 for the DT-MOS, DTC-MOS, and proposed MOS, respectively.The current vector of the forward and reverse conduction is also shown in Figure 6a.It can be seen that there was only one current path for both conduction conditions.The current flows from the N+ region through the N-base to the drift region in reverse conduction, while the current flows from the drift region through the P-base to the N+ region in forward conduction.Figure 6b shows the hole concentration at Is = 100 A/cm 2 of all the devices.In reverse conduction, the drift region of the DT-MOS obtained a high concentration of holes, which causes bipolar degradation [5].The I-V characteristic is shown in Figure 6a.In forward conduction, the R on,sp of the DT-MOS and DTC-MOS was smaller than for the proposed MOS; this is because the DT-MOS has two channel paths for conduction, and because both DT-MOS and DTC-MOS do not extend the P-shield, which increases JFET resistance.With a low barrier diode, the V F of the proposed MOS decreased significantly.The V F was 2.85 V, 2.63 V, and 0.85 V at 100 A/cm 2 for the DT-MOS, DTC-MOS, and proposed MOS, respectively.The current vector of the forward and reverse conduction is also shown in Figure 6a.It can be seen that there was only one current path for both conduction conditions.The current flows from the N+ region through the N-base to the drift region in reverse conduction, while the current flows from the drift region through the P-base to the N+ region in forward conduction.Figure 6b shows the hole concentration at I s = 100 A/cm 2 of all the devices.In reverse conduction, the drift region of the DT-MOS obtained a high concentration of holes, which causes bipolar degradation [5].The short-circuit (SC) test results for the DT-MOS, DTC-MOS, and proposed MOS are shown in Figure 7.The SC test circuit used in the simulation is shown in Figure 7b.The bus voltage was 800 V.The stray inductance and resistance was 1 nH and 1 mΩ, respectively.The gate resistance was 10 Ω.A single pulse of 0 V/15 V gate bias was applied to the gate contact until the device failed due to thermal runaway caused by excessive temperatures.The time from device turn-on to failure was 1.6 µs, 1.9 µs, and 2.8 µs for the DT-MOS, DTC-MOS, and proposed MOS, respectively.For the DT-MOS, the highest saturation current caused a faster temperature rise, leading to earlier device failure.Due to the single current channel and depletion layer extension of the P-shield region, the proposed MOS exhibited the lowest saturation current.As a result, the proposed MOS achieved the longest time until failure.In the proposed MOS, the gate-source extended to the bottom of the gate, leading to a decrease in the overlap between the gate and the drain.As a result, the proposed MOS had the lowest Cgd compared to the DT-MOS and DTC-MOS, as shown in Figure 8a.While switching transients, the time constant is determined by the junction capacitance and gate resistors, which impact the switching speed of the devices.With a smaller capacitance, the devices switch at a faster speed.The Cgd was 141.68 pF/cm 2 , 136 pF/cm 2 , and 1.81 pF/cm 2 for the DT-MOS, DTC-MOS, and proposed MOS, respectively.Figure 8b shows the gate charge for the three devices; the Qgd of the DT-MOS was 569 nC/cm 2 and the Qg (Vgs = 15 V) was 1467 nC/cm 2 .The Qgd of the DTC-MOS was 406 nC/cm 2 and the Qg was 1136 nC/cm 2 .However, the Qgd of the LST-MOSFET was 6.7 nC/cm 2 and the Qg was 333 nC/cm 2 ; The short-circuit (SC) test results for the DT-MOS, DTC-MOS, and proposed MOS are shown in Figure 7.The SC test circuit used in the simulation is shown in Figure 7b.The bus voltage was 800 V.The stray inductance and resistance was 1 nH and 1 mΩ, respectively.The gate resistance was 10 Ω.A single pulse of 0 V/15 V gate bias was applied to the gate contact until the device failed due to thermal runaway caused by excessive temperatures.The time from device turn-on to failure was 1.6 µs, 1.9 µs, and 2.8 µs for the DT-MOS, DTC-MOS, and proposed MOS, respectively.For the DT-MOS, the highest saturation current caused a faster temperature rise, leading to earlier device failure.Due to the single current channel and depletion layer extension of the P-shield region, the proposed MOS exhibited the lowest saturation current.As a result, the proposed MOS achieved the longest time until failure.The short-circuit (SC) test results for the DT-MOS, DTC-MOS, and proposed MOS are shown in Figure 7.The SC test circuit used in the simulation is shown in Figure 7b.The bus voltage was 800 V.The stray inductance and resistance was 1 nH and 1 mΩ, respectively.The gate resistance was 10 Ω.A single pulse of 0 V/15 V gate bias was applied to the gate contact until the device failed due to thermal runaway caused by excessive temperatures.The time from device turn-on to failure was 1.6 µs, 1.9 µs, and 2.8 µs for the DT-MOS, DTC-MOS, and proposed MOS, respectively.For the DT-MOS, the highest saturation current caused a faster temperature rise, leading to earlier device failure.Due to the single current channel and depletion layer extension of the P-shield region, the proposed MOS exhibited the lowest saturation current.As a result, the proposed MOS achieved the longest time until failure.In the proposed MOS, the gate-source extended to the bottom of the gate, leading to a decrease in the overlap between the gate and the drain.As a result, the proposed MOS had the lowest Cgd compared to the DT-MOS and DTC-MOS, as shown in Figure 8a.While switching transients, the time constant is determined by the junction capacitance and gate resistors, which impact the switching speed of the devices.With a smaller capacitance, the devices switch at a faster speed.The Cgd was 141.68 pF/cm 2 , 136 pF/cm 2 , and 1.81 pF/cm 2 for the DT-MOS, DTC-MOS, and proposed MOS, respectively.Figure 8b shows the gate charge for the three devices; the Qgd of the DT-MOS was 569 nC/cm 2 and the Qg (Vgs = 15 V) was 1467 nC/cm 2 .The Qgd of the DTC-MOS was 406 nC/cm 2 and the Qg was 1136 nC/cm 2 .However, the Qgd of the LST-MOSFET was 6.7 nC/cm 2 and the Qg was 333 nC/cm 2 ; In the proposed MOS, the gate-source extended to the bottom of the gate, leading to a decrease in the overlap between the gate and the drain.As a result, the proposed MOS had the lowest C gd compared to the DT-MOS and DTC-MOS, as shown in Figure 8a.While switching transients, the time constant is determined by the junction capacitance and gate resistors, which impact the switching speed of the devices.With a smaller capacitance, the devices switch at a faster speed.The C gd was 141.68 pF/cm 2 , 136 pF/cm 2 , and 1.81 pF/cm 2 for the DT-MOS, DTC-MOS, and proposed MOS, respectively.Figure 8b shows the gate charge for the three devices; the Q gd of the DT-MOS was 569 nC/cm 2 and the Q g (V gs = 15 V) was 1467 nC/cm 2 .The Q gd of the DTC-MOS was 406 nC/cm 2 and the Q g was 1136 nC/cm 2 .However, the Q gd of the LST-MOSFET was 6.7 nC/cm 2 and the Q g was 333 nC/cm 2 ; this result is consistent with the results for the C gd , indicating that the proposed MOS can significantly reduce switching losses.
this result is consistent with the results for the Cgd, indicating that the proposed MOS can significantly reduce switching losses.The switching waveforms and test circuit of the three devices are shown in Figure 9. Figure 9d shows the resistance switch circuit used in the simulation, with a load current of 10 A (100 A/cm 2 ) at a normal current density.As can be seen in Figure 9a, the proposed MOS exhibited a lower Qgd compared to the other devices.The miller plateau almost disappeared, leading to a faster transition of Vgs, which is consistent with the Cgd results.This characteristic resulted in a significantly faster switching speed for the proposed MOS compared to the other devices, thereby reducing switching losses.From Figure 9b, the turnon loss (Eon) and turn-off loss (Eoff) of the DT-MOS was 0.28 mJ/cm 2 and 0.47 mJ/cm 2 and for the DTC-MOS was 0.26 mJ/cm 2 and 0.48 mJ/cm 2 .However, for the proposed MOS, the Eon and Eoff decreased to 0.09 mJ/cm 2 and 0.29 mJ/cm 2 .The switching losses (ESW) consisted of the Eon and Eoff; the ESW of the proposed MOS was 49.3% and 48.6% lower than that of the DT-MOS and DTC-MOS, respectively.The switching waveforms and test circuit of the three devices are shown in Figure 9. Figure 9d shows the resistance switch circuit used in the simulation, with a load current of 10 A (100 A/cm 2 ) at a normal current density.As can be seen in Figure 9a, the proposed MOS exhibited a lower Q gd compared to the other devices.The miller plateau almost disappeared, leading to a faster transition of V gs , which is consistent with the C gd results.This characteristic resulted in a significantly faster switching speed for the proposed MOS compared to the other devices, thereby reducing switching losses.From Figure 9b, the turn-on loss (E on ) and turn-off loss (E off ) of the DT-MOS was 0.28 mJ/cm 2 and 0.47 mJ/cm 2 and for the DTC-MOS was 0.26 mJ/cm 2 and 0.48 mJ/cm 2 .However, for the proposed MOS, the E on and E off decreased to 0.09 mJ/cm 2 and 0.29 mJ/cm 2 .The switching losses (E SW ) consisted of the E on and E off ; the E SW of the proposed MOS was 49.3% and 48.6% lower than that of the DT-MOS and DTC-MOS, respectively.
The total power losses (P t ) consist of conduction power losses and switching losses.When the device is operating under a square wave with a period T and a duty cycle D, the P t can be expressed as (3): When the device operated at 100 A/cm 2 , the V ds was 0.132 V, 0.156 V, and 0.223 V for the DT-MOS, DTC-MOS, and proposed MOS, which is consistent with the R on,sp .The switching frequency, f, is related to the period, T, by the formula f = 1 T .Although the R on,sp of the proposed MOS was greater than that of the DT-MOS and DTC-MOS, the switching losses were the main contributor to power loss at high frequencies.Working at high frequencies can effectively reduce the total power losses of the device; it is worth it to increase the on-resistance slightly to achieve smaller switching losses at high frequencies.Figure 9c shows the total power loss as a function of f for the three devices, when a D of 50% was assumed.When the switching frequency was 50 KHz, the proposed MOS achieved the lowest power loss compared to the other devices due to its lower switching loss.At a switching frequency of 200 KHz, the P t of the proposed MOS was 44.5% lower than the DT-MOS.With increasing f, the deference in P t between the DT-MOS and the proposed MOS gradually increased.The total power losses (Pt) consist of conduction power losses and switching losses.When the device is operating under a square wave with a period T and a duty cycle D, the Pt can be expressed as (3): When the device operated at 100 A/cm 2 , the Vds was 0.132 V, 0.156 V, and 0.223 V for the DT-MOS, DTC-MOS, and proposed MOS, which is consistent with the Ron,sp.The switching frequency, f, is related to the period, T, by the formula  = 1  .Although the Ron,sp of the proposed MOS was greater than that of the DT-MOS and DTC-MOS, the switching losses were the main contributor to power loss at high frequencies.Working at high frequencies can effectively reduce the total power losses of the device; it is worth it to increase the on-resistance slightly to achieve smaller switching losses at high frequencies.Figure 9c shows the total power loss as a function of f for the three devices, when a D of 50% was assumed.When the switching frequency was 50 KHz, the proposed MOS achieved the lowest power loss compared to the other devices due to its lower switching loss.At a switching frequency of 200 KHz, the Pt of the proposed MOS was 44.5% lower than the DT-MOS.With increasing f, the deference in Pt between the DT-MOS and the proposed MOS gradually increased.
The switching condition at a high current density (500 A/cm 2 ) is shown in Figure 10.As the current density increased, both conduction losses and switching losses increased The switching condition at a high current density (500 A/cm 2 ) is shown in Figure 10.As the current density increased, both conduction losses and switching losses increased significantly.The E SW of the three devices is shown in Figure 10a.The proposed MOS value was 0.96 mJ/cm 2 , which was 42.9% and 36.4% lower than the DT-MOS and DTC-MOS.However, the conduction losses of the proposed MOS increased faster than the other devices at 500 A/cm 2 .As a result, the P t of the proposed MOS was the highest before f = 200 KHz, as shown in Figure 10b.At a f of 250 KHz, the P t of the proposed MOS was only 7.6% lower than that of the DT-MOS.Comparing the work conditions between a normal current density and a high current density, it is more favorable for the proposed MOS to work at a normal current density.
However, high switching speeds and frequencies may present a greater switching oscillation challenge [30].By adding RC snubbers [31], reducing the switching speed [32], or using active gate control techniques [33], the switching oscillation will be suppressed.However, the mentioned methods for suppressing switching oscillation will lead to an undesirable increase in switching time and switching losses [30].There is a tradeoff between power losses and switching oscillation.An electronic structure that has transient part-time symmetry triggered by the switching-on and off of electronic devices can release oscillation energy, while still maintaining the very low loss state [34].This may be a good choice for suppressing switching oscillation in the future.The comprehensive performance of the three devices is shown in Table 2.
However, the conduction losses of the proposed MOS increased faster than the other devices at 500 A/cm 2 .As a result, the Pt of the proposed MOS was the highest before f = 200 KHz, as shown in Figure 10b.At a f of 250 KHz, the Pt of the proposed MOS was only 7.6% lower than that of the DT-MOS.Comparing the work conditions between a normal current density and a high current density, it is more favorable for the proposed MOS to work at a normal current density.However, high switching speeds and frequencies may present a greater switching oscillation challenge [30].By adding RC snubbers [31], reducing the switching speed [32], or using active gate control techniques [33], the switching oscillation will be suppressed.However, the mentioned methods for suppressing switching oscillation will lead to an undesirable increase in switching time and switching losses [30].There is a tradeoff between power losses and switching oscillation.An electronic structure that has transient part-time symmetry triggered by the switching-on and off of electronic devices can release oscillation energy, while still maintaining the very low loss state [34].This may be a good choice for suppressing switching oscillation in the future.The comprehensive performance of the three devices is shown in Table 2. Figure 11 shows a possible process for the proposed MOS.The process starts with the formation of the P-shield region after epitaxy, as shown in Figure 11a.Then, the Pbase and N-source are formed by ion implantation followed by high-temperature annealing, as shown in Figure 11b.After this, the gate trench is etched, the gate oxide is formed by chemical vapor deposition (CVD), and the polysilicon is deposited and etched to form the gate-source, which is shown in Figure 11c.Then, the oxide is deposited and the N+  Figure 11 shows a possible process for the proposed MOS.The process starts with the formation of the P-shield region after epitaxy, as shown in Figure 11a.Then, the P-base and N-source are formed by ion implantation followed by high-temperature annealing, as shown in Figure 11b.After this, the gate trench is etched, the gate oxide is formed by chemical vapor deposition (CVD), and the polysilicon is deposited and etched to form the gate-source, which is shown in Figure 11c.Then, the oxide is deposited and the N+ polysilicon is deposited and etched to form the gate electrode, which is shown in Figure 11d.Figure 11e shows the etching of the source trench and tilted implantation to form the P+ region along the sidewall of the source trench.Finally, Figure 11f shows the deposition of a passivation layer, the etching of the contact window, and the formation of the ohmic contact.

Figure 2 .
Figure 2. (a) Three-dimensional EC distribution of the proposed MOSFET at zero bias (b-b'-the yellow dashed line in Figure 1).(b) EC distribution of the SiO2/SiC interface (a-a'-the red dashed line in Figure 1) at different Vds.

Figure 2 .
Figure 2. (a) Three-dimensional E C distribution of the proposed MOSFET at zero bias (b-b'-the yellow dashed line in Figure 1).(b) E C distribution of the SiO 2 /SiC interface (a-a'-the red dashed line in Figure 1) at different V ds .

Figure 3 .
Figure 3. (a) Influence of DNb and WNb on BV and VF; (b) BV, VF at different LPsh and NNb.

Figure 3 .
Figure 3. (a) Influence of D Nb and W Nb on BV and V F ; (b) BV, V F at different L Psh and N Nb .

Figure 4 .
Figure 4. (a) Parasitic capacitance for the Cgd of the proposed MOS.(b) Influence of device characteristics on the distance between the gate and gate-source (c) Influence of Cgd and Ron,sp on the thickness of the gate-source.

Figure 4 .
Figure 4. (a) Parasitic capacitance for the C gd of the proposed MOS.(b) Influence of device characteristics on the distance between the gate and gate-source (c) Influence of C gd and R on,sp on the thickness of the gate-source.

Figure 5 .
Figure 5. (a) BV characteristics (b) electric field distributions with a drain bias at 1200 V of the DT-MOSF, DTC-MOS, and proposed MOS.

Figure 5 .
Figure 5. (a) BV characteristics (b) electric field distributions with a drain bias at 1200 V of the DT-MOSF, DTC-MOS, and proposed MOS.

Figure 6 .
Figure 6.(a) I-V characteristics of the three devices; (b) hole concentration distributions at Is = 100 A/cm 2 .

Figure 7 .
Figure 7. (a) Short circuit characteristics of the three devices; (b) short-circuit test circuit.

Figure 6 .
Figure 6.(a) I-V characteristics of the three devices; (b) hole concentration distributions at I s = 100 A/cm 2 .

Figure 6 .
Figure 6.(a) I-V characteristics of the three devices; (b) hole concentration distributions at Is = 100 A/cm 2 .

Figure 7 .
Figure 7. (a) Short circuit characteristics of the three devices; (b) short-circuit test circuit.

Figure 7 .
Figure 7. (a) Short circuit characteristics of the three devices; (b) short-circuit test circuit.

Figure 9 .
Figure 9.The switching waveforms of the DT-MOS, DTC-MOS, and Proposed MOS, respectively; (a) Turn-on and turn-off waveforms; (b) Turn-on loss and turn-off loss waveforms; (c) total power losses as a function of switching frequency f; (d) resistance switching circuit for simulations.

Figure 9 .
Figure 9.The switching waveforms of the DT-MOS, DTC-MOS, and Proposed MOS, respectively; (a) Turn-on and turn-off waveforms; (b) Turn-on loss and turn-off loss waveforms; (c) total power losses as a function of switching frequency f ; (d) resistance switching circuit for simulations.

Figure 10 .
Figure 10.Device works at 500 A/cm 2 ; (a) Turn-on loss and turn-off loss waveforms; (b) total power losses as a function of switching frequency f.

Figure 10 .
Figure 10.Device works at 500 A/cm 2 ; (a) Turn-on loss and turn-off loss waveforms; (b) total power losses as a function of switching frequency f.

Foundation
for Distinguished Young Leaders of Disciplines in Science and Technology of China (Grant Nos.2019JDJQ0051 and 2019JDJQ0050).

Table 1 .
Structural parameters of the three devices.

Table 1 .
Structural parameters of the three devices.

Table 2 .
Comparison of the three devices' characteristics.

Table 2 .
Comparison of the three devices' characteristics.