A Novel 4H-SiC Asymmetric MOSFET with Step Trench

In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (Cgd) to the gate-to-source capacitance (Cgs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and deep double-trench MOSFET (DDT-MOS), is demonstrated to have an increase of 200 V and 50 V in the breakdown voltage (BV), decreases of 21.8% and 10% in the specific on-resistance (Ron,sp), a reduction of about 1 V in the induced crosstalk voltage, and lower switching loss. Additionally, the trade-off between the resistance of the JFET region (RJFET) and the electric field in the gate oxide (Eox) is studied for a step trench and a deep trench. The improved performances suggest that a step trench is a competitive option in advanced device design.


Introduction
Silicon carbide (SiC) has become one of the most attractive wide-bandgap-power semiconductor materials in recent years due to its outstanding properties, such as high breakdown field, high electron mobility, and high thermal conductivity [1][2][3][4].As a unipolar representative device, an SiC metal-oxide-semiconductor field-effect transistor (MOSFET) can fully exploit the material superiority of SiC to achieve a lower specific on-resistance (R on,sp ) and a higher switching frequency.This has been widely used in applications with high power density and efficiency, such as photovoltaic and new energy vehicles [5,6].However, SiC MOSFET typically exhibits low channel mobility, a high electric field in the gate oxide (E ox ), and a large threshold voltage shift, affecting the expected performance and long-term reliability of the operation of the device [7][8][9].
To address the issue of low channel mobility, it is acknowledged that the trench MOSFET (UMOSFET) is able to effectively increase channel density and improve channel mobility [10].However, if the conventional trench structure is used in SiC UMOSFET, this leads to a high E ox .For this reason, with the SiC UMOSFET, it is necessary to introduce extra p-shield regions into a structure.In recent years, a number of novel shielding structures have been proposed for application to SiC UMOSFET to solve the problem of high E ox [11][12][13][14][15]. Unfortunately, all these structures inevitably introduce additional resistance in the JFET region (R JFET ).Lowering the E ox while retaining superior forward characteristics remains a significant challenge in the development of high-performance SiC UMOSFET.The ROHM's 3rd-generation double-trench MOSFET (DT-MOS) was the first commercially available SiC UMOSFET solution [16].It introduces p-shield regions under the recessed source contact to lower the field near the gate bottom.However, it has recently been shown that the p-shield regions of the DT-MOS inadequately protect the gate oxide under a range of extreme operational conditions [17].Therefore, in the ROHM's 4th-generation deep double-trench MOSFET (DDT-MOS), the deeper p-shield regions and source trench are employed to further reduce the E ox [18].Nevertheless, although the DDT-MOS achieves a lower E ox , the source trench in the DDT-MOS still occupies a considerable cell area.This is not favorable to improving the channel density.One potential solution to this problem is to utilize the deep source trench as a gate trench, with one side of the trench acting as a channel and the other side being grounded to the source.However, since a p-pillar2 with a low doping concentration improves the breakdown voltage (BV) and a p-pillar1 with a high doping concentration reduces E ox in the DDT-MOS, it is difficult to realize the asymmetric impurity distribution in the DDT-MOS via a single-step ion implantation process to ensure a low E ox and a high BV of the device.
In this article, a SiC asymmetric MOSFET with step trench (AST-MOS) is proposed and studied via TCAD simulation.The AST-MOS features a step trench, with an additional electron current path on one side to increase the channel density of the device.A thick oxide layer is also applied at the bottom of the step trench.This is used as a new voltagewithstanding region.The two p-pillars with varying widths and concentrations are formed separately, which means that they do not affect each other.This makes it easier to realize an asymmetric impurity distribution without deteriorating the performance of device.Furthermore, the ratio of the gate-to-drain capacitance (C gd ) to the gate-to-source capacitance (C gs ) in the AST-MOS is significantly reduced.As a result, the AST-MOS exhibits better performance, including higher BV, lower specific on-resistance (R on,sp ), reduced induced crosstalk voltage, and diminished switching loss, while maintaining a low E ox .

Device Structure and Mechanism
Figure 1 shows the schematic cross-sectional structures of the DT-MOS, DDT-MOS, and AST-MOS.The main structure parameters of the three structures are shown in Table 1.The three SiC UMOSFETs under study are rated for 1.2 kV, with a cell pitch of 2.6 µm and an active area of 10 mm 2 for a fair comparison.The DT-MOS is shown in Figure 1a.For the DT-MOS, due to the simultaneous etching of the source and gate trench, the p-shield is formed at the bottom of the source trench through high-dose p-type ion implantation to ensure adequate shielding effects for the gate oxide.The DDT-MOS is shown in Figure 1b and is derived from the DT-MOS structure.However, the former has a deeper p-shield than the latter as a result of the deeper source trench.This allows for a greater level of protection to be afforded to the gate oxide.The AST-MOS is shown in Figure 1c.Compared with the DT-MOS and DDT-MOS, the AST-MOS transforms a deep trench into a step trench and employs a two-step ion implantation to form two p-pillars with varying widths and concentrations.The two p-pillars are formed separately, which means that they do not affect each other.The width of each p-pillar is greater than the width of each trench by 0.2 µm.To achieve the asymmetric structure, the p-pillar1 on the one side is compensated by injecting N-type impurities at an angle without affecting the other side p-pillar1.This increases channel density by 50%.The polysilicon in the step trench is connected to the gate and is isolated from the source metal.Accordingly, the AST-MOS may be regarded as a hybrid of the ROHM's DT-MOS and the INFINEON's asymmetric trench MOSFET (AT-MOS).Additionally, the AST-MOS features a thick oxide layer at the bottom of the step trench, which is used as a new voltage-withstanding region.
In this study, Sentaurus TCAD 2018 tools are used to perform static and dynamic simulations of the device.A few crucial models are considered during the simulation, including Shockley-Read-Hall recombination, Okuto-Crowell impact ionization, Auger recombination, doping-dependent transport, enormal, bandgap narrowing, incomplete dopant ionization, and material anisotropy.The parameters of the TCAD simulation models are also calibrated via some experiments.Figure 2a shows the schematic cross-sectional structure and gives detailed information about the experimental device.The device is an unshielded trench MOSFET with a cell pitch of 2.4 µm and an active area of 20 mm 2 .Figure 2a,b show the comparison of the experimental results and the simulation results: the drain-source current (I ds ) versus the gate-source voltage (V gs ) curve and transconductance (g m ) versus V gs curve at a drain-source voltage (V ds ) of 0.5 V, and I ds −V ds curves with varying V gs .There is a high degree of overlap between the two, indicating that the subsequent simulation results in this paper are quite reliable.In the process of model calibration, the density of electron defects at different energy levels is modified and this is coupled with the appropriate bulk mobility to fit the I ds −V gs , g m −V gs , and I ds −V ds curves.Threshold voltage is mainly fitted by adjusting the fixed charge density.When the thickness of the gate oxide is around 55 nm and the doping concentration of the P-base is 2 × 10 17 cm −3 , a fixed charge of 1.4 × 10 12 cm −2 is employed and the measured threshold voltage is close to the simulated threshold voltage, both of which are approximately 4 V.For the hole defects, since they do not significantly affect the subsequent simulation results, this paper sets their density to be consistent with that of the electron defects and their energy level to be symmetrical to that of the electron defects.In this study, Sentaurus TCAD 2018 tools are used to perform static and dynamic simulations of the device.A few crucial models are considered during the simulation, including Shockley-Read-Hall recombination, Okuto-Crowell impact ionization, Auger re-  gate oxide is around 55 nm and the doping concentration of the P-base is 2 × 10 17 cm −3 , a fixed charge of 1.4 × 10 12 cm −2 is employed and the measured threshold voltage is close to the simulated threshold voltage, both of which are approximately 4 V.For the hole defects, since they do not significantly affect the subsequent simulation results, this paper sets their density to be consistent with that of the electron defects and their energy level to be symmetrical to that of the electron defects.The RJFET and the maximum electric field in the gate oxide (Eox-m) are often influenced by the p-shield.The significant disparity between the BV of the DT-MOS and that of the other two structures as well as the asymmetric design cause a higher Eox.In this paper, only the trade-off between the Eox-m (Vds = 1200 V, Vgs = 0 V) and RJFET at Ids = 40 A for the DDT-MOS and the SiC step trench UMOSFET (ST-MOS, parameters are the same as the AST-MOS) is investigated.Figure 3a and 3b demonstrate the RJFET versus the Eox-m curves when varying the width of JFET and the concentration of current spreading layer (CSL) for the DDT-MOS and ST-MOS, respectively.With a larger width of JFET or a higher concentration of CSL, the RJFET in the two structures is reduced owing to the less severe JFET effect induced by the p-shield, whereas the Eox-m located at the trench corner is increased.The RJFET versus the Eox-m curve of the ST-MOS is more closely aligned with the zero-point compared with that of the DDT-MOS.This indicates that the step trench structure has a superior trade-off between the RJFET and the Eox-m.Figure 3c provides an explanation for this.The ST-MOS employs multistage p-pillars, introducing multiple electric field peaks in the bulk of SiC to fully terminate the electric field lines in the p-pillar and forming multiwidth JFET regions to optimise the distribution of RJFET.In other words, the ST-MOS allows a smaller JFET width to achieve a small Eox-m while maintaining the same JFET resistance as the DDT-MOS.
In conventional SiC trench MOSFET, the p-shield is often designed with a high concentration in order to provide adequate protection for the gate oxide.In the DDT-MOS, the improved shielding effect allows for the use of a low concentration of the p-shield, which effectively improves the breakdown voltage (BV).Figure 4a,b demonstrate the physical mechanisms behind this.Firstly, when the p-pillar2 has a low concentration, it can effectively alleviate the concentration of the electric field at the corner of the p-pillar2.The R JFET and the maximum electric field in the gate oxide (E ox-m ) are often influenced by the p-shield.The significant disparity between the BV of the DT-MOS and that of the other two structures as well as the asymmetric design cause a higher E ox .In this paper, only the trade-off between the E ox-m (V ds = 1200 V, V gs = 0 V) and R JFET at I ds = 40 A for the DDT-MOS and the SiC step trench UMOSFET (ST-MOS, parameters are the same as the AST-MOS) is investigated.Figures 3a and 3b demonstrate the R JFET versus the E ox-m curves when varying the width of JFET and the concentration of current spreading layer (CSL) for the DDT-MOS and ST-MOS, respectively.With a larger width of JFET or a higher concentration of CSL, the R JFET in the two structures is reduced owing to the less severe JFET effect induced by the p-shield, whereas the E ox-m located at the trench corner is increased.The R JFET versus the E ox-m curve of the ST-MOS is more closely aligned with the zero-point compared with that of the DDT-MOS.This indicates that the step trench structure has a superior trade-off between the R JFET and the E ox-m .Figure 3c provides an explanation for this.The ST-MOS employs multistage p-pillars, introducing multiple electric field peaks in the bulk of SiC to fully terminate the electric field lines in the p-pillar and forming multi-width JFET regions to optimise the distribution of R JFET .In other words, the ST-MOS allows a smaller JFET width to achieve a small E ox-m while maintaining the same JFET resistance as the DDT-MOS.
The high-electric-field region of the DDT-MOS is wider than that of the DT-MOS during the off-state.Furthermore, the PN junction relationship between the p-pillar2 and the Nepitaxial layer tends to be more like the parallel planar junction, which decreases the rate of change of the electric field in the vicinity of the junction, as shown in Figure 4a.Secondly, the p-pillar2 can also withstand part of the blocking voltage because of the depletion of the p-pillar2 by the transverse electric field (Ex) and the longitudinal electric field (Ey) during the off-state.As a consequence of the influence of the Ex, the descent rate of the electric field is capable of being reduced for the longitudinal p-pillar2, as illustrated in Figure 4b.These two aspects result in a larger area being enclosed by the longitudinal electric field under electric fields of the same peak; namely, the device achieves a higher BV.Nevertheless, it must be noted that the second aspect has a lesser effect on the BV because the incomplete charge balance between the p-pillar2 and the CSL and the p-pillar2 is shallow in depth.For the AST-MOS, as illustrated in Figure 4c, the thick oxide layer within the step trench and the multistage p-pillar also has an effect on the BV.On the one hand, owing to the higher doping concentration of the p-pillar1, the electric field is concentrated at the p-pillar1, especially at the corner of the p-pillar1, which thus exhibits a wider multistage electric field distribution.On the other hand, the thick oxide layer is used for a new voltage-withstanding region, which also reduces the electric field near the PN junction.In conventional SiC trench MOSFET, the p-shield is often designed with a high concentration in order to provide adequate protection for the gate oxide.In the DDT-MOS, the improved shielding effect allows for the use of a low concentration of the p-shield, which effectively improves the breakdown voltage (BV).Figure 4a,b demonstrate the physical mechanisms behind this.Firstly, when the p-pillar2 has a low concentration, it can effectively alleviate the concentration of the electric field at the corner of the p-pillar2.The high-electric-field region of the DDT-MOS is wider than that of the DT-MOS during the off-state.Furthermore, the PN junction relationship between the p-pillar2 and the N-epitaxial layer tends to be more like the parallel planar junction, which decreases the rate of change of the electric field in the vicinity of the junction, as shown in Figure 4a.Secondly, the p-pillar2 can also withstand part of the blocking voltage because of the depletion of the p-pillar2 by the transverse electric field (E x ) and the longitudinal electric field (E y ) during the off-state.As a consequence of the influence of the E x , the descent rate of the electric field is capable of being reduced for the longitudinal p-pillar2, as illustrated in Figure 4b.These two aspects result in a larger area being enclosed by the longitudinal electric field under electric fields of the same peak; namely, the device achieves a higher BV.Nevertheless, it must be noted that the second aspect has a lesser effect on the BV because the incomplete charge balance between the p-pillar2 and the CSL and the p-pillar2 is shallow in depth.For the AST-MOS, as illustrated in Figure 4c, the thick oxide layer within the step trench and the multistage p-pillar also has an effect on the BV.On the one hand, owing to the higher doping concentration of the p-pillar1, the electric field is concentrated at the p-pillar1, especially at the corner of the p-pillar1, which thus exhibits a wider multistage electric field distribution.On the other hand, the thick oxide layer is used for a new voltage-withstanding region, which also reduces the electric field near the PN junction.
ondly, the p-pillar2 can also withstand part of the blocking voltage because of the depletion of the p-pillar2 by the transverse electric field (Ex) and the longitudinal electric field (Ey) during the off-state.As a consequence of the influence of the Ex, the descent rate of the electric field is capable of being reduced for the longitudinal p-pillar2, as illustrated in Figure 4b.These two aspects result in a larger area being enclosed by the longitudinal electric field under electric fields of the same peak; namely, the device achieves a higher BV.Nevertheless, it must be noted that the second aspect has a lesser effect on the BV because the incomplete charge balance between the p-pillar2 and the CSL and the p-pillar2 is shallow in depth.For the AST-MOS, as illustrated in Figure 4c, the thick oxide layer within the step trench and the multistage p-pillar also has an effect on the BV.On the one hand, owing to the higher doping concentration of the p-pillar1, the electric field is concentrated at the p-pillar1, especially at the corner of the p-pillar1, which thus exhibits a wider multistage electric field distribution.On the other hand, the thick oxide layer is used for a new voltage-withstanding region, which also reduces the electric field near the PN junction.Since AST-MOS introduces an additional gate region, the C gs of AST-MOS becomes larger compared to that of the other two structures.As shown in Figure 5a, the added capacitance, gate-to-pillar capacitance (C gp ), is composed of four components of the AST-MOS, and can be expressed by Equation (1): where the capacitance of the vertical bottom (C bottom ) and the capacitance of the bottom side (C side1 , C side2 ) are equivalent to the specific capacitance of the bottom and side oxide because the oxide layer at the bottom of the G2 is very thick.
the p-pillar will be depleted without inversion, as shown in Figure 5b,c.The Cside3 can be expressed as follows: where Cox-side3 is the specific capacitance of the right gate oxide and Csp is the depletion layer capacitance of the p-pillar.

Simulation Results and Analysis
In the AST-MOS, there are three key parameters, the depth of first step trench (Ds1), the concentration of p-pillar1 (Np1), and the concentration of p-pillar2 (Np2), that need to be further optimized to obtain an excellent trade-off.Figure 6 shows the influence of the Ds1 on the BV, the Eox-m, and the Ron,sp of the AST-MOS when Ds2 + Ds2 = 2 µm.It is indicated that the Ron,sp is sensitive to the Ds1.This is mainly because the space between P-base and p-pillar1 mainly depends on Ds1.If Ds1 ≤ 1.3 µm, the space is narrow, causing a significant JFET effect between the P-base and p-pillar1.This means that the added current path has no effect due to its excessive on-resistance below the extra channel.When Ds1 ≥ 1.3 µm, the on-resistance below the extra channel tends to stabilize, while the effective depth of the p-pillar2 decreases, resulting in a rapid decrease in the BV.Although the BV is greater when Ds1 = 1.3 µm than when Ds1 = 1.4 µm, the Eox-m exceeds 3 MV/cm when Ds1 = 1.3 µm.To achieve a smaller Ron,sp, a higher BV, and a lower Eox-m, the Ds1 is set to 1.4 µm.Furthermore, from the perspective of process realisation, a deep Ds1 combined with a shallow Ds2 is also a more reasonable approach.At this time, the Ds2 is set to 0.6 µm.

Depleltion Inversion
Np1 =6×10 17  For the the capacitance of the G2 right side (C side3 ), when a positive voltage is applied to the gate, there is no additional electron replenishment at the gate-p-pillar interface, and the p-pillar will be depleted without inversion, as shown in Figure 5b,c.The C side3 can be expressed as follows: where C ox-side3 is the specific capacitance of the right gate oxide and C sp is the depletion layer capacitance of the p-pillar.

Simulation Results and Analysis
In the AST-MOS, there are three key parameters, the depth of first step trench (D s1 ), the concentration of p-pillar1 (N p1 ), and the concentration of p-pillar2 (N p2 ), that need to be further optimized to obtain an excellent trade-off.Figure 6 shows the influence of the D s1 on the BV, the E ox-m , and the R on,sp of the AST-MOS when D s2 + D s2 = 2 µm.It is indicated that the R on,sp is sensitive to the D s1 .This is mainly because the space between P-base and p-pillar1 mainly depends on D s1 .If D s1 ≤ 1.3 µm, the space is narrow, causing a significant JFET effect between the P-base and p-pillar1.This means that the added current path has no effect due to its excessive on-resistance below the extra channel.When D s1 ≥ 1.3 µm, the on-resistance below the extra channel tends to stabilize, while the effective depth of the p-pillar2 decreases, resulting in a rapid decrease in the BV.Although the BV is greater when D s1 = 1.3 µm than when D s1 = 1.4 µm, the E ox-m exceeds 3 MV/cm when D s1 = 1.3 µm.To achieve a smaller R on,sp , a higher BV, and a lower E ox-m , the D s1 is set to 1.4 µm.Furthermore, from the perspective of process realisation, a deep D s1 combined with a shallow D s2 is also a more reasonable approach.At this time, the D s2 is set to 0.6 µm.Figure 7a exhibits the influence of the Np2 on the BV, Eox-m and Ron,sp when Np1 = 6 × 10 17 cm −3 .It is evident that the Np2 has a negligible impact on the Ron,sp.This is due to the high doping concentration of the CSL, which results in a small difference in RJFET.However, the influence on the BV and the Eox-m of the device is significant.The reason for the Figure 7a exhibits the influence of the N p2 on the BV, E ox-m and R on,sp when N p1 = 6 × 10 17 cm −3 .It is evident that the N p2 has a negligible impact on the R on,sp .This is due to the high doping concentration of the CSL, which results in a small difference in R JFET .However, the influence on the BV and the E ox-m of the device is significant.The reason for the influence on the E ox-m is that the N p2 determines the number of electric field lines pointing towards the p-pillar2 during the off-state.A higher N p2 results in more electric field lines pointing towards the p-pillar2, resulting in an smaller electric field in the gate oxide.The influence on the BV is mainly due to the electric field distribution within the low-doped p-pillar2, which mainly depends on the N p2 .A high N p2 causes the electric field to concentrate at the junction of the p-pillar2 and induces a narrower electric field distribution, as shown in Figure 8.Nevertheless, an excessively low N p2 can cause the electric field to concentrate on the p-pillar1 and the oxide layer, which may lead to a higher E ox-m and a lower BV, as observed when N p1 = 1 × 10 17 cm −3 .It should be noted that when N p2 = 1.5 × 10 17 cm −3 , the BV is higher than when N p2 = 2 × 10 17 cm −3 .However, the E ox-m is greater than 3 MV/cm; therefore, the N p2 is set to 2 × 10 17 cm −3 .Figure 7a exhibits the influence of the Np2 on the BV, Eox-m and Ron,sp when Np1 = 6 × 10 17 cm −3 .It is evident that the Np2 has a negligible impact on the Ron,sp.This is due to the high doping concentration of the CSL, which results in a small difference in RJFET.However, the influence on the BV and the Eox-m of the device is significant.The reason for the influence on the Eox-m is that the Np2 determines the number of electric field lines pointing towards the p-pillar2 during the off-state.A higher Np2 results in more electric field lines pointing towards the p-pillar2, resulting in an smaller electric field in the gate oxide.The influence on the BV is mainly due to the electric field distribution within the low-doped p-pillar2, which mainly depends on the Np2.A high Np2 causes the electric field to concentrate at the junction of the p-pillar2 and induces a narrower electric field distribution, as shown in Figure 8.Nevertheless, an excessively low Np2 can cause the electric field to concentrate on the p-pillar1 and the oxide layer, which may lead to a higher Eox-m and a lower BV, as observed when Np1 = 1 × 10 17 cm −3 .It should be noted that when Np2 = 1.5 × 10 17 cm −3 , the BV is higher than when Np2 = 2 × 10 17 cm −3 .However, the Eox-m is greater than 3 MV/cm; therefore, the Np2 is set to 2 × 10 17 cm −3 .Figure 7b illustrates the influence of the Np1 on the BV, Eox-m, and Ron,sp when Np2 = 2 × 10 17 cm −3 .The Np1 also has a minimal effect on the Ron,sp, the reason for which is the same as that behind the effect of Np2.However, the Np1 has a partial effect on the BV.The reason for which is that the Np1 can affect the electric field distribution within the p-pillar1 and oxide layer.When the Np1 is low, it possible to achieve a higher BV because the thick oxide layer can withstand a higher voltage.However, the Eox-m may be more than 3 MV/cm due to the weakening of the shielding effect.When the Np1 is high, the electric field is concentrated on the p-pillar1, leading to a premature breakdown of the device or a reduction in the withstanding voltage within the thick oxide layer.Analyzing Np1 = 5 × 10 17 cm −3 , it should be noted that the BV is slightly higher than when Np2 = 6 × 10 17 cm −3 and the Eox-m is Figure 7b illustrates the influence of the N p1 on the BV, E ox-m , and R on,sp when N p2 = 2 × 10 17 cm −3 .The N p1 also has a minimal effect on the R on,sp , the reason for which is the same as that behind the effect of N p2 .However, the N p1 has a partial effect on the BV.The reason for which is that the N p1 can affect the electric field distribution within the p-pillar1 and oxide layer.When the N p1 is low, it possible to achieve a higher BV because the thick oxide layer can withstand a higher voltage.However, the E ox-m may be more than 3 MV/cm due to the weakening of the shielding effect.When the N p1 is high, the electric field is concentrated on the p-pillar1, leading to a premature breakdown of the device or a reduction in the withstanding voltage within the thick oxide layer.Analyzing N p1 = 5 × 10 17 cm −3 , it should be noted that the BV is slightly higher than when N p2 = 6 × 10 17 cm −3 and the E ox-m is lower than 3 MV/cm.However, the increase in the E ox-m is greater, while the improvement in the BV is smaller, when the N p1 is 5 × 10 17 cm −3 instead of 6 × 10 17 cm −3 .Therefore, the N p1 is set to 6 × 10 17 cm −3 .
Figure 9a shows the on-state characteristics curve of the three structures.It can be seen from Figure 9a that the R on,sp values extracted at V ds = 1 V are 2.56, 2.22, and 2.0 mΩ•cm 2 for the DT-MOS, DDT-MOS, and AST-MOS, respectively.Owing to the high doping concentration of the JFET and drift region, and the extra electron current path.The AST-MOS achieves 21.8% and 10% reductions in R on,sp compared with the DT-MOS and the DDT-MOS, respectively.The R JFET values of the three structures are also shown in Figure 9a.The AST-MOS and the DDT-MOS employ a concentration of the CSL that is twice as great as that of the DT-MOS.Consequently, a lower R JFET is also obtained, despite the depth of the JFET region of the two structures being deeper than that of the DT-MOS.Figure 7b illustrates the influence of the Np1 on the BV, Eox-m, and Ron,sp when Np2 = 2 × 10 17 cm −3 .The Np1 also has a minimal effect on the Ron,sp, the reason for which is the same as that behind the effect of Np2.However, the Np1 has a partial effect on the BV.The reason for which is that the Np1 can affect the electric field distribution within the p-pillar1 and oxide layer.When the Np1 is low, it possible to achieve a higher BV because the thick oxide layer can withstand a higher voltage.However, the Eox-m may be more than 3 MV/cm due to the weakening of the shielding effect.When the Np1 is high, the electric field is concentrated on the p-pillar1, leading to a premature breakdown of the device or a reduction in the withstanding voltage within the thick oxide layer.Analyzing Np1 = 5 × 10 17 cm −3 , it should be noted that the BV is slightly higher than when Np2 = 6 × 10 17 cm −3 and the Eox-m is lower than 3 MV/cm.However, the increase in the Eox-m is greater, while the improvement in the BV is smaller, when the Np1 is 5 × 10 17 cm −3 instead of 6 × 10 17 cm −3 .Therefore, the Np1 is set to 6 × 10 17 cm −3 .
Figure 9a shows the on-state characteristics curve of the three structures.It can be seen from Figure 9a that the Ron,sp values extracted at Vds =1 V are 2.56, 2.22, and 2.0 mΩ•cm 2 for the DT-MOS, DDT-MOS, and AST-MOS, respectively.Owing to the high doping concentration of the JFET and drift region, and the extra electron current path.The AST-MOS achieves 21.8% and 10% reductions in Ron,sp compared with the DT-MOS and the DDT-MOS, respectively.The RJFET values of the three structures are also shown in Figure 9a.The AST-MOS and the DDT-MOS employ a concentration of the CSL that is twice as great as that of the DT-MOS.Consequently, a lower RJFET is also obtained, despite the depth of the JFET region of the two structures being deeper than that of the DT-MOS.Figure 9b shows the electric field distribution of the three structures along line A-A' at E sic-m = 3 MV/cm.The BV extracted at E sic-m = 3 MV/cm are 1330, 1511, and 1561 V for the DT-MOS, DDT-MOS, and AST-MOS, respectively.The E ox-m values are 2.68, 2.45, and 2.38 MV/cm for the three structures, respectively.It is worth noting that the AST-MOS achieves 231 and 50 V increases in the BV compared with the DT-MOS and DDT-MOS, respectively, while maintaining the lowest E ox-m value.This phenomenon is mainly attributed to the wider W s1 and the multistage p-pillar, which provide superior shielding effects even if there is no p-shield on one side of the first step trench.Further analysis of the BV enhancement can be attributed to two aspects, as shown in the small box in Figure 9b.On the one hand, part of the voltage is withstood by the thick oxide layer.On the other hand, the electric field decreases slightly slower across the PN junction due to the wider electric field distribution, as shown in Figure 9c.This is consistent with what is described in the mechanism section above.
The capacitances of the three structures are shown in Figure 10.The gate-to-source capacitance (C gd ) values extracted at V ds = 1000 V are 94.5, 44, and 44 pF/cm 2 for the DT-MOS, DDT-MOS, and AST-MOS, respectively.Although the AST-MOS has larger gate region numbers than the DT-MOS and DDT-MOS, the AST-MOS achieves a low C gd , the reasons for which are twofold.Primarily, the depth of the p-pillar is deeper than that of the DT-MOS, and the width of the p-pillar is wider than that of the DDT-MOS.These configurations are beneficial to the positive charge in the depletion layer overlapping gate and drain interacting with the p-pillar.Furthermore, as the p-shield of the AST-MOS overlaps with the gate more than that of the DT-MOS and DDT-MOS, the C gs of the AST-MOS increases significantly.As shown in Figure 10, the gate-to-source capacitance (C gs ) of the AST-MOS is 66.8 nF/cm 2 , while those of the DT-MOS and DDT-MOS are only 31.6 and 31.2 nF/cm 2 .The C gs of the AST-MOS is more than 2 double that of the DT-MOS and DDT-MOS.Finally, the drain-source capacitance (C ds ) is 850, 928, and 924 pF/cm 2 for the DT-MOS, DDT-MOS, and AST-MOS, respectively.
The capacitances of the three structures are shown in Figure 10.The gate-to-source capacitance (Cgd) values extracted at Vds = 1000 V are 94.5, 44, and 44 pF/cm 2 for the DT-MOS, DDT-MOS, and AST-MOS, respectively.Although the AST-MOS has larger gate region numbers than the DT-MOS and DDT-MOS, the AST-MOS achieves a low Cgd, the reasons for which are twofold.Primarily, the depth of the p-pillar is deeper than that of the DT-MOS, and the width of the p-pillar is wider than that of the DDT-MOS.These configurations are beneficial to the positive charge in the depletion layer overlapping gate and drain interacting with the p-pillar.Furthermore, as the p-shield of the AST-MOS overlaps with the gate more than that of the DT-MOS and DDT-MOS, the Cgs of the AST-MOS increases significantly.As shown in Figure 10, the gate-to-source capacitance (Cgs) of the AST-MOS is 66.8 nF/cm 2 , while those of the DT-MOS and DDT-MOS are only 31.6 and 31.2 nF/cm 2 .The Cgs of the AST-MOS is more than 2 double that of the DT-MOS and DDT-MOS.Finally, the drain-source capacitance (Cds) is 850, 928, and 924 pF/cm 2 for the DT-MOS, DDT-MOS, and AST-MOS, respectively.Since the AST-MOS has a large Cgs and a small Cgd, the AST-MOS is able to achieve a small Cgd/Cgs, which is beneficial for the suppression of induced crosstalk voltage [19].Currently, due to the problem of parasitic turn-on (PTO) [20], the switching frequency of the device is often limited by the gate-induced crosstalk voltage.The gate-induced crosstalk voltage mainly comes from two parts: one is the charging and discharging displacement current of the Cgd, and the other is the induced voltage introduced by the common- Since the AST-MOS has a large C gs and a small C gd , the AST-MOS is able to achieve a small C gd /C gs , which is beneficial for the suppression of induced crosstalk voltage [19].Currently, due to the problem of parasitic turn-on (PTO) [20], the switching frequency of the device is often limited by the gate-induced crosstalk voltage.The gate-induced crosstalk voltage mainly comes from two parts: one is the charging and discharging displacement current of the C gd , and the other is the induced voltage introduced by the common-source inductor (L s ).Both of these are coupled to the gate voltage through the drive loop [21].The two parts of the induced crosstalk voltage are often opposites [22].Owing to the first part of these being unfavorable to the device, only the first part of these is considered in this paper in our efforts to establish a switching-characteristics simulation circuit, as shown in Figure 11.The circuit consists of high and low sides, where the high side is in a reverse conducting mode and the low side is in a switching mode.Working according to [23,24], gate inductance (L g ) and parasitic inductance (L δ ) are chosen to be 15 and 36 nH, respectively; the gate-to-source voltage (V gs ) is a pulse voltage of +18 V/−5 V.The load inductance (L load ) is set to 10 µH and the high-side gate turn-off resistance is 10 Ω.The V gs of the high side during the switching process is given by Equation (3).
where V gsoff is the high side gate turn-off voltage, R goff is the high side gate turn-off resistance, V ds is the high side drain-to-source voltage, and V gs is the high side gate-tosource voltage.
When the gate turn-on resistance is equal to turn-off, the values are 10 Ω, 10 Ω, and 6 Ω for the DT-MOS, DDT-MOS, and AST-MOS, respectively.The dI ds /dt during the turn-on and turn-off processes for the three structures are similar, as shown in Figure 12a.The high-side gate-induced crosstalk voltage waveform for the three structures is shown in Figure 12b.The high-side positively induced crosstalk voltage (V ic+ ) is 2.9 V, 2.7 V, and 1.6 V for the DT-MOS, DDT-MOS, and AST-MOS, respectively, and the high-side negatively induced crosstalk voltage (V ic− ) is −2.5 V, −2.6 V, and −1.6 V for the DT-MOS, DDT-MOS, and AST-MOS, respectively.The AST-MOS exhibited lower V ic+ values of 1.3 V and 1.1 V compared to that of the DT-MOS and DDT-MOS during the turn-on process.Similarly, during the turn-off process, the V ic− of the AST-MOS is 0.9 V and 1 V lower than that of the DT-MOS and DDT-MOS.This indicates that a larger gate turn-off voltage can be employed for the AST-MOS during the switching process.Figure 12c illustrates the switching loss of the three structures.The AST-MOS exhibits a lower switching loss at a similar dI ds /dt.
6 Ω for the DT-MOS, DDT-MOS, and AST-MOS, respectively.The dIds/dt during the turnon and turn-off processes for the three structures are similar, as shown in Figure 12a.The high-side gate-induced crosstalk voltage waveform for the three structures is shown in Figure 12b.The high-side positively induced crosstalk voltage (Vic+) is 2.9 V, 2.7 V, and 1.6 V for the DT-MOS, DDT-MOS, and AST-MOS, respectively, and the high-side negatively induced crosstalk voltage (Vic−) is −2.5V, −2.6V, and −1.6V for the DT-MOS, DDT-MOS, and AST-MOS, respectively.The AST-MOS exhibited lower Vic+ values of 1.3 V and 1.1 V compared to that of the DT-MOS and DDT-MOS during the turn-on process.Similarly, during the turn-off process, the Vic− of the AST-MOS is 0.9 V and 1 V lower than that of the DT-MOS and DDT-MOS.This indicates that a larger gate turn-off voltage can be employed for the AST-MOS during the switching process.Figure 12c illustrates the switching loss of the three structures.The AST-MOS exhibits a lower switching loss at a similar dIds/dt.Figure 13 shows the main process flow for the AST-MOS.The epitaxial wafer with the CSL is prepared; then, the N+ source region, P+ source region, and P-base are formed by ion implantation at 500 °C (see Figure 13a).The gate trench G1 is etched (see Figure 13b).The first step trench is etched and then the first p-pillar, with specified width and depth, is formed by tilted injection (see Figure 13c).The extra channel on one side of the deep trench is formed via tilted N-type ion implantation (see Figure 13d).The second step trench is etched and then the second p-pillar is formed via tilted injection (see Figure 13e).The thick oxide is deposited.Then, the oxide is back-etched to a specified depth and ion injection is performed at 1750 °C.Then, the silicon carbide surface is repaired via annealing in H2 atmosphere at 1400 °C (see Figure 13f).Gate oxide is deposited, followed by annealing in NO atmosphere (see Figure 13g).Polysilicon is deposited and back-etched to a specified depth, followed by the ILD deposition and patterning (see Figure 13h).N+ source region, P+ source region, and backside drain are sputtered with Ni to form an ohmic contact; this is followed by metal thickening and PI deposition and patterning (see Figure 13i).Figure 13 shows the main process flow for the AST-MOS.The epitaxial wafer with the CSL is prepared; then, the N+ source region, P+ source region, and P-base are formed by ion implantation at 500 • C (see Figure 13a).The gate trench G1 is etched (see Figure 13b).The first step trench is etched and then the first p-pillar, with specified width and depth, is formed by tilted injection (see Figure 13c).The extra channel on one side of the deep trench is formed via tilted N-type ion implantation (see Figure 13d).The second step trench is etched and then the second p-pillar is formed via tilted injection (see Figure 13e).The thick oxide is deposited.Then, the oxide is back-etched to a specified depth and ion injection is performed at 1750 • C.Then, the silicon carbide surface is repaired via annealing in H 2 atmosphere at 1400 • C (see Figure 13f).Gate oxide is deposited, followed by annealing in NO atmosphere (see Figure 13g).Polysilicon is deposited and back-etched to a specified depth, followed by the ILD deposition and patterning (see Figure 13h).N+ source region, P+ source region, and backside drain are sputtered with Ni to form an ohmic contact; this is followed by metal thickening and PI deposition and patterning (see Figure 13i).
Table 2 shows the performance comparison of the three structures.Compared with the DT-MOS and the DDT-MOS, the AST-MOS features a thick oxide layer at the bottom step trench and a low-doped p-pillar2, resulting in increase of 231 V and 50 V increases in the BV, respectively, while maintaining a low E ox-m .Additionally, due to the high doping concentration of the JFET and drift regions and the extra electron current path, the AST-MOS achieves 21.8% and 10% reductions in the R on,sp , respectively.Meanwhile, the C gd /C gs of the AST-MOS experiences a significant decrease, resulting in a reduction of about 1 V in the induced crosstalk voltage and a lower switching loss at a similar dI ds /dt.13b).The first step trench is etched and then the first p-pillar, with specified width and depth, is formed by tilted injection (see Figure 13c).The extra channel on one side of the deep trench is formed via tilted N-type ion implantation (see Figure 13d).The second step trench is etched and then the second p-pillar is formed via tilted injection (see Figure 13e).The thick oxide is deposited.Then, the oxide is back-etched to a specified depth and ion injection is performed at 1750 °C.Then, the silicon carbide surface is repaired via annealing in H2 atmosphere at 1400 °C (see Figure 13f).Gate oxide is deposited, followed by annealing in NO atmosphere (see Figure 13g).Polysilicon is deposited and back-etched to a specified depth, followed by the ILD deposition and patterning (see Figure 13h).N+ source region, P+ source region, and backside drain are sputtered with Ni to form an ohmic contact; this is followed by metal thickening and PI deposition and patterning (see Figure 13i).Table 2 shows the performance comparison of the three structures.Compared with the DT-MOS and the DDT-MOS, the AST-MOS features a thick oxide layer at the bottom step trench and a low-doped p-pillar2, resulting in increase of 231 V and 50 V increases in the BV, respectively, while maintaining a low Eox-m.Additionally, due to the high doping concentration of the JFET and drift regions and the extra electron current path, the AST-MOS achieves 21.8% and 10% reductions in the Ron,sp, respectively.Meanwhile, the Cgd/Cgs of the AST-MOS experiences a significant decrease, resulting in a reduction of about 1V in the induced crosstalk voltage and a lower switching loss at a similar dIds/dt.

Conclusions
A novel 4H-SiC asymmetric MOSFET with a step trench is proposed and investigated via numerical simulation.The introduction of the step trench optimizes compromise between the R JFET and E ox-m and the asymmetric design improves the channel density of the device.A thick oxide layer is also employed at the bottom of the step trench to be used for a new voltage-withstanding region.As a result, the AST-MOS exhibits a higher BV and a lower R on,sp than the DT-MOS and DDT-MOS.Additionally, due to the ratio of the C gd /C gs in the AST-MOS decreasing, the AST-MOS demonstrates lower induced crosstalk voltage and switching losses.Consequently, the proposed AST-MOS has the potential to be a highly effective solution for designing advanced device structure.

Figure 2 .
Figure 2. (a) Schematic cross-sectional structure and detailed information of the experimental device.Comparison of the experimental results and the simulation results: (b) Ids−Vgs and gm−Vgs curves at Vds = 0.5 V, (c) Vds−Ids curves with varying Vgs.

Figure 2 .
Figure 2. (a) Schematic cross-sectional structure and detailed information of the experimental device.Comparison of the experimental results and the simulation results: (b) I ds −V gs and g m −V gs curves at V ds = 0.5 V, (c) V ds −I ds curves with varying V gs .

Figure 3 .
Figure 3. Trade-off between the RJFET and the Eox-m with varying (a) the width of JFET and (b) the concentration of CSL for the DDT-MOS and ST-MOS.(c) Electric field distribution of the DDT-MOS and ST-MOS at a maximum electric field in the SiC (Esic-m) of 3 MV/cm.

Figure 3 .
Figure 3. Trade-off between the R JFET and the E ox-m with varying (a) the width of JFET and (b) the concentration of CSL for the DDT-MOS and ST-MOS.(c) Electric field distribution of the DDT-MOS and ST-MOS at a maximum electric field in the SiC (E sic-m ) of 3 MV/cm.

Figure 3 .Figure 4 .Figure 4 .
Figure 3. Trade-off between the RJFET and the Eox-m with varying (a) the width of JFET and (b) the concentration of CSL for the DDT-MOS and ST-MOS.(c) Electric field distribution of the DDT-MOS and ST-MOS at a maximum electric field in the SiC (Esic-m) of 3 MV/cm.

Figure 6 .
Figure 6.The influence of the D s1 on the BV, E ox-m and R on,sp when D s2 + D s2 = 2 µm.

Figure 7 .Figure 7 .Figure 8 .
Figure 7.The influence of (a) the Np2 and (b) the Np1 on the BV, Eox-m and Ron,sp

Figure 9 .
Figure 9. (a) On-state characteristics curve.(b) Electric field distribution of the AST-MOS, DT-MOS, and DT-MOS along line A-A' at E sic-m = 3 MV/cm.(c) Electric field distribution of the DDT-MOS and AST-MOS during the off-state.

Figure 13 .
Figure 13.Process flow for the AST-MOS.(a) Epitaxial layer preparation and formation of the Pbase, N+ source region, and P+ source region.(b) Etching the gate trench G1.(c) Etching the first step trench and forming the p-pillar1.(d) Forming an extra channel on one side of the deep trench.(e) Etching the second step trench and forming the p-pillar2.(f) Depositing oxide and back-etching.(g) Depositing gate oxide.(h) Depositing polysilicon and ILD, and then patterning.(i) Metallization.

Figure 13 .
Figure 13.Process flow for the AST-MOS.(a) Epitaxial layer preparation and formation of the P-base, N+ source region, and P+ source region.(b) Etching the gate trench G1.(c) Etching the first step trench and forming the p-pillar1.(d) Forming an extra channel on one side of the deep trench.(e) Etching the second step trench and forming the p-pillar2.(f) Depositing oxide and back-etching.(g) Depositing gate oxide.(h) Depositing polysilicon and ILD, and then patterning.(i) Metallization.

Table 1 .
Structural parameters of the three devices. 17

Table 1 .
Structural parameters of the three devices.

Table 2 .
Comparison of the three devices' characteristics.

Table 2 .
Comparison of the three devices' characteristics.
a BFOM is the value of BV 2 /R on,sp .