# Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed

^{1}

^{2}

^{*}

## Abstract

**:**

_{F}) at I

_{S}= 100 A/cm

^{2}, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (E

_{mox}). Additionally, the gate–drain capacitance (C

_{gd}) and gate–drain charge (Q

_{gd}) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater R

_{on,sp}than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

## 1. Introduction

_{on,sp}).

_{rss}[20,21,22] and to achieve a fast switching speed. This study was carried out with numerical TCAD, and some essential models were included such as the Fermi–Dirac, incomplete-ionization, Shockley–Reed–Hall and Auger combination, Lombardi (CVT), impact-ionization, and band-narrowing models [23,24,25]. A channel mobility of 50 cm

^{2}/(Vs) was used [26]. The structure achieved a lower V

_{F}, C

_{gd}, and Q

_{gd}and lower switching losses compared with a DT-MOS [27] and a DT-MOS with an MOS-channel diode (DTC-MOS) [18], and it also reduced the maximum oxide electric field (E

_{mox}).

## 2. Device Structure and Mechanism

_{gd}. Meanwhile, at the right half-cell, the p-base turns into an n-base, so a low-barrier diode is integrated into this structure to improve its reverse conduction. The P-shield extends to the current spreading layer (CSL), and it decreases the E

_{mox}in the blocking state and increases the BV, improving the device’s reliability.

^{15}cm

^{−3}and 9 μm, respectively. The P-base region in all the devices had a doping concentration of 2 × 10

^{17}cm

^{−3}and a thickness of 0.5 μm. The N-base had a doping concentration of 3 × 10

^{16}cm

^{−3}and a thickness of 0.3 μm. The P-shield had a doping concentration of 2 × 10

^{18}cm

^{−3}and a thickness of 0.3 μm. The CSL had a doping concentration of 8 × 10

^{16}cm

^{−3}and a depth of 1.7 μm. The depth of the source trench and gate trench was 1.4 μm for both devices. The thickness of the gate oxide was 50 nm for both the N-base and P-base to improve the device reliability in the DT-MOS and proposed MOS. Considering the sufficient volume of the gate and the electric field, the distance of the oxide between the gate and gate-source and the thickness of the gate-source was 0.1 μm for the DTC-MOS and the proposed MOS. The cell pitch was 3.8 μm for the DT-MOS, and that of the other two devices was 4.2 μm. The main structure parameters of the DT-MOS, DTC-MOS, and proposed MOS are shown in Table 1.

_{C}) distribution of the 4H-SiC in the proposed MOS structure at zero bias. The E

_{C}decreased from the P-shield to the N-base at the right half-cell. The high doping of the P-shield and the low doping of the N-base led to a rapid depletion of the N-base region at zero bias, preventing the formation of a conducting channel. Therefore, there was no impact on the BV at low doping concentrations. At zero bias, the E

_{C}of the N-base was lower than the P-base, allowing electrons to overcome the potential barrier at a low V

_{ds}. Figure 2b shows the E

_{C}distribution along the a–a’ line (shown in Figure 1) at different V

_{ds}. As V

_{ds}decreased, the E

_{C}increased in both the N-base and CSL. However, the E

_{C}of the CSL increased faster than the N-base region. At V

_{ds}= −1 V, the potential barrier became very low, allowing electrons to overcome the potential barrier, turning on the low barrier diode.

_{2}and SiC. N

_{Nb}is the doping concentration of the N-base. The W

_{Nb}is the width of the N-base. The structure of the low barrier diode in a planar structure and trench structure is the same, being formed by the N+ polysilicon, oxide, the low doping concentration N region, and the high doping concentration P region. Although the formula was obtained for planar structures [19,28], it is also applicable to trench structures. The t

_{c}is the thickness of the oxide between the gate-source and the N-base, which is fixed at 50 nm in the proposed MOS, as it has a great influence on device reliability. The t

_{c}of the DTC-MOS was 20 nm, to easily turn on the built-in diode. From equation (1), N

_{Nb}and W

_{Nb}had an impact on the potential barrier of the LBD. Additionally, the thickness of the N-base (T

_{Nb}) and the length of the P-shield (L

_{Psh}) also influenced the resistance of the LBD, which in turn affects the V

_{F}. Therefore, these parameters were optimized.

## 3. Simulation Results and Analysis

_{Nb}and D

_{Nb}on the BV and V

_{F}. The solid circles represent BV values and the dashed circles represent V

_{F}values. The W

_{Nb}varied from 0.1 μm to 0.6 μm in steps of 0.1 μm. As W

_{Nb}increased, the reverse current path expanded, which led to a decrease in V

_{F}. However, the breakdown turned into a punch-through breakdown, which made the device unable to withstand high voltages. With increasing D

_{Nb}, the length of the potential barrier increased, leading to an increase in V

_{F}. In this case, a longer W

_{Nb}was required to trigger a punch-through breakdown. It is worth noting that when D

_{Nb}exceeded 0.3 μm, the leakage current of the proposed MOS became comparable to the DT-MOS, which will be further discussed later. To tradeoff the BV, V

_{F}, and leakage current, the optimal values of W

_{Nb}= 0.3 μm and D

_{Nb}= 0.3 μm were selected.

_{F}for the proposed MOS, considering different values of L

_{Psh}and N

_{Nb}. As the L

_{Psh}increased from 1 μm to 1.5 μm in steps of 0.1 μm, the depletion region extended, leading to a decrease in E

_{mox}and an increase in BV. However, the current path became narrow, leading to an increase in R

_{on,sp}and V

_{F}because of the change in the JFET resistance. With increasing N

_{Nb}, the potential barrier of the low barrier diode reduced, leading to a decrease in V

_{F}. However, with high doping of N

_{Nb}, the BV dropped below 1400 V, as shown for N

_{Nb}= 3.5 × 10

^{16}cm

^{−3}. At low N

_{N}values

_{,}the breakdown point occurred at the P-shield/N-drift junction, so the BV did not change with different N

_{Nb}values. The change in N

_{Nb}had no influence on R

_{on,sp}. However, with increasing L

_{Psh}, the R

_{on,sp}increased from 1.84 mΩ × cm

^{−2}to 4.58 mΩ × cm

^{−2}. In order to tradeoff BV, V

_{F}, and R

_{on,sp}, L

_{Psh}= 1.3 μm and N

_{Nb}= 3 × 10

^{16}cm

^{−3}were selected, represented by the red circle in Figure 3b.

_{ox}) on the C

_{gd}and oxide electric field (E

_{ox}). The voltage between the gate and the gate-source was set to 15 V. When D

_{ox}was 0.1 μm for both the bottom and side wall of the gate, the E

_{ox}was 1.5 MV/cm, which corresponds to the simulation results. The thickness of the gate-source (T

_{GS}) was fixed at 0.1 μm, and the thickness of gate poly (T

_{G}) changed as D

_{ox}increased or decreased. With increasing D

_{ox}, the BV and V

_{F}had no influence, so they are not included in Figure 4b. The D

_{ox}has little influence on C

_{gd}. Therefore, when D

_{ox}was greater than 0.1 μm, E

_{ox}was already less than 3 MV/cm. In order to facilitate subsequent simulations and ensure a sufficient volume of gate poly for adjusting the gate resistance, D

_{ox}= 0.1 μm was selected.

_{GS}is shown in Figure 4c; the D

_{ox}was fixed at 0.1 μm. With increasing T

_{GS}, there was no influence on BV and V

_{F}, which is not shown in the figure. R

_{on,sp}increased from 2.23 mΩ∙cm

^{2}to 2.28 mΩ∙cm

^{2}, because the CSL, oxide, and gate poly formed an MIS structure, which increased the electron concentration of the CSL during conduction; this effect weakened as T

_{G}decreased.

_{GS}, C

_{gd}decreases; this is because the gate-source extends to the bottom of the gate poly, resulting in a significant decrease in the overlap between the gate electrode and drain electrode. In this case, the C

_{gd}can be expressed as:

_{p}is the oxide capacitance between the P-base and gate electrode, which is related to the thickness of the oxide and the overlap between the gate poly and the P-base. C

_{PN}is the junction capacitance, which is completely independent of the gate parameters, and the C

_{PN}decreases as V

_{ds}increases. When increasing T

_{GS}or D

_{ox}, the T

_{G}decreases, resulting in a decreased overlap between the gate poly and the P-base, thus causing a decrease in C

_{p}. Meanwhile, the T

_{G}has no influence on C

_{PN}, so the C

_{gd}will decrease. However, it is worth noting that the C

_{gd}is already sufficiently small, and further decreasing C

_{p}cannot significantly change the C

_{gd}. To ensure a suitable gate resistance for device, a sufficient volume of gate poly must be considered, which cannot be reflected in a simulation. Therefore, T

_{GS}= 0.1 μm was selected for further simulations. According to Figure 4b,c, the internal parameters of the gate trench have little influence on the performance of the device when the resistance of the gate poly is not considered; this shows that the proposed MOS has a wide process window for forming the L-shape gate-source.

_{Nb}= 0.2 μm. However, when D

_{Nb}= 0.3 μm, the BV was the same as D

_{Nb}= 0.2 μm, the leakage current decreased to the level of the DT-MOS. This is because the leakage current is related to the parameters of the N-base before breakdown and the blocking voltage is related to the P-shield/N-drift junction, where the electric field is highest in the SiC region and avalanche breakdown occurs. The electric field distribution of the three devices at 1200 V is shown in Figure 5b. The E

_{mox}was located at the bottom of the oxide for all the devices. Compared with the DT-MOS and DTC-MOS, the proposed MOS had an extended P-shield, which was able to expand the depletion layer and provide better protection effects to the oxide. As a result, the E

_{mox}was only 2.52 MV/cm, while the E

_{mox}of the other devices was higher than 4 MV/cm. With a high E

_{mox}, a Fowler–Nordheim tunneling current may be generated; this carries electrons through the oxide layer, breaking the Si-O bond over time and generating defects, leading to a full breakdown of the SiO

_{2}layer [29], which has a great influence on device reliability.

_{on,sp}of the DT-MOS and DTC-MOS was smaller than for the proposed MOS; this is because the DT-MOS has two channel paths for conduction, and because both DT-MOS and DTC-MOS do not extend the P-shield, which increases JFET resistance. With a low barrier diode, the V

_{F}of the proposed MOS decreased significantly. The V

_{F}was 2.85 V, 2.63 V, and 0.85 V at 100 A/cm

^{2}for the DT-MOS, DTC-MOS, and proposed MOS, respectively. The current vector of the forward and reverse conduction is also shown in Figure 6a. It can be seen that there was only one current path for both conduction conditions. The current flows from the N+ region through the N-base to the drift region in reverse conduction, while the current flows from the drift region through the P-base to the N+ region in forward conduction. Figure 6b shows the hole concentration at I

_{s}= 100 A/cm

^{2}of all the devices. In reverse conduction, the drift region of the DT-MOS obtained a high concentration of holes, which causes bipolar degradation [5].

_{gd}compared to the DT-MOS and DTC-MOS, as shown in Figure 8a. While switching transients, the time constant is determined by the junction capacitance and gate resistors, which impact the switching speed of the devices. With a smaller capacitance, the devices switch at a faster speed. The C

_{gd}was 141.68 pF/cm

^{2}, 136 pF/cm

^{2}, and 1.81 pF/cm

^{2}for the DT-MOS, DTC-MOS, and proposed MOS, respectively. Figure 8b shows the gate charge for the three devices; the Q

_{gd}of the DT-MOS was 569 nC/cm

^{2}and the Q

_{g}(V

_{gs}= 15 V) was 1467 nC/cm

^{2}. The Q

_{gd}of the DTC-MOS was 406 nC/cm

^{2}and the Q

_{g}was 1136 nC/cm

^{2}. However, the Q

_{gd}of the LST-MOSFET was 6.7 nC/cm

^{2}and the Q

_{g}was 333 nC/cm

^{2}; this result is consistent with the results for the C

_{gd}, indicating that the proposed MOS can significantly reduce switching losses.

^{2}) at a normal current density. As can be seen in Figure 9a, the proposed MOS exhibited a lower Q

_{gd}compared to the other devices. The miller plateau almost disappeared, leading to a faster transition of V

_{gs}, which is consistent with the C

_{gd}results. This characteristic resulted in a significantly faster switching speed for the proposed MOS compared to the other devices, thereby reducing switching losses. From Figure 9b, the turn-on loss (E

_{on}) and turn-off loss (E

_{off}) of the DT-MOS was 0.28 mJ/cm

^{2}and 0.47 mJ/cm

^{2}and for the DTC-MOS was 0.26 mJ/cm

^{2}and 0.48 mJ/cm

^{2}. However, for the proposed MOS, the E

_{on}and E

_{off}decreased to 0.09 mJ/cm

^{2}and 0.29 mJ/cm

^{2}. The switching losses (E

_{SW}) consisted of the E

_{on}and E

_{off}; the E

_{SW}of the proposed MOS was 49.3% and 48.6% lower than that of the DT-MOS and DTC-MOS, respectively.

_{t}) consist of conduction power losses and switching losses. When the device is operating under a square wave with a period T and a duty cycle D, the P

_{t}can be expressed as (3):

^{2}, the V

_{ds}was 0.132 V, 0.156 V, and 0.223 V for the DT-MOS, DTC-MOS, and proposed MOS, which is consistent with the R

_{on,sp}. The switching frequency, f, is related to the period, T, by the formula $f=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$T$}\right.$. Although the R

_{on,sp}of the proposed MOS was greater than that of the DT-MOS and DTC-MOS, the switching losses were the main contributor to power loss at high frequencies. Working at high frequencies can effectively reduce the total power losses of the device; it is worth it to increase the on-resistance slightly to achieve smaller switching losses at high frequencies. Figure 9c shows the total power loss as a function of f for the three devices, when a D of 50% was assumed. When the switching frequency was 50 KHz, the proposed MOS achieved the lowest power loss compared to the other devices due to its lower switching loss. At a switching frequency of 200 KHz, the P

_{t}of the proposed MOS was 44.5% lower than the DT-MOS. With increasing f, the deference in P

_{t}between the DT-MOS and the proposed MOS gradually increased.

^{2}) is shown in Figure 10. As the current density increased, both conduction losses and switching losses increased significantly. The E

_{SW}of the three devices is shown in Figure 10a. The proposed MOS value was 0.96 mJ/cm

^{2}, which was 42.9% and 36.4% lower than the DT-MOS and DTC-MOS. However, the conduction losses of the proposed MOS increased faster than the other devices at 500 A/cm

^{2}. As a result, the P

_{t}of the proposed MOS was the highest before f = 200 KHz, as shown in Figure 10b. At a f of 250 KHz, the P

_{t}of the proposed MOS was only 7.6% lower than that of the DT-MOS. Comparing the work conditions between a normal current density and a high current density, it is more favorable for the proposed MOS to work at a normal current density.

## 4. Conclusions

_{F}compared to the DT-MOS and DTC-MOS because of the low barrier diode, which suppresses the conduction of the body diode. This allows the proposed MOS to operate under unipolar operations with reverse conduction, preventing the effects of bipolar degradation. The influence of the main parameters of LBD on device performance has been studied, and the optimal value has been determined. Additionally, the length of the P-shield has been studied to achieve a low E

_{mox}and high blocking voltage. The parameters of the gate trench have also been studied, which show a high process tolerance for forming an L-shape without affecting the static performance.

_{gd}and Q

_{gd}of the three devices were compared. Due to a reduction in the overlap between the gate electrode and drain electrode, the proposed MOS achieved the lowest C

_{gd}and Q

_{gd}. As a result, the proposed MOSFET is able to achieve better switching speeds and lower switching losses. The proposed MOS achieved the lowest total power losses under 50 KHz and higher switching frequencies with a normal current density. This indicates that the proposed MOSFET has more advantages in high frequency switching applications.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

- Millan, J.; Godignon, P.; Perpina, X.; Perez-Tomas, A.; Rebollo, J. A Survey of Wide Bandgap Power Semiconductor Devices. IEEE Trans. Power Electron.
**2014**, 29, 2155–2163. [Google Scholar] [CrossRef] - Hudgins, J.L.; Simin, G.S.; Santi, E.; Khan, M.A. An assessment of wide bandgap semiconductors for power devices. IEEE Trans. Power Electron.
**2003**, 18, 907–914. [Google Scholar] [CrossRef] - Hazra, S.; De, A.K.; Cheng, L.; Palmour, J.; Schupbach, M.; Hull, B.A.; Allen, S.; Bhattacharya, S. High Switching Performance of 1700-V, 50-A SiC Power MOSFET Over Si IGBT/BiMOSFET for Advanced Power Conversion Applications. IEEE Trans. Power Electron.
**2016**, 31, 4742–4754. [Google Scholar] - Tong, Z.K.; Gu, L.; Ye, Z.C.; Surakitbovorn, K.; Rivas-Davila, J. On the Techniques to Utilize SiC Power Devices in High- and Very High-Frequency Power Converters. IEEE Trans. Power Electron.
**2019**, 34, 12181–12192. [Google Scholar] [CrossRef] - Skowronski, M.; Ha, S. Degradation of hexagonal silicon-carbide-based bipolar devices. J. Appl. Phys.
**2006**, 99, 24. [Google Scholar] [CrossRef] - Lendenmann, H.; Dahlquist, F.; Johansson, N.; Soderholm, R.; Nilsson, P.A.; Bergman, J.P.; Skytt, P. Long term operation of 4.5 kV PiN and 2.5 kV JBS diodes. In Materials Science Forum; Trans Tech Publications Ltd.: Zurich-Uetikon, Switzerland, 2000; pp. 353–356. [Google Scholar]
- Aiba, R.; Matsui, K.; Baba, M.; Harada, S.; Yano, H.; Iwamuro, N. Demonstration of Superior Electrical Characteristics for 1.2 kV SiC Schottky Barrier Diode-Wall Integrated Trench MOSFET With Higher Schottky Barrier Height Metal. IEEE Electron. Device Lett.
**2020**, 41, 1810–1813. [Google Scholar] [CrossRef] - An, J.J.; Hu, S.D. SiC trench MOSFET with heterojunction diode for low switching loss and high short-circuit capability. IET Power Electron.
**2019**, 12, 1981–1985. [Google Scholar] [CrossRef] - Sung, W.; Baliga, B.J. On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET). IEEE Trans. Ind. Electron.
**2017**, 64, 8206–8212. [Google Scholar] [CrossRef] - Saito, K.; Miyoshi, T.; Kawase, D.; Hayakawa, S.; Masuda, T.; Sasajima, Y. Simplified Model Analysis of Self-Excited Oscillation and Its Suppression in a High-Voltage Common Package for Si-IGBT and SiC-MOS. IEEE Trans. Electron. Devices
**2018**, 6, 1062–1071. [Google Scholar] [CrossRef] - Hsu, F.J.; Yen, C.T.; Hung, C.C.; Hung, H.T.; Lee, C.Y.; Lee, L.S.; Huang, Y.F.; Chen, T.L.; Chuang, P.J. High performance SiC MOSFET module for industrial applications. In Proceedings of the 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Prague, Czech Republic, 12–16 June 2016; pp. 479–482. [Google Scholar]
- Stevanovic, L.; Rowden, B.; Harfman-Todorovic, M.; Losee, P.; Bolotnikov, A.; Kennerly, S.; Schuetz, T.; Carastro, F.; Datta, R.; Tao, F.; et al. High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier. In Proceedings of the 2017 29th International Symposium on Power Semiconductor Devices and IC’s (ISPSD), Nagoya, Japan, 28 May–1 June 2017; pp. 45–48. [Google Scholar]
- She, X.; Datta, R.; Todorovic, M.H.; Mandrusiak, G.; Dai, J.; Frangieh, T.; Cioffi, P.; Rowden, B.; Mueller, F. High Performance Silicon Carbide Power Block for Industry Applications. IEEE Trans. Ind. Appl.
**2017**, 53, 3738–3747. [Google Scholar] [CrossRef] - Han, Z.L.; Bai, Y.; Chen, H.; Li, C.Z.; Lu, J.; Yang, C.Y.; Yao, Y.; Tian, X.L.; Tang, Y.D.; Song, G.; et al. A Novel 4H-SiC Trench MOSFET Integrated With Mesa-Sidewall SBD. IEEE Trans. Electron. Devices
**2021**, 68, 192–196. [Google Scholar] [CrossRef] - Matsui, K.; Aiba, R.; Yano, H.; Iwamuro, N.; Baba, M.; Harada, S. Comprehensive Study on Electrical Characteristics in 1.2 kV SiC SBD-integrated Trench and Planar MOSFETs. In Proceedings of the 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan, 30 May–3 June 2021; pp. 215–218. [Google Scholar]
- Lin, Z.; Chow, T.P.; Jones, K.A.; Agarwal, A. Design, fabrication, and characterization of low forward drop, low leakage, 1-kV 4H-SiC JBS rectifiers. IEEE Trans. Electron. Devices
**2006**, 53, 363–368. [Google Scholar] [CrossRef] - Zhang, M.; Wei, J.; Zhou, X.; Jiang, H.; Li, B.; Chen, K.J. Simulation Study of a Power MOSFET With Built-in Channel Diode for Enhanced Reverse Recovery Performance. IEEE Electron. Device Lett.
**2019**, 40, 79–82. [Google Scholar] [CrossRef] - Zhou, X.; Pang, H.; Jia, Y.; Hu, D.; Wu, Y.; Tang, Y.; Xia, T.; Gong, H.; Zhao, Y. SiC Double-Trench MOSFETs With Embedded MOS-Channel Diode. IEEE Trans. Electron. Devices
**2020**, 67, 582–587. [Google Scholar] [CrossRef] - Deng, X.; Xu, X.; Li, X.; Li, X.; Wen, Y.; Chen, W. A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance. IEEE Electron. Device Lett.
**2020**, 41, 1472–1475. [Google Scholar] [CrossRef] - Shuming, X.; Changhong, R.; Pang-Dow, F.; Yong, L.; Yi, S. Dummy gated radio frequency VDMOSFET with high breakdown voltage and low feedback capacitance. In Proceedings of the 2000 12th International Symposium on Power Semiconductor Devices & ICs, Proceedings, Toulouse, France, 22–25 May 2000; pp. 385–388. [Google Scholar]
- Wang, Y.; Hu, H.; Jiao, W. Split-Gate-Enhanced UMOSFET With an Optimized Layout of Trench Surrounding Mesa. IEEE Trans. Electron. Devices
**2012**, 59, 3037–3041. [Google Scholar] [CrossRef] - Jiang, H.; Wei, J.; Dai, X.; Ke, M.; Zheng, C.; Deviny, I. Silicon carbide split-gate MOSFET with merged Schottky barrier diode and reduced switching loss. In Proceedings of the 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Prague, Czech Republic, 12–16 June 2016; pp. 59–62. [Google Scholar]
- Zhou, X.; Xiao, H.; Sun, H.; Gao, B.; Liu, X. Physics-based Numerical Modeling for SiC MOSFET Devices. In Proceedings of the 2021 IEEE Sustainable Power and Energy Conference (ISPEC), Nanjing, China, 23–25 December 2021; pp. 3403–3410. [Google Scholar]
- Yang, L.; Bai, Y.; Li, C.; Chen, H.; Han, Z.; Tang, Y.; Hao, J.; Yang, C.; Tian, X.; Lu, J.; et al. Analysis of Mobility for 4H-SiC N/P-Channel MOSFETs Up To 300 °C. IEEE Trans. Electron. Devices
**2021**, 68, 3936–3941. [Google Scholar] [CrossRef] - Kutsuki, K.; Watanabe, Y.; Yamashita, Y.; Soejima, N.; Kataoka, K.; Onishi, T.; Yamamoto, K.; Fujiwara, H. Experimental investigation and modeling of inversion carrier effective mobility in 4H-SiC trench MOSFETs. Solid State Electron.
**2019**, 157, 12–19. [Google Scholar] [CrossRef] - Yang, T.; Wang, Y.; Yue, R. SiC Trench MOSFET With Reduced Switching Loss and Increased Short-Circuit Capability. IEEE Trans. Electron. Devices
**2020**, 67, 3685–3690. [Google Scholar] [CrossRef] - Nakamura, T.; Nakano, Y.; Aketa, M.; Nakamura, R.; Mitani, S.; Sakairi, H.; Yokotsuji, Y. High performance SiC trench devices with ultra-low ron. In Proceedings of the 2011 International Electron Devices Meeting, Washington, DC, USA, 5–7 December 2011; pp. 26.5.1–26.5.3. [Google Scholar]
- Ding, J.; Deng, X.; Li, S.; Wu, H.; Li, X.; Li, X.; Chen, W.; Zhang, B. A Low-Loss Diode Integrated SiC Trench MOSFET for Improving Switching Performance. IEEE Trans. Electron. Devices
**2022**, 69, 6249–6254. [Google Scholar] [CrossRef] - Pu, S.; Yang, F.; Vankayalapati, B.T.; Akin, B. Aging Mechanisms and Accelerated Lifetime Tests for SiC MOSFETs: An Overview. IEEE J. Emerg. Sel. Top. Power Electron.
**2022**, 10, 1232–1254. [Google Scholar] [CrossRef] - Liu, T.; Wong, T.T.Y.; Shen, Z.J. A Survey on Switching Oscillations in Power Converters. IEEE J. Emerg. Sel. Top. Power Electron.
**2020**, 8, 893–908. [Google Scholar] [CrossRef] - Zhou, Y.; Jin, Y.; Xu, H.; Luo, H.; Li, W.; He, X. Heterogeneous Integration of Silicon-Based RC Snubber in SiC Power Module for Parasitic Oscillation Noise Reduction. IEEE Trans. Power Electron.
**2023**, 38, 6902–6906. [Google Scholar] [CrossRef] - Zhang, Z.; Zhang, W.; Wang, F.; Tolbert, L.M.; Blalock, B.J. Analysis of the switching speed limitation of wide band-gap devices in a phase-leg configuration. In Proceedings of the 2012 IEEE Energy Conversion Congress and Exposition (ECCE), Raleigh, NC, USA, 15–20 September 2012; pp. 3950–3955. [Google Scholar]
- Camacho, A.P.; Sala, V.; Ghorbani, H.; Martinez, J.L.R. A Novel Active Gate Driver for Improving SiC MOSFET Switching Trajectory. IEEE Trans. Ind. Electron.
**2017**, 64, 9032–9042. [Google Scholar] [CrossRef] - Yang, X.; Li, J.W.; Ding, Y.F.; Xu, M.W.; Zhu, X.F.; Zhu, J. Observation of Transient Parity-Time Symmetry in Electronic Systems. Phys. Rev. Lett.
**2022**, 128, 06571. [Google Scholar] [CrossRef] [PubMed]

**Figure 1.**Schematic cross-sectional structures of the (

**a**) DT-MOS, (

**b**) DTC-MOS, and (

**c**) proposed MOSFET.

**Figure 3.**(

**a**) Influence of D

_{Nb}and W

_{Nb}on BV and V

_{F}; (

**b**) BV, V

_{F}at different L

_{Psh}and N

_{Nb}.

**Figure 4.**(

**a**) Parasitic capacitance for the C

_{gd}of the proposed MOS. (

**b**) Influence of device characteristics on the distance between the gate and gate-source (

**c**) Influence of C

_{gd}and R

_{on,sp}on the thickness of the gate-source.

**Figure 5.**(

**a**) BV characteristics (

**b**) electric field distributions with a drain bias at 1200 V of the DT-MOSF, DTC-MOS, and proposed MOS.

**Figure 6.**(

**a**) I–V characteristics of the three devices; (

**b**) hole concentration distributions at I

_{s}= 100 A/cm

^{2}.

**Figure 9.**The switching waveforms of the DT-MOS, DTC-MOS, and Proposed MOS, respectively; (

**a**) Turn-on and turn-off waveforms; (

**b**) Turn-on loss and turn-off loss waveforms; (

**c**) total power losses as a function of switching frequency f; (

**d**) resistance switching circuit for simulations.

**Figure 10.**Device works at 500 A/cm

^{2}; (

**a**) Turn-on loss and turn-off loss waveforms; (

**b**) total power losses as a function of switching frequency f.

**Figure 11.**Key fabrication process flows for the proposed MOSFET: (

**a**) Form P-shield layer. (

**b**) Form P-base layer and N-source layer. (

**c**) Etch to form gate trench and form oxide by CVD to form the gate oxide; deposit and etch polysilicon to form gate-source. (

**d**) Deposit oxide and polysilicon to form gate. (

**e**) Etch to form source trench and ion implantation to form the P+. (

**f**) Form source electrode.

Symbol | Description | DT-MOS | DTC-MOS | Proposed MOS |
---|---|---|---|---|

W_{cell} | Width of cell pitch, μm | 3.8 | 4.2 | 4.2 |

t_{ox} | Thickness of gate oxide, nm | 50 | 50 | 50 |

t_{c} | Thickness of gate oxide, nm | 50 | 20 | 50 |

W_{ST} | Width of source trench, μm | 0.6 | 0.7 | 0.7 |

W_{GT} | Width of gate trench, μm | 1 | 1.2 | 1.2 |

T_{Nd} | Thickness of N-drift, μm | 9 | 9 | 9 |

N_{Nd} | Concentration of N-drift, cm^{−3} | 8 × 10^{15} | 8 × 10^{15} | 8 × 10^{15} |

Symbol | DT-MOS | DTC-MOS | Proposed MOS |
---|---|---|---|

BV [V] | 1434 | 1343 | 1411 |

E_{mox} [V cm^{−1}] | 4.71 | 4.11 | 2.52 |

V_{F} [V] | 2.86 | 2.63 | 0.85 |

R_{on,sp} [mΩ∙cm^{2}] | 1.42 | 1.56 | 2.23 |

Q_{gd} [nC/cm^{2}] | 569 | 406 | 6.7 |

E_{on} [mJ/cm^{2}] | 0.28 | 0.26 | 0.09 |

E_{off} [mJ/cm^{2}] | 0.47 | 0.48 | 0.29 |

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## Share and Cite

**MDPI and ACS Style**

Ou, Y.; Lan, Z.; Hu, X.; Liu, D.
Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed. *Micromachines* **2024**, *15*, 254.
https://doi.org/10.3390/mi15020254

**AMA Style**

Ou Y, Lan Z, Hu X, Liu D.
Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed. *Micromachines*. 2024; 15(2):254.
https://doi.org/10.3390/mi15020254

**Chicago/Turabian Style**

Ou, Yangjie, Zhong Lan, Xiarong Hu, and Dong Liu.
2024. "Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed" *Micromachines* 15, no. 2: 254.
https://doi.org/10.3390/mi15020254