Search Results (208)

Channel length modulation (CLM) in indium gallium zinc oxide (IGZO) thin film transistors (TFTs) reduces the output resistance (r_o) in the saturation regime. It also degrades current driving accuracy for active matrix organic light emitting diode (AMOLED) backplanes. For top gate, self-aligned devices with nominal channel lengths of 5–15 μm, transmission line method (TLM) analysis yields an effective channel length reduction (ΔL) of about 1.8 μm. This result is consistent with lateral hydrogen redistribution from the self-aligned source/drain (S/D) process. At L = 5 μm, the conventional TFT exhibits r_o = 13.5 ± 2.5 MΩ and an Early voltage (V_A) = 56.1 ± 10.4 V (n = 5). We propose a source connected bottom gate (SCBG) structure that electrostatically stabilizes the pinch-off region and suppresses CLM. The SCBG TFT increases r_o to 475 ± 52 MΩ and V_A to 1159 ± 173 V at L = 5 μm (n = 5), while maintaining normal transfer characteristics. Two-dimensional device simulations reproduce the trend and show that the drain-bias-induced pinch-off shift is reduced, with d(ΔL)/dV_DS decreasing from 0.027 to 0.012 μm/V (about 55%). These results indicate that the SCBG approach is effective for enhancing current saturation in short channel IGZO TFTs for high-resolution AMOLED applications. Full article

We present a methodology that enhances the analytical performance of organic electrochemical transistors (OECTs) by continuously cycling the devices through gate potential sweeps during sensing experiments. This continuous cycling methodology (CCM) enables real-time acquisition of full transfer curves, allowing simultaneous monitoring of multiple characteristic parameters. We show that the simultaneous temporal evolution of several OECT response parameters (threshold voltage (V_TH), maximum transconductance (g_max), and maximum transconductance potential (V_G,gmax)) provides highly sensitive descriptors for detecting pH changes and macromolecule adsorption on OECTs based on polyaniline (PANI) and poly(3,4-ethylenedioxythiophene) (PEDOT) channels. Moreover, the method allows reconstruction of I_DS–t (drain–source current vs. time) profiles at any selected gate potential, enabling the identification of optimal gate voltage (V_G) values for maximizing sensitivity. This represents a substantial improvement over traditional measurements at fixed V_G, which may suffer from reduced sensitivity and parasitic reactions associated with gate polarization. Moreover, the expanded set of parameters obtained with the CCM provides deeper insight into the physicochemical processes occurring at both gate and channel electrodes. We demonstrate its applicability in monitoring polyelectrolyte and enzyme adsorption, and detecting urea and glucose through enzyme-mediated reactions. Owing to its versatility and the richness of the information it provides, the CCM constitutes a significant advance for the development and optimization of OECT-based sensing platforms. Full article

Gallium nitride (GaN)-based high electron mobility transistors (HEMTs) are pivotal for next-generation power-switching applications, but their reliability under high electric fields remains constrained by lattice mismatches and high dislocation densities in heterogeneous substrates. Herein, we systematically investigate the electrical performance and reliability of GaN-on-GaN HEMTs in comparison to conventional GaN-on-SiC HEMTs via DC characterization, reverse gate step stress, off-state drain step stress, and on-state electrical stress tests. Notably, the homogeneous epitaxial structure of GaN-on-GaN devices reduces dislocation density by 83.3% and minimizes initial tensile stress, which is obtained through HRXRD and Raman spectroscopy. The GaN-on-GaN HEMTs exhibit a record BFOM of 950 MW/cm², enabled by a low specific on-resistance (R_ON-SP) of 0.6 mΩ·cm² and a high breakdown voltage (BV) of 755 V. They withstand gate voltages up to −200 V and drain voltages beyond 200 V without significant degradation, whereas GaN-on-SiC HEMTs fail at −95 V (reverse gate stress) and 150 V (off-state drain stress). The reduced dislocation density suppresses leakage channels and defect-induced degradation, as confirmed by post-stress Schottky/transfer characteristics and Frenkel–Poole emission analysis. These findings establish GaN-on-GaN technology as a transformative solution for power electronics, offering a unique combination of high efficiency and long-term stability for demanding high-voltage applications. Full article

NMOSFET, whose gate is on the top of the n-p-n junction with gate oxide in between, is called the n-channel transistor. This bipolar junction underneath the gate oxide may provide an n-n-n-conductive channel as the gate is applied with a positive bias over the threshold voltage (V_th). Conceptually, the definition of an n-type or p-type semiconductor depends on whether the corresponding Fermi energy is higher or lower than the intrinsic Fermi energy, respectively. The positive bias applied to the gate would bend down the intrinsic Fermi energy until it is lower than the original p-type Fermi energy, which means that the p-type becomes strongly inverted to become an n-type. First, the thickness of the inversion layer is derived and presented in a planar 40 nm MOSFET, a 3D 240 nm FinFET, and a power discrete IGBT, with the help of the p (1/m³) of the p-type semiconductor. Different ways of finding p (1/m³) are, thus, proposed to resolve the strong inversion layers. Secondly, the conventional formulas, including the triode region and saturation region, are already modified, especially in the triode region from a continuity point of view. The modified formulas then become necessary and available for fitting the measured characteristic curves at different applied gate voltages. Nevertheless, they work well but not well enough. Thirdly, the electromagnetic wave (EM wave) generated from accelerating carriers (radiation by accelerated charges, such as synchrotron radiation) is proposed to demonstrate phonon scattering, which is responsible for the Source–Drain current reduction at the adjoining of the triode region and saturation region. This consideration of reduction makes the fitting more perfect. Fourthly, the strongly inverted layer may be formed but not conductive. The existing trapping would stop carriers from moving (nearly no mobility, μ) unless the applied gate bias is over the threshold voltage. The quantum confinement addressing the quantum well, which traps the carriers, is to be estimated. Full article

Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device characteristics, and, to study this effect, this work investigates the impact of RITs on the DC/AC/RF characteristic fluctuations of FinFETs. Under high gate bias, the device screening effect suppresses large fluctuations induced by RITs. In relation to different densities of interface traps (D_it), fluctuations of short-channel effects, including potential barriers and current densities, are analyzed. Bulk FinFETs exhibit entirely different variability, despite having the same number of RITs. Potential barriers are significantly altered when devices with RITs are located near the source end. An analysis and a discussion of RIT-fluctuated gate capacitances, transconductances, cut-off, and 3-dB frequencies are provided. Under high D_it conditions, we observe ~146% variation in off-state current, ~26% in threshold voltage, and large fluctuations of ~107% and ~131% in gain and cut-off frequency, respectively. The effects of the random position of RITs on both AC and RF characteristic fluctuations are also discussed and designed in three different scenarios. Across all densities of interface traps, the device with RITs near the drain end exhibits relatively minimal fluctuations in gate capacitance, voltage gain, cut-off, and 3-dB frequencies. Full article

In this study, the nonlinearity characteristics of bilayer graphene field-effect transistors (Bi-GFETs) are analyzed by using a small-signal equivalent circuit. The static nonlinearity is determined by applying mathematical operation on the drain current equation of Bi-GFETs. Furthermore, the closed expressions for the second- and third-order harmonic distortion (HD) and the intermodulation (IM) distortion of the second- and third-order for Bi-GFETs are analyzed graphically. Dynamic nonlinearity is studied and illustrated in the results by examining the input and output characteristics; i.e., the drain current versus the negative drain to the source voltage and the transfer characteristic curve at various gate voltages controlled by both the top gate as well as the back gate. The characteristic behavior of the gate voltage in Bi-GFETs at short channel lengths is observed and compared; that is, the characteristic curves exhibits strong nonlinearity, with a low power point with some kinks at high gate biasing and a constant linear region at low gate biasing. The quantitative values of the second-order harmonic distortion (HD) and intermodulation distortion (IM) of the proposed analytical model are −40 dB and −45 dB. Quantitative and qualitative outcomes of the characteristics of Bi-GFETs are compared with existing experimental data, which is available in the literature. Full article

This study examines the performance of a GaN HEMT with a 150 nm gate length, fabricated on silicon carbide, across various operational modes, including direct current (DC), radio frequency (RF), and small-signal parameters. The evaluation of DC, RF, and small-signal performance under diverse bias conditions remains a relatively unexplored area of study for this specific technology. The DC characteristics revealed relatively little I_ds at zero gate and drain voltages, and the current grew as V_gs increased. Essential measurements include I_dss at 109 mA and I_dssm at 26 mA, while the peak g_m was 62 mS. Because transconductance is sensitive to variations in V_gs and V_ds, it shows “Vth _roll-off,” where Vth decreases as V_ds increases. The transfer characteristics corroborated this trend, illustrating the impact of drain-induced barrier lowering (DIBL) on threshold voltage (Vth) values, which spanned from −5.06 V to −5.71 V across varying drain-source voltages (V_ds). The equivalent-circuit technique revealed substantial non-linear behaviors in capacitances such as C_gs and C_gd concerning V_gs and V_ds, while also identifying extrinsic factors including parasitic capacitances and resistances. Series resistances (R_gs and R_gd) decreased as V_gs increased, thereby enhancing device conductivity. As V_gs approached neutrality, particularly at elevated V_ds levels, the intrinsic transconductance (g_mo) and time constants (τ_gm, τ_gs, and τ_gd) exhibited enhanced performance. f_t and f_max, which are essential for high-frequency applications, rose with decreasing V_gs and increasing V_ds. When V_gs approached −3 V, the S₂₁ and Y₂₁ readings demonstrated improved signal transmission, with peak S₂₁ values of approximately 11.2 dB. The stability factor (K), which increased with V_ds, highlighted the device’s operational limits. The robust correlation between simulation and experimental data validated the equivalent-circuit model, which is essential for enhancing design and creating RF circuits. Further examination of bias conditions would enhance understanding of the device’s performance. Full article

In this study, we propose a bidirectional chemical sensor platform based on a reconfigurable ion-sensitive field-effect transistor (R-ISFET) architecture. The device incorporates Ni-silicide Schottky barrier source/drain (S/D) contacts, enabling ambipolar conduction and bidirectional turn-on behavior for both p-type and n-type configurations. Channel polarity is dynamically controlled via the program gate (PG), while the control gate (CG) suppresses leakage current, enhancing operational stability and energy efficiency. A dual-control-gate (DCG) structure enhances capacitive coupling, enabling sensitivity beyond the Nernst limit without external amplification. The extended-gate (EG) architecture physically separates the transistor and sensing regions, improving durability and long-term reliability. Electrical characteristics were evaluated through transfer and output curves, and carrier transport mechanisms were analyzed using band diagrams. Sensor performance—including sensitivity, hysteresis, and drift—was assessed under various pH conditions and external noise up to 5 V_pp (i.e., peak-to-peak voltage). The n-type configuration exhibited high mobility and fast response, while the p-type configuration demonstrated excellent noise immunity and low drift. Both modes showed consistent sensitivity trends, confirming the feasibility of complementary sensing. These results indicate that the proposed R-ISFET sensor enables selective mode switching for high sensitivity and robust operation, offering strong potential for next-generation biosensing and chemical detection. Full article

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

Aiming at the problems of low withstand voltage and poor RF performance of traditional HEMT devices, a new AlGaN/GaN high electron mobility transistor device with a π-gate (NπGS HEMT) is designed in this paper. The new structure incorporates a π-gate design along with a PN-junction field plate and an AlGaN back-barrier layer. The device is modeled and simulated in Silvaco TCAD 2015 software and compared with traditional t-gate HEMT devices. The results show that the NπGS HEMT has a significant improvement in various characteristics. The new structure has a higher peak transconductance of 336 mS·mm⁻¹, which is 13% higher than that of the traditional HEMT structure. In terms of output characteristics, the new structure has a higher saturation drain current of 0.188 A/mm. The new structure improves the RF performance of the device with a higher maximum cutoff frequency of about 839 GHz. The device also has a better performance in terms of voltage withstand, exhibiting a higher breakdown voltage of 1817 V. These results show that the proposed new structure could be useful for future research on high voltage withstand and high RF HEMT devices. Full article

Nanoparticle floating gate (NPFG) transistors have gained attention as synaptic devices due to their discrete charge storage capability, which minimizes leakage currents and enhances the memory window. In this study, we propose and evaluate a mesh-type floating gate transistor (Mesh-FGT) designed to emulate the characteristics of NPFG transistors. Individual floating gates with dimensions of 3 µm × 3 µm are arranged in an array configuration to form the floating gate structure. The Mesh-FGT is composed of an Al/Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/SOI (silicon-on-insulator) stack. Threshold voltages (Vth) extracted from the transfer and output curves followed Gaussian distributions with means of 0.063 V (σ = 0.100 V) and 1.810 V (σ = 0.190 V) for the erase (ERS) and program (PGM) states, respectively. Synaptic potentiation and depression were successfully demonstrated in a multi-level implementation by varying the drain current (I_ds) and Vth. The Mesh-FGT exhibited high immunity to leakage current, excellent repeatability and retention, and a stable memory window that initially measured 2.4 V. These findings underscore the potential of the Mesh-FGT as a high-performance neuromorphic device, with promising applications in array device architectures and neuromorphic neural network implementations. Full article

To enhance the DC and RF performance of AlGaN/GaN HEMTs, a novel device structure was proposed and investigated through simulation. The key innovation of this new structure lies in the incorporation of an Al_0.7In_0.15Ga_0.15N back-barrier layer and an N-type locally doped AlGaN barrier layer (BD-HEMT), based on conventional device architecture. The Al_0.7In_0.15Ga_0.15N back-barrier layer effectively confines electrons within the channel, thereby increasing the electron concentration. Simultaneously, the N-type locally doped AlGaN barrier layer introduced beneath the gate supplies additional electrons to the channel, further enhancing the electron density. These modifications collectively lead to improved DC and RF characteristics of the device. Compared to the conventional AlGaN/GaN HEMT, BD-HEMT achieves a 24.8% increase in saturation drain current and a 10.4% improvement in maximum transconductance. Furthermore, the maximum cutoff frequency and maximum oscillation frequency are enhanced by 14.8% and 21.2%, respectively. Full article

In this study, a novel silicon carbide (SiC) double-trench MOSFET (DT-MOS) combined Schottky barrier diode (SBD) and MOS-channel diode (MCD) is proposed and investigated using TCAD simulations. The integrated MCD helps inactivate the parasitic body diode when the device is utilized as a freewheeling diode, eliminating bipolar degradation. The adjustment of SBD position provides an alternative path for reverse conduction and mitigates the electric field distribution near the bottom source trench region. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate the proposed structure with both SBD and MCD has advantages in switching and breakdown characteristics. Full article

A dual Al₂O₃ MIS gate structure is proposed to enhance the DC and RF performance of enhancement-mode GaN high-electron mobility transistors (HEMTs). As a result, the proposed MOS-HEMT with a dual recessed MIS gate structure offers 84% improvements in cutoff frequency (f_T) and 92% improvements in maximum oscillation frequency (f_max) compared to conventional HEMTs (from 7.1 GHz to 13.1 GHz and 17.5 GHz to 33.6 GHz, respectively). As for direct-current characteristics, a remarkable reduction in off-state gate leakage current and a 26% enhancement in the maximum saturation drain current (from 519 mA·mm⁻¹ to 658 A·mm⁻¹) are manifested in HEMTs with new structures. The maximum transconductance (g_m) is also raised from 209 mS·mm⁻¹ to 246 mS·mm⁻¹. Correspondingly, almost unchanged gate–source capacitance curves and gate–drain capacitance curves are also discussed to explain the electrical characteristic mechanism. These results indicate the superiority of using a dual Al₂O₃ MIS gate structure in GaN-based HEMTs to promote the RF and DC performance, providing a reference for further development in a miniwatt antenna amplifier and sub-6G frequencies of operation. Full article