New Trends in the Modeling and Design of Micro/Nano-Devices

A special issue of Processes (ISSN 2227-9717). This special issue belongs to the section "Materials Processes".

Deadline for manuscript submissions: 15 December 2025 | Viewed by 485

Special Issue Editors


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Guest Editor
Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu 300093, Taiwan
Interests: semiconductor devices; computational electronics; nano-electronics; semiconductor device modeling; numerical simulation

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Guest Editor Assistant
Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu 300093, Taiwan
Interests: device modeling and simulation

Special Issue Information

Dear Colleagues,

The Special Issue “New Trends in the Modeling and Design of Micro/Nano-Devices” covers all aspects of the advanced modeling, simulation, and optimization of electronic transport, thermal conduction, and optoelectronic processes in semiconductor materials, structures, and devices ranging from micro- to nano-meter regimes. Topics of the Special Issue include the following: (1) modeling and simulation, as well as classical and quantum-mechanical transports of all types of semiconductor devices; (2) thermal transport, as well as optoelectronic processes and multiscale phenomena; (3) machine learning, deep learning, and artificial intelligence for device modeling and simulation; (4) modeling and simulation of all sorts of semiconductor processes, including first-principles calculations in the context of transport studies; and (5) novel designs for micro- and nano-devices.

This Special Issue is the leading forum for discussions on current trends and future directions of computational semiconductor materials, structures, and micro/nano-devices. It provides an open forum for the presentation of leading-edge research and development results in the area of the modeling, simulation, and optimization of micro/nano-devices, which is mainly devoted to technology computer-aided design and the advanced modeling of novel semiconductor materials and devices, as well as nano-electronic structures. Emphasis is placed on the interdisciplinary aspects of computational designs, which combine a diverse range of fields, including electronic devices, physics, and simulation, as well as modeling and optimization.

Prof. Dr. Yiming Li
Guest Editor

Dr. Sekhar Reddy Kola
Guest Editor Assistant

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Keywords

  • computational design for all micro/nano-devices
  • multiphysics
  • modeling, simulation, and optimization
  • learning-based methodologies

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Published Papers (1 paper)

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Research

24 pages, 6128 KB  
Article
DC/AC/RF Characteristic Fluctuation of N-Type Bulk FinFETs Induced by Random Interface Traps
by Sekhar Reddy Kola and Yiming Li
Processes 2025, 13(10), 3103; https://doi.org/10.3390/pr13103103 - 28 Sep 2025
Viewed by 297
Abstract
Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device [...] Read more.
Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device characteristics, and, to study this effect, this work investigates the impact of RITs on the DC/AC/RF characteristic fluctuations of FinFETs. Under high gate bias, the device screening effect suppresses large fluctuations induced by RITs. In relation to different densities of interface traps (Dit), fluctuations of short-channel effects, including potential barriers and current densities, are analyzed. Bulk FinFETs exhibit entirely different variability, despite having the same number of RITs. Potential barriers are significantly altered when devices with RITs are located near the source end. An analysis and a discussion of RIT-fluctuated gate capacitances, transconductances, cut-off, and 3-dB frequencies are provided. Under high Dit conditions, we observe ~146% variation in off-state current, ~26% in threshold voltage, and large fluctuations of ~107% and ~131% in gain and cut-off frequency, respectively. The effects of the random position of RITs on both AC and RF characteristic fluctuations are also discussed and designed in three different scenarios. Across all densities of interface traps, the device with RITs near the drain end exhibits relatively minimal fluctuations in gate capacitance, voltage gain, cut-off, and 3-dB frequencies. Full article
(This article belongs to the Special Issue New Trends in the Modeling and Design of Micro/Nano-Devices)
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