Enhanced Current Saturation in IGZO Thin Film Transistors Using a Source-Connected Bottom Gate Structure

Highlights

What are the main findings?

• SCBG (source-connected bottom gate) improves drain current saturation in short-channel IGZO TFTs.
• For L = 5 μm, r_o = 475 MΩ and V_A = 1.2 kV.
• SCBG suppresses channel length modulation, reducing d(ΔL)/dV_DS by ~55%.
• Simulations show slower drain-side depletion growth with increasing V_DS in SCBG.

What are the implications of the main findings?

• SCBG mitigates channel length modulation.
• Electrostatic scheme compatible with self-aligned IGZO TFT process flows.
• Improved current saturation can stabilize OLED driving TFT operation at scaled L.

Abstract

Channel length modulation (CLM) in indium gallium zinc oxide (IGZO) thin film transistors (TFTs) reduces the output resistance (r_o) in the saturation regime. It also degrades current driving accuracy for active matrix organic light emitting diode (AMOLED) backplanes. For top gate, self-aligned devices with nominal channel lengths of 5–15 μm, transmission line method (TLM) analysis yields an effective channel length reduction (ΔL) of about 1.8 μm. This result is consistent with lateral hydrogen redistribution from the self-aligned source/drain (S/D) process. At L = 5 μm, the conventional TFT exhibits r_o = 13.5 ± 2.5 MΩ and an Early voltage (V_A) = 56.1 ± 10.4 V (n = 5). We propose a source connected bottom gate (SCBG) structure that electrostatically stabilizes the pinch-off region and suppresses CLM. The SCBG TFT increases r_o to 475 ± 52 MΩ and V_A to 1159 ± 173 V at L = 5 μm (n = 5), while maintaining normal transfer characteristics. Two-dimensional device simulations reproduce the trend and show that the drain-bias-induced pinch-off shift is reduced, with d(ΔL)/dV_DS decreasing from 0.027 to 0.012 μm/V (about 55%). These results indicate that the SCBG approach is effective for enhancing current saturation in short channel IGZO TFTs for high-resolution AMOLED applications.

1. Introduction

Amorphous indium gallium zinc oxide (IGZO) has been widely studied as a channel material for thin film transistors (TFTs) in backplanes for active matrix organic light emitting diode (AMOLED) displays. This interest is driven by its high field effect mobility, low leakage current, and compatibility with large area fabrication processes [1,2]. IGZO TFTs can achieve field effect mobility above 10 cm²/V∙s even in the amorphous phase, which is advantageous for high resolution displays [3,4]. In addition, IGZO TFTs can be fabricated at low process temperatures below 300 °C on large-area substrates, making it attractive for next generation applications such as flexible and transparent displays [5,6].

In high-resolution AMOLED displays, the area occupied by TFTs in each pixel must be reduced to maximize the pixel aperture ratio and achieve high brightness at low power consumption. This requirement inevitably drives the downscaling of TFT dimensions, particularly the channel length. Modern high-resolution displays with pixel densities exceeding 500 ppi demand TFTs with channel lengths approaching 5 μm or even shorter [7,8]. However, as the channel length decreases, various short channel effects emerge, among which channel length modulation (CLM) is particularly detrimental to the current driving capability required for AMOLED operation. CLM refers to the phenomenon in which the effective channel length decreases as the drain–source voltage increases in the saturation regime, causing the drain current to continue increasing rather than remaining constant [9]. In a typical 2T1C (two transistors and one capacitor) pixel circuit, the driving TFT is intended to operate in the saturation mode. It is desirable that the drain current remains nearly independent of the drain voltage so that the OLED current is accurately determined by the data voltage [10]. Therefore, suppressing CLM is crucial for achieving stable pixel operation in high-resolution AMOLED displays.

In our IGZO TFTs, however, we observed a markedly enhanced CLM when the channel length (L) was reduced to ~5 μm. The drain current strongly depended on the drain voltage, and the slope of the output characteristics in the saturation regime was much larger than that of the long-channel devices. This degradation in current saturation has a serious impact on the ability of the driving TFT to supply stable current in AMOLED pixels. Notably, a channel length of 5 μm is not extremely short by conventional TFT standards [11,12]. This suggests that specific factors inherent to our IGZO TFT fabrication process may be contributing to the enhanced CLM beyond simple geometric scaling effects.

A distinctive feature of our IGZO TFT fabrication process is the use of in situ hydrogen doping during silicon nitride (SiN_x) passivation layer deposition to form low resistance source/drain (S/D) regions. This approach has been widely reported in the literature [13,14,15]. During SiN_x deposition by plasma enhanced chemical vapor deposition (PECVD), hydrogen radicals diffuse in IGZO, and they act as n-type dopants. We hypothesize that lateral hydrogen diffusion from the S/D regions into the channel shortens the effective channel length. This mechanism may be a primary contributor to the enhanced CLM observed in short channel devices. The major pathway is hypothesized to be through the silicon dioxide (SiO₂) layer, which will be discussed based on the cross-sectional structure in the following sections.

In this work, we focus on IGZO TFTs with L = 5 μm that exhibit pronounced CLM compared with long-channel devices. First, we perform transmission line method (TLM) analysis on fabricated devices with various channel lengths to experimentally quantify the effective channel length. In order to improve current saturation, we propose a source-connected bottom gate (SCBG) structure. From device fabrication results, we show that the proposed SCBG structure suppresses this effect through enhanced electrostatic control of the channel. Finally, we support the effect of the SCBG structure on the suppression of pinch-off point shift using physics-based device simulations performed with COMSOL Multiphysics (ver. 5.3).

2. Device Structure and Fabrication

Conventional IGZO TFTs were fabricated with a top gate structure, as shown in Figure 1. Figure 1a illustrates the hydrogen doping process during the SiN_x passivation layer deposition, showing the diffusion pathways of hydrogen radicals, and Figure 1b shows the cross-sectional schematic of the completed device structure. The channel width was fixed at 15 μm. The channel length (L) was varied from 5 to 15 μm (5, 7.5, 10, and 15 μm) to investigate the dependence of the electrical characteristics on channel length.

The fabrication sequence began with the deposition of a buffer layer on a glass substrate. A 300 nm thick silicon dioxide (SiO₂) buffer layer was deposited by PECVD at 200 °C to provide electrical isolation and surface smoothing. A 50 nm thick IGZO film was subsequently deposited by radio frequency (RF) magnetron sputtering at room temperature. A target with In:Ga:Zn = 1:1:1 at. % was used in an Ar/O₂ mixture (95/5). The IGZO layer was patterned by wet etching to define the active island. Next, a 200 nm thick SiO₂ gate insulator was deposited by PECVD at 250 °C. A 100 nm thick molybdenum (Mo) film was deposited by sputtering and patterned to form the top gate electrode. All film thicknesses were controlled by calibrated deposition rates and deposition time, and were verified by ellipsometry for inorganic dielectric films and by stylus profilometry for metal layers.

Hydrogen plasma doping for S/D formation was carried out by in situ hydrogen incorporation during deposition of the SiN_x passivation layer. In our study, a 200 nm thick SiN_x passivation layer was deposited by PECVD at 250 °C. During the SiN_x deposition, the S/D regions were self-aligned to the top gate electrode because hydrogen radicals were blocked by the Mo gate. Therefore, only the IGZO regions not covered by the gate were selectively doped. As schematically illustrated in Figure 1a, hydrogen radicals diffuse not only vertically through the SiO₂ gate insulator but also laterally within the SiO₂ gate insulator toward the channel region. We hypothesize that the effective channel length is reduced by lateral hydrogen diffusion mediated by the gate insulator, which extends the doped regions into the channel. Contact holes were subsequently opened through the SiN_x and SiO₂ layers by dry etching. Finally, a 100 nm thick Mo contact metal was deposited by sputtering and patterned to form the S/D electrodes. All devices underwent post-annealing at 250 °C for 1 h in ambient air to stabilize the electrical performance and activate the hydrogen dopants.

For the SCBG devices, the process flow was identical to that of the conventional devices except that two additional steps were inserted between the SiO₂ buffer layer deposition and the IGZO deposition. After depositing the 300 nm thick buffer layer on the glass substrate, a 100 nm thick molybdenum (Mo) film was deposited by sputtering and patterned to form the bottom gate electrode. Subsequently, a 200 nm thick SiO₂ bottom gate oxide was deposited by PECVD at 250 °C. After these steps, the IGZO active layer was deposited and patterned in the same manner as in the conventional devices, and all subsequent steps were identical to those used for the conventional devices. The detailed device structure is presented in Section 3.2.

3. Results and Discussions

3.1. Device Characteristics as a Function of Channel Length

The electrical characteristics of the fabricated conventional IGZO TFTs were measured at room temperature using an Agilent 4156C semiconductor parameter analyzer (Agilent Technologies, Santa Clara, CA, USA). Transfer characteristics (I_D–V_GS) were obtained by sweeping the gate–source voltage (V_GS) from −15 V to 20 V at a fixed drain–source voltage (V_DS) of 1 V. Output characteristics (I_D–V_DS) were measured by sweeping V_DS from 0 to 15 V at a fixed V_GS of 4 V. Figure 2a shows the I_D–V_GS curves for devices with channel lengths of 5, 7.5, 10, and 15 μm. The threshold voltage (Vth) and the field effect mobility (μ_eff) were extracted using the linear extrapolation method in the linear regime, where V_GS − Vth > V_DS. Specifically, Vth was determined from the V_GS-axis intercept (V_int) of a linear fit to the I_D–V_GS curve. It was then corrected as Vth = V_int − V_DS/2. This correction is used because the intercept corresponds to Vth + V_DS/2 in the standard MOSFET linear regime expression. The extracted Vth ranged from −0.19 to 0.23 V across L = 5–15 μm, and μ_eff waw around 9.0 cm²/V∙s, respectively. These values are consistent with those reported for IGZO TFTs with hydrogen-doped S/D in the literature [13,14].

Figure 2b presents the I_D–V_DS curves for the same set of devices. A clear difference in current saturation behavior is observed as a function of channel length. The L = 15 μm and L = 10 μm devices exhibit well-defined current saturation, indicating weak CLM. In contrast, the L = 7.5 μm device shows a moderate increase in the drain current with V_DS, and the L = 5 μm device displays a severe current rise in the saturation regime. To quantitatively assess the CLM effect, we extracted the output resistance (r_o = (dI_D/dV_DS)⁻¹) which is the inverse of the slope of the I_D–V_DS curve in the saturation regime (V_DS = 10–15 V). The average value of r_o for the L = 5 μm device is 13.5 MΩ, and that for the L = 15 μm device is 53.6 MΩ which is 4 times higher. This result demonstrates that short channel IGZO TFTs suffer from stronger CLM than their long channel counterparts. Specifically, in the saturation regime, I_D–V_DS curves are linearly fitted as I_D = (1/r_o) × V_DS + I_D0, where I_D0 is the extrapolated current obtained from the y-intercept of the above linear fit. The CLM is often quantified by the Early voltage which is defined as V_A = I_D0 × r_o, which corresponds to the absolute value of extrapolated x-intercept of the aforementioned linear fit. The Early voltage (V_A) for the L = 5 μm device is approximately 56 V. Reproducibility of the transfer and output characteristics is provided in Figure A1 and Figure A2 in Appendix A. Device-to-device statistics of Vth, r_o, and V_A are summarized in Section 3.2.

To investigate the effective channel length of the fabricated devices, we performed transmission line method (TLM) analysis [16,17,18]. Using the drain current values measured at V_DS = 1 V for three different gate voltages (V_GS = 10, 15, and 20 V), we calculated the total source-to-drain resistance. Heare, R_T = R_ch + R_s. R_ch is the channel resistance dependent on V_GS, whereas R_s is the independent series resistance incorporating S/D and contact resistances. For each channel length, five devices were measured. R_T was calculated for each device. The symbols and error bars in Figure 3 represent mean ± standard deviation (SD) (n = 5). Figure 3 plots the R_T versus the nominal (designed) channel length for three V_GS conditions, where the extrapolated lines do not converge at the positive y-axis. The nominal channel length was defined by the top gate pattern, and it was verified by an optical microscope after fabrication. In standard TLM analysis, the extrapolated lines for different gate voltages should intersect at a point on the positive y-axis, and this y-intercept represents R_s. However, the fact that our intersection point does not lie on the positive y-axis indicates that the nominal channel lengths do not accurately represent the effective channel lengths. As shown in Figure 3, the three extrapolated lines converge at a point of (1.8 μm, 18.6 kΩ). According to conventional TLM interpretation, a non-zero x-coordinate of the intersection indicates channel length reduction [17]. We define ΔL ≈ 1.8 μm as the difference between the nominal channel length (L) and the effective channel length (L_eff).

As described in Section 2, hydrogen is intentionally introduced as an n-type dopant during the SiN_x passivation layer deposition at 250 °C by PECVD. The dopants are activated during the subsequent post-annealing step at 250 °C for 1 h. During SiN_x deposition, hydrogen diffuses not only vertically into the IGZO S/D regions but also laterally within the 200 nm thick SiO₂ gate insulator as illustrated in Figure 1a. Because the hydrogen diffusion coefficient in SiO₂ is substantially higher than that in IGZO, the gate insulator can be a dominant diffusion pathway for hydrogen in our devices. To assess the plausibility of this hypothesis, we compare the hydrogen diffusion coefficients in the literature. Nomura et al. reported a hydrogen diffusion coefficient of 2.6 × 10⁻¹⁵ cm²/s at 200 °C in IGZO [19]. The diffusion coefficient at 250 °C can be estimated as 1.7 × 10⁻¹⁴ cm²/s using the Arrhenius equation and an activation energy (E_a) of 0.89 eV. In contrast, Shang et al. reported a hydrogen diffusion coefficient of 2.4 × 10⁻⁸ cm²/s at 250 °C in SiO₂ [20]. This value is more than six orders of magnitude larger than the estimated value in IGZO at 250 °C. Such a large contrast supports that lateral hydrogen transport within the SiO₂ gate insulator can occur much more readily than through the IGZO layer itself. Therefore, even though the lateral diffusion length cannot be uniquely determined with the literature values alone, it can depend on microstructure such as film thickness and layer stack. Nevertheless, the gate insulator provides a physically plausible and potentially dominant pathway for lateral hydrogen redistribution. In this scenario, hydrogen in IGZO may form a gradual concentration profile extending toward the channel from S/D edges. Such lateral redistribution would reduce the electrically active channel length (L_eff) relative to the nominal designed length (L). Accordingly, we believe that an effective channel length reduction (ΔL = L − L_eff) produced by the net impact of hydrogen redistribution is broadly consistent with the extracted ΔL (≈1.8 μm) from TLM analysis.

3.2. Source-Connected Bottom Gate Structure and Its Effects

As mentioned in Section 3.1, lateral hydrogen diffusion toward the channel during in situ doping can reduce L_eff, which can enhance CLM in short channel devices. This severe CLM degrades the output characteristics and limits the scalability of IGZO TFTs with hydrogen-doped S/D. To suppress this CLM effect in short-channel devices while preserving the benefits of hydrogen doping for low contact resistance and self-alignment, we propose a source-connected bottom gate (SCBG) structure. Figure 4 shows the cross-sectional schematic of the SCBG device. Unlike the conventional top gate structure discussed in Section 2, the SCBG configuration incorporates an additional bottom gate electrode. The bottom gate and source electrodes are connected by a metal interconnection through two via holes, ensuring that both electrodes remain at the source potential during device operation. This architecture is designed to stabilize the channel potential near the drain depletion region by introducing a bottom gate tied to the source potential (V_S = 0 V). Consequently, the pinch-off point shift and the resulting CLM are expected to be suppressed in the proposed structure.

Figure 5 demonstrates the effectiveness of the SCBG structure in suppressing CLM. Figure 5a shows the I_D–V_GS curves of fabricated SCBG devices with channel lengths of 5, 7.5, 10, and 15 μm, measured at V_DS = 1 V. All devices exhibit well-defined transfer characteristics with Vth of approximately 0.66 V. The bottom gate in the SCBG device is tied to the source potential (V_BG = V_S = 0 V). Therefore, the slight positive shift in Vth compared with the conventional structure (−0.19 V in Section 3.1) is not attributed to an intentional bottom gate biasing effect. Instead, it is considered a secondary effect arising from the modified electrostatic boundary condition. More importantly, differences in the IGZO/SiO₂ bottom interface (buffer SiO₂ deposited at 200 °C versus bottom gate insulator deposited at 250 °C) may alter interfacial defect states. These changes in oxygen-vacancy-related and hydroxyl/hydrogen-related defects can shift Vth [21]. Figure 5b shows the I_D–V_DS curves measured at V_GS = 4 V, revealing a clear contrast with the conventional devices (Figure 2b). In the saturation regime, the SCBG devices exhibit nearly flat saturation behavior. For the L = 5 μm device, the output resistance (r_o) was extracted from a linear fit of the I_D–V_DS curve at V_DS = 10–15 V. We used the same procedure as for the conventional devices, yielding r_o = 475 MΩ. The Early voltage (V_A) of the SCBG structure is approximately 1.2 kV, which is approximately 20 times higher than that of the conventional structure. This increase in V_A indicates a substantial suppression of CLM in the SCBG structure. Reproducibility of the transfer and output characteristics is provided in Figure A3 and Figure A4 in Appendix A. Key parameters (Vth, r_o, and V_A for each L) extracted from the measured characteristics are summarized in

Table 1. Summary of key device parameters for the conventional and SCBG IGZO TFTs as a function of channel length (L). Values are reported as mean ± SD (n = 5).

L (μm)	Conventional TFT			SCBG TFT
	Vth (V)	ro (MΩ)	VA (V)	Vth (V)	ro (MΩ)	VA (V)
5	−0.19 ± 0.17	13.5 ± 2.5	56.1 ± 10.4	0.66 ± 0.12	475 ± 52	1159 ± 173
7.5	0.11 ± 0.12	23.3 ± 2.3	56.0 ± 8.5	0.92 ± 0.09	848 ± 83	1275 ± 150
10	0.22 ± 0.11	32.7 ± 2.3	54.1 ± 5.5	1.07 ± 0.13	1329 ± 84	1226 ± 81
15	0.23 ± 0.11	53.6 ± 3.3	55.4 ± 4.5	1.09 ± 0.1	2290 ± 136	1292 ± 86

. Values are reported as mean ± SD (n = 5).

The proposed SCBG structure exhibits an almost V_DS-independent drain current in the saturation regime. This behavior can be attributed to the fact that the bottom gate is electrically tied to the source potential (0 V). Consequently, an increase in V_DS is not expected to significantly perturb the potential distribution in the vicinity of the pinch-off point near the drain. As a result, the drain-bias-induced shift of the pinch-off point is significantly suppressed, which leads to a pronounced improvement in the current saturation characteristics. In addition to the high V_DS comparison, we examined the low V_DS saturation behavior under lower gate biases (V_GS = 1 V and 2 V), for which current saturation occurs at lower V_DS. The corresponding output characteristics confirm that the SCBG device maintains a markedly reduced output slope compared with the conventional device in the saturation regime (Appendix B, Figure A5). To support the suppressed pinch-off point movement with increasing V_DS in the SCBG structure, device simulations were performed. The corresponding results and discussion are presented in the following section.

3.3. Simulation Analysis of Pinch-Off Point Movement

To assess the effectiveness of the SCBG structure in suppressing CLM, two-dimensional (2-D) electrostatic simulations were performed using the Semiconductor Module of COMSOL Multiphysics. Material parameters for IGZO were set to typical values (E_g = 3.05 eV, ε_r = 10). The simulation domain represents a 2-D cross section along the nominal channel length (5 μm) with the S/D length (1 + 1 μm) and thickness (50 nm), matching the geometry of the fabricated devices. The reduction in effective channel length was modeled using the complementary error function (erfc), which can mimic the lateral diffusion of hydrogen. The detailed doping profile in the IGZO channel (1 μm < x < 6 μm) was modeled as

$$N(x)=N_{\mathrm{c}\mathrm{h}}+0.5N_{\mathrm{S}\mathrm{D}}·\mathrm{e}\mathrm{r}\mathrm{f}\mathrm{c}\left({\displaystyle \frac{x-\left(L_{\mathrm{S}\mathrm{D}}+L_{\mathrm{c}\mathrm{h}\mathrm{a}\mathrm{r}}\right)}{L_{\mathrm{c}\mathrm{h}\mathrm{a}\mathrm{r}}}}\right)+0.5N_{\mathrm{S}\mathrm{D}}·\mathrm{e}\mathrm{r}\mathrm{f}\mathrm{c}\left({\displaystyle \frac{(L+L_{\mathrm{S}\mathrm{D}}-L_{\mathrm{c}\mathrm{h}\mathrm{a}\mathrm{r}})-x}{L_{\mathrm{c}\mathrm{h}\mathrm{a}\mathrm{r}}}}\right).$$

(1)

Here, N_ch (=1 × 10¹⁵ cm⁻³) is the background dopant concentration in the channel and N_SD (=1 × 10¹⁹ cm⁻³) is the dopant concentration in the S/D. The nominal channel length is L (=5 μm), and L_SD (=1 μm) is the length of the S/D outside the channel. L_char (=0.28 μm) is a fitting parameter in the erfc-based profile that sets the spatial scale of the dopant concentration tail extending from the S/D edges into the channel. A detailed explanation of this point is provided later.

The primary objective of these simulations was to qualitatively investigate the impact of the gradual doping profile and the effect of the SCBG structure on the CLM. We did not attempt to quantitatively match the measured device characteristics. Therefore, we examined the electron concentration profiles in the IGZO layer rather than I_D–V_DS characteristics. Figure 6 compares 2-D electron concentration maps in the IGZO layer. Figure 6a shows a series of 2-D electron concentration maps of the conventional top gate structure at V_GS = 4 V and V_DS = 0, 2, 4, 6, 8, and 10 V. Figure 6b shows the corresponding maps of the SCBG structure under the same bias conditions. In both cases, the electron concentration in the channel region near the drain begins to decrease noticeably once V_DS exceeds approximately 4 V, forming a drain depletion region. However, a critical difference is observed between the two structures. In the conventional device, the reduction in electron concentration occurs predominantly in the upper portion of the IGZO layer. In the SCBG device, the reduction is concentrated mainly in the lower portion of the IGZO layer. This implies that, for the conventional structure, the depletion-region expansion takes place near the top of the IGZO. The channel is primarily formed under top gate control. As V_DS increases, this promotes movement of the pinch-off point toward the source. In contrast, in the SCBG structure the depletion region expands mostly in the lower IGZO region, which is less directly associated with the top-gate-controlled channel. Consequently, the pinch-off point shift can be relatively smaller. This contrast indirectly indicates that the SCBG configuration suppresses the CLM effect.

To analyze the pinch-off point movement, we defined a horizontal cutline located 5 nm below the gate insulator interface, extending from the source through the channel to the drain. The electron concentration along this cutline was then extracted with V_DS varying from 0 to 10 V in 1 V steps at fixed V_GS = 4 V. Figure 7a shows a series of the electron concentration on the cutline of the conventional structure, while Figure 7b shows the corresponding series of the SCBG structure under the same bias conditions. At V_DS = 0 V, the electron concentration at the channel center is approximately 2 × 10¹⁷ cm⁻³. The effective channel length (L_eff) can be estimated by measuring the distance between two points near the S/D edges where the electron concentration begins to increase. However, because the concentration increases only gradually near the onset, the exact locations of these points are ambiguous. Therefore, we adopt an operational definition that is less sensitive to this ambiguity. We define the two edge points as those where the electron concentration at V_DS = 0 V is 10% higher than the central value (i.e., 2.2 × 10¹⁷ cm⁻³). We confirmed that using nearby substitutions (e.g., 5–15%) do not appreciably change the extracted L_eff. For both device structures, the extracted effective channel length is approximately fitted to 3.2 μm, which is consistent with the L_eff extracted from TLM analysis in Section 3.1. The reason for setting L_char = 0.28 μm (in Equation (1)) is to calibrate the simulated L_eff to the value extracted from the TLM analysis. When L_char = 0.28 μm, the effective channel length could be obtained as 3.2 μm. We denote the effective channel length extracted at V_DS = 0 V using the above definition as L_eff0.

In Figure 7a for the conventional structure, it is observed that a pronounced electron-depleted region forms near the drain and expands once V_DS exceeds ~4–5 V. As V_DS increases further, the electron concentration in this region drops sharply. In Figure 7b for the SCBG structure, it is also observed that an electron-depleted region forms near the drain. However, as V_DS increases, the minimum electron concentration does not decrease to the same level as in the conventional structure, and the rate of reduction is markedly reduced. In addition, the expansion of the depletion region toward the source is substantially slowed.

To facilitate quantitative analysis of the pinch-off point shift, we define the pinch-off point operationally. Specifically, it is the position where the electron concentration drops to 1/20 of the channel center value at V_DS = 0 V (i.e., 2 × 10¹⁶ cm⁻³). This corresponds to a 95% depletion of electrons and avoids reliance on the conventional pinch-off definition. Among the two points that satisfy the defined criteria, the one located closer to the channel is selected. Figure 8a shows the extracted positions of the pinch-off point (x_po) as a function of V_DS ranging from 6 to 10 V for both the conventional and SCBG structures. To assess the variability of the simulation results, we varied a few simulation parameters. We scaled the S/D doping concentration by 1.5 and by 1/1.5. We also varied the gate insulator thickness by +10% and −10%. The resulting spread is shown as error bars in Figure 8. In the case of conventional structure, x_po moves progressively toward the source as V_DS increases, confirming the characteristic behavior of CLM. However, in the case of the SCBG structure, x_po exhibits a markedly reduced shift, in contrast to the conventional case.

Figure 8b illustrates the channel length reduction (ΔL), as a function of V_DS, where ΔL was defined as the distance between the drain-side channel edge and x_po. The slope of the linear regression of ΔL corresponds to d(ΔL)/dV_DS. Linear regression analysis yielded d(ΔL)/dV_DS = 0.027 μm/V for the conventional structure. On the other hand, the SCBG structure showed a considerably smaller d(ΔL)/dV_DS of 0.012 μm/V. This corresponds to a ~55% reduction in d(ΔL)/dV_DS compared with the conventional structure.

A clear difference between the SCBG and conventional structures appears in the degree of pinch-off point shift. This considerable reduction in the pinch-off point shift demonstrates that the SCBG effectively improves current saturation against V_DS variations. The reduced ΔL and d(ΔL)/dV_DS in the SCBG device can be interpreted as an electric field control effect. The source-tied bottom gate (V_BG = V_S = 0 V) redistributes the electric field near the pinch-off region. This weakens the lateral field component that drives pinch-off shift. Supporting 2-D electric field plots and a lateral field component comparison are provided in Appendix C (Figure A6 and Figure A7). These simulation results support that the SCBG structure suppresses CLM in short-channel IGZO TFTs with hydrogen-doped S/D under the assumed lateral doping profile. To address scalability toward submicron operation, we additionally evaluated shorter channels (L = 3.0 and 2.5 μm). For these cases, hydrogen-diffusion-induced effective channel lengths are estimated to be approximately 1.2 and 0.7 μm, respectively. We used the same pinch-off extraction framework as in Figure 8 (V_DS = 6–10 V). The results confirm that the SCBG structure continues to suppress pinch-off shift compared with the conventional structure (Appendix C, Figure A8).

4. Conclusions

This study investigated CLM in top gate IGZO TFTs with self-aligned hydrogen-doped S/D. Conventional devices showed pronounced CLM as the channel length approached 5 μm, with a strong reduction in output resistance and Early voltage. TLM analysis indicated an effective channel length reduction of about 1.8 μm. COMSOL simulations with an assumed gradual doping profile supported drain-bias-induced expansion of the drain side depletion region and a shift of the pinch-off point toward the source.

To mitigate this degradation, we proposed a SCBG structure that adds a bottom gate that is tied to the source potential while maintaining process compatibility with self-aligned hydrogen-doped S/D. Experiments demonstrated markedly improved current saturation for L = 5 μm SCBG devices, with substantially higher output resistance and Early voltage than the conventional structure. Simulations for the SCBG structure also showed a smaller pinch-off point shift than the conventional structure.

These results indicate that the proposed SCBG structure stabilizes the potential near the pinch-off point and screens drain-induced perturbations. The modest threshold voltage shift is a manageable tradeoff for the improved saturation behavior. Overall, the SCBG structure provides a practical device-level strategy for robust short channel IGZO TFTs and is promising for high-resolution AMOLED backplanes. Future work will address bottom gate optimization, long-term stability, and circuit integration.