Nanostructured Electronic Components and Devices

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (31 May 2024) | Viewed by 1313

Special Issue Editor


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Guest Editor
Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung, Taiwan
Interests: resistive random-access memory; dye-sensitized solar cells; thin-film growth; ferroelectric materials; nanophotonics devices

Special Issue Information

Dear Colleagues,

Nanostructured electronic components represent the pinnacle of miniaturization, where the manipulation of matter at the nanoscale bestows electronic devices with unprecedented performance and capabilities. These components, featuring meticulously engineered nanomaterials and architectures, offer a new frontier in electronics, promising advancements that were once considered beyond our reach.

The impact of nanoscale design on electronic components is profound. Nanostructured materials, such as quantum dots, nanowires, and two-dimensional materials, introduce unique properties, enabling faster and more efficient devices. Moreover, their utilization in transistors, sensors, energy storage, etc., opens doors to innovations with far-reaching consequences.

This Special Issue aims to assemble contributions from leading experts and research groups in this field to provide a comprehensive overview of the latest advances on the topic of “Nanostructured Electronic Components and Devices”. From nanoelectronics to nanophotonics, interplay between nanoscience and electronics promises to shape the future of technologies such as solar cells, and this collection of papers will offer invaluable insights into the state-of-the-art developments in this exciting domain.

Prof. Dr. Ming-Cheng Kao
Guest Editor

Manuscript Submission Information

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Keywords

  • nanowires
  • nanoparticles
  • quantum dots
  • nanotransistors
  • nanophotonics devices
  • nanomemory devices
  • nanogenerators
  • nanotubes and nanorods
  • nanoscale sensors

Published Papers (2 papers)

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Research

14 pages, 5077 KiB  
Article
Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors
by Jinsu Jeong, Sanguk Lee and Rock-Hyun Baek
Nanomaterials 2024, 14(12), 1006; https://doi.org/10.3390/nano14121006 - 10 Jun 2024
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Abstract
The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s [...] Read more.
The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs. Full article
(This article belongs to the Special Issue Nanostructured Electronic Components and Devices)
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9 pages, 2172 KiB  
Communication
Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors
by Jaemin Son, Juhee Jeon, Kyoungah Cho and Sangsig Kim
Nanomaterials 2024, 14(7), 562; https://doi.org/10.3390/nano14070562 - 23 Mar 2024
Viewed by 725
Abstract
In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator [...] Read more.
In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.6% for logic 0 and 48.4% for logic 1. The generation of analog voltages provides binary random variables that are stored for over 5000 s. This demonstrates the potential of the ring oscillator in advanced physical functions and true random number generator technologies. Full article
(This article belongs to the Special Issue Nanostructured Electronic Components and Devices)
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