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Micromachines
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Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition
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Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: 25 April 2027 | Viewed by 7621

Editors

Dr. Liangxing Hu

E-Mail Website
Guest Editor
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
Interests: micromachining; nanofabrication; 3D integration; CMOS-MEMS stacking; advanced packaging
Special Issues, Collections and Topics in MDPI journals
Dr. Peng Zhao

E-Mail Website
Guest Editor
Imec, Kapeldreef 75, 3001 Leuven, Belgium
Interests: nano TSV; backside power delivery network; middle of line; hybrid bonding; fusion bonding
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

With the rapid development trend of microelectronics technology, the optimization of microsystems and their different electronic components, in recent years, have moved towards small form factors, high bandwidths, high frequencies, high performance, high reliability, low power consumption, and low cost. Packaging materials and bonding technologies are especially vital parts of this trend since they have essential roles in back-end processes. The further these processes develop, the more advanced packaging materials and bonding technologies are needed. To meet the rising need for advanced systems development and to address the emerging challenges and issues facing the assembly and packaging of microelectronics, various packaging materials and technologies (2D, 2.5D, 3D, wafer-level packaging, and other advanced packaging technologies) are being developed across industry and academia. The good news is that the demand around these is rapidly increasing.

This Special Issue addresses research on microelectronics assembly and packaging, including bonding technologies (glass frit bonding, eutectic bonding, transient liquid-phase diffusion bonding, adhesive bonding, fusion bonding, thermocompression bonding, hybrid bonding), 2D/2.5D/3D integration and packaging, heterogeneous integration, and chiplet interconnections. Additionally, we welcome articles and reviews on electronic packaging materials such as metals, alloys, ceramics, and semiconductor materials, as well as their characterization and qualification.

Dr. Liangxing Hu
Dr. Peng Zhao
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-anonymized peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • semiconductor packaging
  • advanced pakaging
  • chip and wire bonding technology
  • mixed-assembly technology
  • multichip modules (MCM)
  • package-on-package (PoP)
  • system-in-package (SiP)
  • heterogeneous integration
  • chiplet interconnection
  • hybrid bonding
  • 2.5D (interposer)
  • 3D (TSV/TGV)
  • packaging materials
  • materials qualification

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Related Special Issue

Published Papers (6 papers)

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Research

32 pages, 27884 KB  
Article
An Efficient Numerical Homogenization Method for Multi-Scale Modeling of 2.5D Package Warpage and Thermal Analysis
by Pengying Xu, Shaoyi Liu, Lu Hao, Jitang Zhang, Yan Wang, Qiulin Tan and Congsi Wang
Micromachines 2026, 17(7), 853; https://doi.org/10.3390/mi17070853 - 17 Jul 2026
Viewed by 460
Abstract
To achieve high interconnect density in 2.5D packages, various microscale structures such as through-silicon vias (TSVs), microbumps, and redistribution layers (RDLs) are employed. These features typically exist at the micron scale, whereas other package components span millimeter to centimeter scales, resulting in a [...] Read more.
To achieve high interconnect density in 2.5D packages, various microscale structures such as through-silicon vias (TSVs), microbumps, and redistribution layers (RDLs) are employed. These features typically exist at the micron scale, whereas other package components span millimeter to centimeter scales, resulting in a wide range of physical dimensions within the package. Although finite element analysis (FEA) has proven effective for evaluating the mechanical and thermal characteristics of 2.5D packages, the inherent multi-scale nature poses significant computational challenges and numerical convergence issues, severely hindering the design and analysis of increasingly dense packages. To address this problem, this paper proposes an efficient numerical homogenization method for the mechanical and thermal analysis of 2.5D packages. The method employs periodic boundary conditions (PBCs) based on the concept of referential statistical volume elements (rSVEs). In this approach, typical microstructures—including TSVs, microbumps, and RDL traces together with the surrounding matrix material—are treated as a homogeneous medium, and the equivalent material properties of the multi-scale structures are evaluated. These properties include the stiffness matrices (from which the equivalent Young’s modulus, shear modulus, and Poisson’s ratio can be derived), coefficients of thermal expansion, and thermal conductivity. Validation results demonstrate that the proposed method ensures continuity of displacement, stress, strain, and heat flux across opposite surface pairs of the rSVEs. Compared with experimental measurements and other existing homogenization techniques, the method accurately determines the equivalent material properties of complex multi-scale structures without being restricted to specific geometries, while significantly improving computational efficiency. Finally, the proposed numerical homogenization method is successfully applied to wafer warpage analysis during the manufacturing process and to thermal analysis under operating conditions. The results indicate that the method achieves high computational efficiency while maintaining accuracy in both mechanical and thermal analyses of 2.5D packages, thereby laying a solid foundation for the development of next-generation 2.5D package structures. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition)
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13 pages, 3824 KB  
Article
A Simulation Study of a Bandpass Filter Formed by CNT-Core Cu-TSVs with Enhanced Thermal Management
by Han Wang, Yingtao Ding, Ziyue Zhang, Jiaxuan Zhang, Anda Zhang, Xiang Pei and Zhiming Chen
Micromachines 2026, 17(6), 724; https://doi.org/10.3390/mi17060724 - 15 Jun 2026
Viewed by 373
Abstract
Bandpass filters based on through-silicon-via (TSV) interposers offer advantages such as compact footprint, excellent radio frequency (RF) performance, simplified processing, and low cost. However, as power densities in three-dimensional (3D) integrated circuits continue to rise, thermal management has become a critical performance bottleneck. [...] Read more.
Bandpass filters based on through-silicon-via (TSV) interposers offer advantages such as compact footprint, excellent radio frequency (RF) performance, simplified processing, and low cost. However, as power densities in three-dimensional (3D) integrated circuits continue to rise, thermal management has become a critical performance bottleneck. In this work, we present a TSV-based bandpass filter design where the TSVs feature annular Cu conductors with carbon nanotube (CNT) cores. The annular Cu structure provides the required vertical electrical connectivity, while the high-thermal-conductivity CNT core facilitates inter-layer heat dissipation. RF simulations confirm that the RF characteristics of the filter remain comparable to those of filters based on conventional TSVs with Cu-pillar conductors or TSVs with annular Cu conductors and polymer cores such as benzocyclobutene (BCB). In addition, multiphysics simulations demonstrate that the proposed filter exhibits a maximum steady-state temperature of only 89.1 °C with a 5 W constant heat source attached to the interposer surface and a heat sink at the bottom side, presenting an efficient reduction compared to the other two types. The filter also shows reduced thermally induced surface deformation, confirming the thermal benefits of the CNT cores. Furthermore, comprehensive parametric analyses involving the influences of critical TSV structural parameters on the TSV-based capacitors and inductors are performed, providing guidelines for customized filter design. We believe the proposed design highlights a promising pathway for addressing the thermal management challenges in high-density RF integrated microsystems. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition)
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12 pages, 5935 KB  
Article
Porous Au/Ti Bilayer Thin-Film Getters Based on Black Silicon for MEMS Vacuum Packaging
by Kunwei Zhao, Tianyou Chen, Yuelong Liu and Ji Fan
Micromachines 2026, 17(5), 520; https://doi.org/10.3390/mi17050520 - 24 Apr 2026
Viewed by 1292
Abstract
Porous thin-film getters are extensively utilized in the field of MEMS vacuum packaging. Nevertheless, their effectiveness is frequently constrained by the comparatively modest effective surface area of conventional planar structures. In this work, a porous Au/Ti thin-film getter based on a three-dimensional black [...] Read more.
Porous thin-film getters are extensively utilized in the field of MEMS vacuum packaging. Nevertheless, their effectiveness is frequently constrained by the comparatively modest effective surface area of conventional planar structures. In this work, a porous Au/Ti thin-film getter based on a three-dimensional black silicon scaffold is developed to enhance the effective surface area and improve gettering performance. The fabrication of black silicon nanostructures is achieved through an SF6/O2-based inductively coupled plasma (ICP) etching process, followed by the deposition of Au/Ti bilayer films by DC magnetron sputtering. The morphological evolution of the Ti film on the nanostructured substrate and the activation behavior of the Au/Ti bilayer are systematically investigated using scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). The results demonstrate that the shadowing effect during sputtering leads to the formation of a porous film with increased surface roughness and an open structure. XPS analysis demonstrates that there is a significant increase in the oxygen content on the surface at higher activation temperatures. This suggests that effective sorption capability is achieved following activation. In comparison with planar substrates, the three-dimensional black silicon scaffold has been demonstrated to promote the formation of a more open and functional structure. The results obtained from this study indicate that the proposed fabrication strategy offers a feasible and MEMS-compatible approach for the construction of porous thin-film getters, thereby enhancing their effective surface area. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition)
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28 pages, 27017 KB  
Article
Electro-Thermal Co-Design and Verification of TGV Transmission Structures for High-Power High-Frequency Applications
by Luming Chen, Zhilin Wei, Shenglin Ma, Yan Chen, Yihan Xie, Chunlei Li, Shuwei He and Hai Yuan
Micromachines 2026, 17(2), 253; https://doi.org/10.3390/mi17020253 - 16 Feb 2026
Cited by 4 | Viewed by 1263
Abstract
Through Glass Via (TGV) technology has emerged as a promising solution for advanced packaging. While glass offers lower dielectric loss than silicon, its lower thermal conductivity raises concerns about electro-thermal coupling effects in high-power, high-frequency applications. Therefore, this study conducted an electro-thermal co-design [...] Read more.
Through Glass Via (TGV) technology has emerged as a promising solution for advanced packaging. While glass offers lower dielectric loss than silicon, its lower thermal conductivity raises concerns about electro-thermal coupling effects in high-power, high-frequency applications. Therefore, this study conducted an electro-thermal co-design of TGV grounded Coplanar Waveguide (CPW) and Radio Frequency (RF) TGV connected CPW structures. A high-power test platform was developed to investigate the electrical and thermal performance of these structures. The temperature distribution mechanism under high-power conditions was revealed. Under high power and high frequency, the decrease in surface conductivity affected by surface state and film layer composition leads to increased loss, triggering temperature rise and forming an electrothermal coupling loop. Under continuous wave operation (5–20 W), the temperature rise reaches 92.4 °C while insertion loss increases by only 0.4 dB. Under pulsed wave operation (25–100 W, 2.5% duty cycle), the temperature rise is merely 2.1 °C with insertion loss increasing by 0.3 dB. The quadruple-redundant design and reduces heat flux density, preventing localized hotspot formation. The pulse intervals suppress thermal accumulation, leading to lower temperature rise. Therefore, continuous wave applications should prioritize thermal management, while pulsed wave applications can focus on electrical performance optimization. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition)
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22 pages, 6477 KB  
Article
An End-to-End Design and Simulation Methodology for Evaluating Package-Induced Signal Integrity Degradation in PCIe Channels
by Siwook Park, Uichan Kim, Jonghyun Lee, Jiwoon Moon, Yuchul Jung and Youngwoo Kim
Micromachines 2026, 17(2), 218; https://doi.org/10.3390/mi17020218 - 6 Feb 2026
Cited by 1 | Viewed by 1200
Abstract
This paper presents an end-to-end simulation methodology for evaluating package-induced signal integrity (SI) degradation in a peripheral component interconnect express (PCIe) 5.0 channel. By integrating package, printed circuit board (PCB), and add-in card (AIC) structures into a unified simulation flow, the proposed approach [...] Read more.
This paper presents an end-to-end simulation methodology for evaluating package-induced signal integrity (SI) degradation in a peripheral component interconnect express (PCIe) 5.0 channel. By integrating package, printed circuit board (PCB), and add-in card (AIC) structures into a unified simulation flow, the proposed approach enables accurate assessment of system-level eye diagram degradation. Various package-level degradation factors, such as impedance mismatch, meander routing, and via stubs, are assumed and designed to analyze their individual and combined effects on insertion loss, intra-pair skew, and eye diagrams. Results show that even localized discontinuities inside the package propagate and compound through the end-to-end channel, causing a significant reduction in the eye diagram at the system level. These findings demonstrate that package-induced impairments cannot be evaluated solely at the package level but must instead be analyzed within a complete end-to-end channel environment. The proposed methodology provides a practical framework for predicting system-level SI degradation caused by package design choices, offering valuable insights for next-generation high-speed package and channel co-design. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition)
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18 pages, 2870 KB  
Article
Research on the Parasitic Inductance of the Bonding Wires in IGBT Modules Based on Their Morphology and Layout
by Junwei Cao, Sheng Wu, Yanhui Wang, Chongyang Xu, Xiaotong Wang, Weibin Jiang, Yingchun Wang and Yuan Wang
Micromachines 2026, 17(1), 26; https://doi.org/10.3390/mi17010026 - 25 Dec 2025
Cited by 1 | Viewed by 836
Abstract
As a typical electronic switching device, IGBT is widely used in various fields. Reducing the parasitic inductance parameters of IGBT is of great significance for improving the performance of power devices, enhancing system stability and reliability. To study the parasitic inductance of the [...] Read more.
As a typical electronic switching device, IGBT is widely used in various fields. Reducing the parasitic inductance parameters of IGBT is of great significance for improving the performance of power devices, enhancing system stability and reliability. To study the parasitic inductance of the internal bonding wire connection structure during the operation of IGBT modules, this paper considers the morphological modeling of bonding wires, bonding parameters, and the layout of bonding wire arrays, and proposes a new analysis model. Through mathematical calculation of the analysis model and Ansys Q3D simulation, the bonding wires with different geometric dimensions and layouts were studied and good correlation were obtained. This will reduce the impact of bonding parameters on the total parasitic inductance of the bonding wire during the pre-layout stage. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 3rd Edition)
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