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Micromachines
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Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition
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Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D：Materials and Processing".

Deadline for manuscript submissions: 20 August 2025 | Viewed by 4881

Special Issue Editors

Dr. Liangxing Hu

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Guest Editor
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
Interests: micromachining; nanofabrication; 3D integration; CMOS-MEMS stacking; advanced packaging
Special Issues, Collections and Topics in MDPI journals
Dr. Youngwoo Kim

E-Mail Website
Guest Editor
Department of Semiconductor System Engineering, Sejong University, Seoul 05006, Republic of Korea
Interests: advanced package design/development; signal and power integrity; EMI/EMC in digital systems; hardware security
Dr. Peng Zhao

E-Mail Website
Guest Editor
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Interests: nano TSV; backside power delivery network; middle of line; hybrid bonding; fusion bonding

Special Issue Information

Dear Colleagues,

With the rapid development trend of microelectronics technology, the optimization of microsystems and their different electronic components in recent years has moved towards small form factors, high bandwidths, high frequencies, high performance, high reliability, low power consumption, and low cost. Packaging materials and bonding technologies are especially vital parts of this trend since they have essential roles in back-end processes. The further these processes develop, the more advanced packaging materials and bonding technologies are needed. To meet the rising need for advanced systems development and to address the emerging challenges and issues facing the assembly and packaging of microelectronics, various packaging materials and technologies (2D, 2.5D, 3D, wafer-level packaging, and other advanced packaging technologies) are being developed across industry and academia. The good news is that the demand around these is rapidly increasing.

This Special Issue addresses research on microelectronics assembly and packaging, including bonding technologies (glass frit bonding, eutectic bonding, transient liquid-phase diffusion bonding, adhesive bonding, fusion bonding, thermocompression bonding, hybrid bonding), 2D/2.5D/3D integration and packaging, heterogeneous integration, and chiplet interconnections. Additionally, we welcome articles and reviews on electronic packaging materials such as metals, alloys, ceramics, and semiconductor materials, as well as their characterization and qualification.

Dr. Liangxing Hu
Dr. Youngwoo Kim
Dr. Peng Zhao
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • semiconductor packaging
  • advanced packaging
  • chip and wire bonding technology
  • mixed-assembly technology
  • multichip modules (MCM)
  • package-on-package (PoP)
  • system-in-package (SiP)
  • heterogeneous integration
  • chiplet interconnection
  • hybrid bonding
  • 2.5D (interposer)
  • 3D (TSV/TGV)
  • packaging materials
  • materials qualification

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Related Special Issue

Published Papers (7 papers)

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Research

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12 pages, 2838 KiB  
Article
Glass Microbubble Encapsulation for Improving the Lifetime of a Ferrofluid-Based Magnetometer
by Chenchen Zhang and Srinivas Tadigadapa
Micromachines 2025, 16(5), 519; https://doi.org/10.3390/mi16050519 (registering DOI) - 28 Apr 2025
Viewed by 89
Abstract
In this paper, we explore the use of chip-scale blown glass microbubble structures for MEMS packaging applications. Specifically, we demonstrate the efficacy of this method of packaging for the improvement of the lifetime of a ferrofluid-based magnetoviscous magnetometer. We have previously reported on [...] Read more.
In this paper, we explore the use of chip-scale blown glass microbubble structures for MEMS packaging applications. Specifically, we demonstrate the efficacy of this method of packaging for the improvement of the lifetime of a ferrofluid-based magnetoviscous magnetometer. We have previously reported on the novel concept of a ferrofluid based magnetometer in which the viscoelastic response of a ferrofluid interfacial layer on a high frequency shear wave quartz resonator is sensitively monitored as a function of applied magnetic field. The quantification of the magnetic field is accomplished by monitoring the at-resonance admittance characteristics of the ferrofluid-loaded resonator. While the proof-of-concept measurements of the device have been successfully made, under open conditions, the evaporation of the carrier fluid of the ferrofluid continuously changes its viscoelastic properties and compromises the longevity of the magnetometer. To prevent the evaporation of the ferrofluid, here, we seal the ferrofluid on top of the micromachined quartz resonator within a blown glass hemispherical microbubble attached to it using epoxy. The magnetometer design used a bowtie-shaped thin film Metglas (Fe85B5Si10) magnetic flux concentrator on the resonator chip. A four-times smaller noise equivalent, a magnetic field of 600 nT/√Hz at 0.5 Hz was obtained for the magnetometer using the Metglas flux concentrator. The ferrofluid-based magnetometer is capable of sensing magnetic fields up to a modulation frequency of 40 Hz. Compared with the unsealed ferrofluid device, the lifetime of the glass microbubble integrated chip packaged device improved significantly from only a few hours to over 50 days and continued. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition)
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15 pages, 10184 KiB  
Article
An Overview of Substrate Copper Trace Crack Through Experiments, Characterization, and Numerical Simulations
by Wei Yu, Faxing Che, Vance Liu, Raymond Chen, Sam Ireland, Yeow Chon Ong, Hong Wan Ng and Gokul Kumar
Micromachines 2025, 16(4), 428; https://doi.org/10.3390/mi16040428 - 2 Apr 2025
Viewed by 294
Abstract
The high input/output demands of memory packages require precise trace width and spacing, posing challenges for contemporary package design. Substrate copper trace cracks are a major reliability issue during temperature cycling tests (TCTs). This study offers a detailed analysis of copper trace crack [...] Read more.
The high input/output demands of memory packages require precise trace width and spacing, posing challenges for contemporary package design. Substrate copper trace cracks are a major reliability issue during temperature cycling tests (TCTs). This study offers a detailed analysis of copper trace crack mechanisms through experimental observations, material characterization, and numerical simulations. Common failure modes of trace cracks are identified from experimental data, pinpointing initiation sites and propagation paths. Young’s modulus of copper foil samples is assessed using four testing methods, revealing consistent trends across samples from different substrate suppliers. Sample A with higher E/H values tested via nanoindentation correlated with lower failure rates in the experiment. Stress–strain testing on copper foil was successfully performed at the lower TCT temperature limit of −65 °C, providing vital input for finite element (FE) models. The simulations show strong alignment with trace crack locations under different failure modes. The impact of copper trace width and material properties is illustrated in numerical models by comparing variations in plastic strain responses, which show differences of up to 40% and 30%, respectively. The simulation design of the experiments (DOE) indicates that high-strength solder resist (SR) can significantly enhance temperature cycling performance by reducing SR and copper trace stress and strain by up to 75%. The accumulation of plastic strain in copper traces is predicted to increase up to four times when SR breaks at the crack location, underscoring the importance of SR in copper trace reliability. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition)
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21 pages, 16369 KiB  
Article
Application Characteristics of Ultra-Fine 15 μm Stainless Steel Wires: Microstructures, Electrical Fatigue, and Ball Formation Mechanisms
by Hsiang-Chi Yang, Fei-Yi Hung, Bo-Ding Wu and Yi-Tze Chang
Micromachines 2025, 16(3), 326; https://doi.org/10.3390/mi16030326 - 12 Mar 2025
Viewed by 396
Abstract
Stainless steel wires exhibit excellent mechanical properties and are widely used in engineering applications. This study fabricates 15 μm stainless steel wires for potential integration into wire bonding technology for electronic packaging. The research explores the microstructural characteristics, electrical conduction mechanisms, and ball [...] Read more.
Stainless steel wires exhibit excellent mechanical properties and are widely used in engineering applications. This study fabricates 15 μm stainless steel wires for potential integration into wire bonding technology for electronic packaging. The research explores the microstructural characteristics, electrical conduction mechanisms, and ball formation behavior of ultra-fine stainless-steel wires to assess their feasibility for wire bonding applications. Results indicate that both 15 μm and 30 μm stainless steel wires exhibit elongated grains with outstanding tensile strength and hardness. Compared to the 30 μm wires, the 15 μm wires undergo more pronounced work hardening, leading to higher tensile strength and resistance. This study investigates the differences between vacuum and electrified annealing processes to address the work hardening and ductility issues in stainless steel wires. Results confirm that the hardness of the original wire significantly decreases after vacuum annealing at 780 °C for 15 min. Furthermore, using the derived equation, T=IV2.3085×10−3+25, the annealing temperature of 780 °C is converted into an equivalent current, and electrify annealing is conducted under a condition of 0.08 A for 15 min. The annealed wires exhibit a softening effect and enhance ductility. Furthermore, due to stored deformation energy and recrystallization effects, the electrical fatigue life of 15 μm stainless steel wires is approximately 300 cycles. After electrifying annealing, the base microstructure becomes more homogeneous due to thermal effects, reducing fatigue life to around 150 cycles. However, due to the softening effect, the annealed wires make the EFO process easier and minimize solidification segregation in the free air ball (FAB) microstructure, demonstrating their potential for electronic packaging applications. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition)
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17 pages, 23179 KiB  
Article
Impact of Bonding Pressure on the Reactive Bonding of LTCC Substrates
by Erik Wiss, Nesrine Jaziri, Jens Müller and Steffen Wiese
Micromachines 2025, 16(3), 321; https://doi.org/10.3390/mi16030321 - 11 Mar 2025
Viewed by 460
Abstract
Reactive bonding can overcome the issues associated with conventional soldering processes, such as potential damage to heat-sensitive components and the creation of thermomechanical stress due to differing coefficients of thermal expansion. The risk of such damage can be reduced by using localized heat [...] Read more.
Reactive bonding can overcome the issues associated with conventional soldering processes, such as potential damage to heat-sensitive components and the creation of thermomechanical stress due to differing coefficients of thermal expansion. The risk of such damage can be reduced by using localized heat sources like reactive multilayer systems (RMS), which is already a well-established option in the field of silicon or metal bonding. Adapting this process to other materials, such as low temperature co-fired ceramics (LTCC), is difficult due to their differing properties, but it would open new technological possibilities. One aspect that significantly affects the quality of the bonding joints is the pressure applied during the bonding process. To investigate its influence more closely, various LTCC samples were manufactured, and cross-sections were prepared. The microscopical analysis reveals that there is an optimum range for the bonding pressure. While too little pressure results in the formation of lots of voids and gaps, most likely in poor mechanical and electrical properties, too high pressure seems to cause a detachment of the metallization from the base material. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition)
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17 pages, 7273 KiB  
Article
Measurement and Analysis of Interconnects’ Resonance and Signal/Power Integrity Degradation in Glass Packages
by Youngwoo Kim
Micromachines 2025, 16(1), 112; https://doi.org/10.3390/mi16010112 - 20 Jan 2025
Viewed by 866
Abstract
In this article, resonance phenomena of high-speed interconnects and power delivery networks in glass packages are measured and analyzed. The resonances are generated in the interconnection by the physical dimension, cancelation of reactance components, and modes. When the resonances are generated in the [...] Read more.
In this article, resonance phenomena of high-speed interconnects and power delivery networks in glass packages are measured and analyzed. The resonances are generated in the interconnection by the physical dimension, cancelation of reactance components, and modes. When the resonances are generated in the operation frequency band, the signal/power integrity of the interconnect can be affected. As such, resonances generated in high-speed interconnects increase insertion loss, which degrades signal integrity. Also, resonances of the power delivery network (PDN) associated with boundary conditions increase PDN impedance, which degrades power integrity by generating power/ground noise and return current discontinuity of through vias. Recently, glass packaging has been gaining more attention due to its advantages associated with low substrate loss and large dimensions compared to silicon wafers. However, the low loss of the substrate and process variation may affect the resonance properties of interconnects. The resonance impacts on signal/power integrity must be analyzed, and mitigation plans should be proposed to maximize the advantages of the glass packaging technology. To analyze the resonance impacts on signal/power integrity, various glass package test vehicles are designed and fabricated. The fabricated test vehicles include transmission lines, PDNs, and patterns to measure an interaction between the through via and PDN. First, transmission line patterns that have 50-ohm characteristic impedance are measured. Due to the process variations, quarter-wave resonances are monitored, and at those frequencies, a sharp increase in insertion loss is observed, which deteriorates the signal integrity of the interconnect. Various PDN patterns are measured in the frequency domain, and regardless of the PDN shape, PDN impedance peaks are observed at the mode resonance frequencies. Due to a low-loss characteristic of the glass substrate, sharp PDN impedance peaks are generated at these frequencies. Also, at these frequencies, both signal and power integrity degradations are measured and analyzed. To fully benefit from the advantages of glass packaging technology, a thorough electrical performance analysis should be conducted to avoid resonances in the target frequency range. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition)
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19 pages, 11328 KiB  
Article
Assessment of the Risk of Crack Formation at a Hybrid Bonding Interface Using Numerical Analysis
by Xuan-Bach Le and Sung-Hoon Choa
Micromachines 2024, 15(11), 1332; https://doi.org/10.3390/mi15111332 - 30 Oct 2024
Cited by 1 | Viewed by 1989
Abstract
Hybrid bonding technology has recently emerged as a promising solution for advanced semiconductor packaging technologies. However, several reliability issues still pose challenges for commercialization. In this study, we investigated the possibility of crack formation caused by chemical mechanical polishing (CMP) defects and the [...] Read more.
Hybrid bonding technology has recently emerged as a promising solution for advanced semiconductor packaging technologies. However, several reliability issues still pose challenges for commercialization. In this study, we investigated the possibility of crack formation caused by chemical mechanical polishing (CMP) defects and the misalignment of the hybrid bonding structure. Crack formation and thermomechanical stress were analyzed for two common hybrid bonding structures with misalignment using a numerical simulation. The effects of annealing temperature and dishing value on changes in the non-bonding area and peeling stress were systematically analyzed. The calculated peeling stresses were compared to the bonding strength of each bonding interface to find vulnerable regions prone to cracking. The non-bonding area in the bonding structure increased with a decreasing annealing temperature and an increasing dishing value. To achieve a sufficient bonding area of more than 90%, the annealing temperature should be greater than 200 °C. During the heating period of the annealing process, the SiCN-to-SiCN bonding interface was the most vulnerable cracking site with the highest peeling stress. An annealing temperature of 350 °C carries a significant risk of cracking. On the other hand, an annealing temperature lower than 250 °C will minimize the chance of cracking. The SiCN-to-SiO2 bonding interface, which has the lowest adhesion energy and a large coefficient of thermal expansion (CTE) mismatch, was expected to be another possible cracking site. During cooling, the SiCN-to-Cu bonding interface was the most vulnerable site with the highest stress. However, the simulated peeling stresses were lower than the adhesion strength of the bonded interface, indicating that the chance of cracking during the cooling process was very low. This study provides insights into minimizing the non-bonding area and preventing crack formation, thereby enhancing the reliability of hybrid bonding structures. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition)
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13 pages, 5333 KiB  
Perspective
Interposer-Based ESD Protection: A Potential Solution for μ-Packaging Reliability of 3D Chips
by Xunyu Li, Zijin Pan, Weiquan Hao, Runyu Miao, Zijian Yue and Albert Wang
Micromachines 2025, 16(4), 488; https://doi.org/10.3390/mi16040488 - 21 Apr 2025
Viewed by 211
Abstract
The ending of Moore’s Law calls for innovations in integrated circuit (IC) technologies and chip designs. Heterogeneous integration (HI) emerges as a pathway towards smart future chips for more Moore time and for beyond-Moore time, featuring systems-on-integrated-chiplets (SoICs) and advanced micro-packaging (μ-packaging). Reliability, [...] Read more.
The ending of Moore’s Law calls for innovations in integrated circuit (IC) technologies and chip designs. Heterogeneous integration (HI) emerges as a pathway towards smart future chips for more Moore time and for beyond-Moore time, featuring systems-on-integrated-chiplets (SoICs) and advanced micro-packaging (μ-packaging). Reliability, particularly with regard to electrostatic charge (ESD) failure, is a major challenge for 3D SoIC chips in μ-packaging, which is an emerging design-for-reliability challenge for future chips. This perspective article articulates that interposer-based ESD protection will be an important potential solution for 3D SoIC chips in μ-packaging against the devastating ESD failure problem. Full article
(This article belongs to the Special Issue Microelectronics Assembly and Packaging: Materials and Technologies, 2nd Edition)
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