Special Issue "Selected Papers from SubVt 2012 Conference"
A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).
Deadline for manuscript submissions: closed (1 February 2013)
Prof. David Bol
ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Phone: +32 10472539
Fax: +32 10472598
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
Dr. Steven A. Vitale
Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108, USA
Phone: +1 781 981 2646
Fax: 1 781 981 7889
Ultra-low-voltage circuits operating in the near- or sub-threshold region offer invaluable power savings for ultra-low-power applications. However, designers face significant challenges fighting against magnified sensitivity to process and temperature variations, low drain currents, high gate delay and higher proportion of leakage currents. This issue of JLPEA is the second special issue dedicated to selected papers from the Subthreshold Microelectronics Conference (SubVt 2012) held in Waltham, MA, on 9-10 October 2012. Extended versions of outstanding papers presented at SubVt 2012 are solicited for submission to this special issue but other works related to ultra-low-power microelectronics will also be considered.
Prof. David Bol
Dr. Steven A. Vitale
Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. Papers will be published continuously (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.
Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are refereed through a peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed Open Access quarterly journal published by MDPI.
Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 300 CHF (Swiss Francs). English correction and/or formatting fees of 250 CHF (Swiss Francs) will be charged in certain cases for those articles accepted for publication that require extensive additional formatting and/or English corrections.
Upon publication in JLPEA, authors are requested to acquire reprint permissions for the IEEE copyrighted materials they want use without significant modifications. If less than 50% of each paper is reused and the papers are sufficiently revised, permissions will be granted to the authors as long as the following requirements are fulfilled:
- Senior author's approval of the revisions is obtained, that the following IEEE credit/copyright notice appears prominently on the first page of the reprinted material, with the appropriate details filled in:
Based on "(full paper title)", by (authors' names) which appeared in (complete publication information). © [Year] IEEE.
- A new title is used for the new paper (extended version of the IEEE conference paper), to indicate that the paper has been substantially revised.
Research and review papers on subthreshold microelectronics are solicited in areas including, but not limited to:
- ultra-low voltage logic circuits and techniques
- memory design and technologies
- unattended remote sensors
- memory technologies
- radiation effects
- implantable and handheld biomedical devices
- transistor variability and mitigation
- energy harvesting techniques
- ultra-low-power computation
- asynchronous circuits
- analog and RF technologies and circuits
- device and fabrication technology
J. Low Power Electron. Appl. 2013, 3(3), 250-266; doi:10.3390/jlpea3030250
Received: 6 January 2013; in revised form: 5 July 2013 / Accepted: 9 July 2013 / Published: 29 July 2013| Download PDF Full-text (492 KB) | View HTML Full-text | Download XML Full-text
J. Low Power Electron. Appl. 2013, 3(3), 233-249; doi:10.3390/jlpea3030233
Received: 4 February 2013; in revised form: 29 May 2013 / Accepted: 25 June 2013 / Published: 15 July 2013| Download PDF Full-text (453 KB) | View HTML Full-text | Download XML Full-text
Review: A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications
J. Low Power Electron. Appl. 2013, 3(3), 215-232; doi:10.3390/jlpea3030215
Received: 18 March 2013; in revised form: 1 June 2013 / Accepted: 5 June 2013 / Published: 24 June 2013| Download PDF Full-text (740 KB) | View HTML Full-text | Download XML Full-text
J. Low Power Electron. Appl. 2013, 3(2), 194-214; doi:10.3390/jlpea3020194
Received: 13 March 2013; in revised form: 7 May 2013 / Accepted: 24 May 2013 / Published: 18 June 2013| Download PDF Full-text (476 KB) | View HTML Full-text | Download XML Full-text
J. Low Power Electron. Appl. 2013, 3(2), 174-193; doi:10.3390/jlpea3020174
Received: 4 February 2013; in revised form: 4 April 2013 / Accepted: 25 April 2013 / Published: 24 May 2013| Download PDF Full-text (7644 KB)
J. Low Power Electron. Appl. 2013, 3(2), 159-173; doi:10.3390/jlpea3020159
Received: 13 February 2013; in revised form: 8 April 2013 / Accepted: 25 April 2013 / Published: 24 May 2013| Download PDF Full-text (845 KB) | View HTML Full-text | Download XML Full-text
J. Low Power Electron. Appl. 2013, 3(2), 73-98; doi:10.3390/jlpea3020073
Received: 6 February 2013; in revised form: 7 April 2013 / Accepted: 19 April 2013 / Published: 21 May 2013| Download PDF Full-text (1436 KB)
Article: Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling
J. Low Power Electron. Appl. 2013, 3(2), 54-72; doi:10.3390/jlpea3020054
Received: 4 February 2013; in revised form: 16 March 2013 / Accepted: 19 March 2013 / Published: 29 April 2013| Download PDF Full-text (3640 KB)
Last update: 8 October 2012