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A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications

The Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA
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J. Low Power Electron. Appl. 2013, 3(3), 215-232; https://doi.org/10.3390/jlpea3030215
Received: 18 March 2013 / Revised: 1 June 2013 / Accepted: 5 June 2013 / Published: 24 June 2013
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and power management strategies cannot be correctly established without accounting for the associated overhead related to the DC-DC converters that provide regulated power to the system. The proposed model accurately predicts the efficiency of inductor based DC-DC converters with varying topologies and control schemes across a range of output voltage and current loads. It also accounts for the energy and timing overhead associated with the change in the operating condition of the regulator. Since modern SoCs employ power management techniques that vary the voltage and current loads seen by the converter, accurate modeling of the impact on the converter efficiency becomes critical. We use this model to compute the overall cost of two power distribution strategies for a SoC with multiple voltage islands. The proposed model helps us to obtain the energy benefits of a power management technique and can also be used as a basis for comparison between power management techniques or as a tool for design space exploration early in a SoC design cycle. View Full-Text
Keywords: power management; modeling; DC-DC converter; DVS; DVFS; Ultra low power SoC; efficiency power management; modeling; DC-DC converter; DVS; DVFS; Ultra low power SoC; efficiency
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Shrivastava, A.; Calhoun, B.H. A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications. J. Low Power Electron. Appl. 2013, 3, 215-232.

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