Special Issue "Selected Papers from IEEE S3S Conference 2016"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 February 2017)

Special Issue Editors

Guest Editor
Prof. Dr. David Bol

ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Website | E-Mail
Phone: +3210472539
Fax: +32 10472598
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
Guest Editor
Dr. Steven A. Vitale

Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108, USA
E-Mail
Fax: 1 781 981 7889

Special Issue Information

Dear Colleagues,

For more than two decades, low-power consumption has been paramount for integrated circuits (ICs) and systems-on-a-chip (SoCs). In today’s sub-100 nm technologies, low-power design flows are maturing with techniques, such as clock/power gating, multi-Vt/Vdd assignment, and dynamic frequency/voltage scaling, becoming mainstream. However, further power savings are still needed for extremely power-constrained applications, such as green computing, mobile wireless communications, sensor networks, and biomedical devices. Feasible ways of achieving further power savings include, for example, sub-threshold and ultra-low-voltage operation, SOI technology and circuits, and 3-D and heterogeneous integration. The 2016 IEEE Unified S3S (SOI-3D-SubVt) Conference event gathered researchers studying the aforementioned three topics to share their views and advances regarding lower-power and more efficient ICs and SoCs.

This issue of JLPEA is the sixth special issue dedicated to selected papers from the IEEE S3S Conference 2016 held in Burlingame, CA, on October 10-13, 2016. Extended versions of papers presented at the conference will be invited for submission to this special issue. A selection of the invited papers will be made based on their low-power content and their scientific/technical excellence.

Prof. David Bol
Dr. Steven A. Vitale
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. For selected papers, all Article Processing Charge (APC) for publication in this Special Issue will be waived. Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • ultra-low voltage circuits and design techniques
  • SOI-specific circuits and design techniques
  • SOI devices, processes, and technologies
  • 3-D and heterogeneous system integration
  • memory design and technologies
  • analog and RF technologies and circuits
  • implantable and handheld biomedical devices
  • transistor variability and mitigation
  • ultra-low-power computation
  • device and fabrication technology
  • energy harvesting techniques
  • unattended remote sensors

Published Papers (2 papers)

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Research

Open AccessArticle Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection
J. Low Power Electron. Appl. 2017, 7(2), 16; https://doi.org/10.3390/jlpea7020016
Received: 1 March 2017 / Revised: 28 May 2017 / Accepted: 6 June 2017 / Published: 11 June 2017
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Abstract
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas requiring near-sensor processing, including elaboration of biosignals. Parallel near-threshold computing is emerging as an approach to achieve significant improvements in energy efficiency while overcoming the performance
[...] Read more.
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas requiring near-sensor processing, including elaboration of biosignals. Parallel near-threshold computing is emerging as an approach to achieve significant improvements in energy efficiency while overcoming the performance degradation typical of low-voltage operations. In this paper, we demonstrate the capabilities of the PULP (Parallel Ultra-Low Power) platform on an algorithm for seizure detection, representative of a wide range of EEG signal processing applications. Starting from the 28-nm FD-SOI (Fully Depleted Silicon On Insulator) technology implementation of the third embodiment of the PULP architecture, we analyze the energy-efficient implementation of the seizure detection algorithm on PULP. The proposed parallel implementation exploits the dynamic voltage and frequency scaling capabilities, as well as the embedded power knobs of the PULP platform, reducing energy consumption for a seizure detection by up to 10× with respect to a sequential implementation at the nominal supply voltage and by 4.2× with respect to a sequential implementation with voltage scaling. Moreover, we analyze the trans-precision optimization of the algorithm on PULP, by means of a hybrid fixed- and floating-point implementation. This approach reduces the energy consumption by up to 43% with respect to the plain fixed-point and floating-point implementations, leveraging the requirements in terms of the precision of the kernels composing the processing chain to improve energy efficiency. Thanks to the proposed architecture and system-level approach for optimization, we demonstrate that PULP reduces energy consumption by up to 140× with respect to commercial low-power microcontrollers, being able to satisfy the real-time constraints typical of bio-medical applications, breaking the barrier of microwatts for a 50-ms complete seizure detection and a few milliwatts for a 5-ms detection latency on a fully-programmable architecture. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2016)
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Open AccessArticle Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
J. Low Power Electron. Appl. 2017, 7(2), 11; https://doi.org/10.3390/jlpea7020011
Received: 2 March 2017 / Revised: 29 April 2017 / Accepted: 4 May 2017 / Published: 11 May 2017
PDF Full-text (1899 KB) | HTML Full-text | XML Full-text
Abstract
This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a
[...] Read more.
This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2016)
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