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JLPEA
Special Issues
Selected Papers from SubVt 2011 Conference
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Selected Papers from SubVt 2011 Conference

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (1 March 2012) | Viewed by 58540

Special Issue Editors

Prof. Dr. David Bol

E-Mail Website
Guest Editor
ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
Special Issues, Collections and Topics in MDPI journals
Dr. Steven A. Vitale

E-Mail Website
Guest Editor
Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108, USA
Interests: quantum devices; solid state physics; plasma physics
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Collleagues,

Subthreshold microelectronic circuits are gaining momentum for ultra-low-power applications but their maturity remains low when compared to conventional above-threshold designs. Therefore, this special issue of JLPEA is intended to focus on the advances in subthreshold microelectronics with extended versions of papers presented from the 2011 Subthreshold Microelectronics Conference (SubVt 2011) held in Lexington, MA, USA on 26-27 September 2011. However, other works related to ultra-low-power microelectronics not presented at SubVt 2011 will also be considered.

Dr. David Bol
Dr. Steven A. Vitale
Guest Editors

Keywords

Research and review papers on subthreshold microelectronics are solicited in areas including, but not limited to:

  • unattended remote sensors
  • memory technologies
  • space-based sensors
  • radiation effects
  • implantable biomedical devices
  • transistor variability and mitigation
  • handheld biomedical devices
  • energy harvesting techniques
  • ultra-low-power computation
  • asynchronous circuits
  • analog and RF technologies
  • device and fabrication technology

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Published Papers (6 papers)

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Research

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1656 KiB  
Article
Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI
by Chien-Yu Lu and Ching-Te Chuang
J. Low Power Electron. Appl. 2012, 2(4), 282-300; https://doi.org/10.3390/jlpea2040282 - 12 Dec 2012
Cited by 3 | Viewed by 10096
Abstract
This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and [...] Read more.
This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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481 KiB  
Article
A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications
by Sakkarapani Balagopal and Vishal Saxena
J. Low Power Electron. Appl. 2012, 2(3), 197-209; https://doi.org/10.3390/jlpea2030197 - 26 Jul 2012
Cited by 8 | Viewed by 9973
Abstract
A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design [...] Read more.
A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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621 KiB  
Article
Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS
by Jani Mäkipää, Matthew J. Turnquist, Erkka Laulainen and Lauri Koskinen
J. Low Power Electron. Appl. 2012, 2(2), 180-196; https://doi.org/10.3390/jlpea2020180 - 6 Jun 2012
Cited by 15 | Viewed by 8422
Abstract
This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. [...] Read more.
This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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556 KiB  
Article
Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation
by Ameet Chavan, Praveen Palakurthi, Eric MacDonald, Joseph Neff and Eric Bozeman
J. Low Power Electron. Appl. 2012, 2(2), 168-179; https://doi.org/10.3390/jlpea2020168 - 24 May 2012
Cited by 4 | Viewed by 9291 | Correction
Abstract
A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold ( Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and [...] Read more.
A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold ( < Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μm fully-depleted SOI CMOS technology—a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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1253 KiB  
Article
0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process
by Piotr Olejarz, Kyoungchul Park, Samuel MacNaughton, Mehmet R. Dokmeci and Sameer Sonkusale
J. Low Power Electron. Appl. 2012, 2(2), 155-167; https://doi.org/10.3390/jlpea2020155 - 18 May 2012
Cited by 4 | Viewed by 11569
Abstract
We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have [...] Read more.
We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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Review

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296 KiB  
Review
Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN
by James Boley, Jiajing Wang and Benton H. Calhoun
J. Low Power Electron. Appl. 2012, 2(2), 143-154; https://doi.org/10.3390/jlpea2020143 - 18 Apr 2012
Cited by 9 | Viewed by 8305
Abstract
The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable [...] Read more.
The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write VMIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4–13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the unassisted test case. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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