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JLPEA
Special Issues
Selected Papers from IEEE S3S Conference 2015
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Selected Papers from IEEE S3S Conference 2015

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 March 2016) | Viewed by 34315

Special Issue Editors

Prof. Dr. David Bol

E-Mail Website
Guest Editor
ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
Special Issues, Collections and Topics in MDPI journals
Dr. Steven A. Vitale

E-Mail Website
Guest Editor
Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108, USA
Interests: quantum devices; solid state physics; plasma physics
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

For more than two decades, low-power consumption has been paramount for integrated circuits (ICs) and systems-on-a-chip (SoCs). In today’s sub-100 nm technologies, low-power design flows are maturing with techniques, such as clock/power gating, multi-Vt/Vdd assignment, and dynamic frequency/voltage scaling, becoming mainstream. However, further power savings are still needed for extremely power-constrained applications, such as green computing, mobile wireless communications, sensor networks, and biomedical devices. Feasible ways of achieving further power savings include, for example, sub-threshold and ultra-low-voltage operation, SOI technology and circuits, and 3-D and heterogeneous integration. The 2015 IEEE Unified S3S (SOI-3D-SubVt) Conference event gathered researchers studying the aforementioned three topics to share their views and advances regarding lower-power and more efficient ICs and SoCs.

This issue of JLPEA is the fifth special issue dedicated to selected papers from the IEEE S3S Conference 2015 held in Rohnert Park, CA, on October 5-8, 2015. Extended versions of papers presented at the conference will be invited for submission to this special issue. A selection of the invited papers will be made based on their low-power content and their scientific/technical excellence.

Prof. David Bol
Dr. Steven A. Vitale
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

About Copyright

For the IEEE-copyrighted materials published in the S3S proceedings (e.g. figures/tables), the authors are responsible to acquire reprint permissions if they want to use them without significant modifications and to make the following IEEE credit/copyright notice appears prominently in the figure/table caption:
Based on "(full paper title)", by (authors' names) which appeared in (complete publication information). © [Year] IEEE.
Moreover, a new title is requested for the new paper (extended version of the IEEE conference paper), to indicate that the paper has been substantially revised.

Keywords

  • ultra-low voltage circuits and design techniques
  • SOI-specific circuits and design techniques
  • SOI devices, processes, and technologies
  • 3-D and heterogeneous system integration
  • memory design and technologies
  • analog and RF technologies and circuits
  • implantable and handheld biomedical devices
  • transistor variability and mitigation
  • ultra-low-power computation
  • device and fabrication technology
  • energy harvesting techniques
  • unattended remote sensors

Published Papers (4 papers)

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Research

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995 KiB  
Article
InGaAs-OI Substrate Fabrication on a 300 mm Wafer
by Sebastien Sollier, Julie Widiez, Gweltaz Gaudin, Frederic Mazen, Thierry Baron, Mickail Martin, Marie-Christine Roure, Pascal Besson, Christophe Morales, Elodie Beche, Frank Fournel, Sylvie Favier, Amelie Salaun, Patrice Gergaud, Maryline Cordeau, Christellle Veytizou, Ludovic Ecarnot, Daniel Delprat, Ionut Radu and Thomas Signamarcheix
J. Low Power Electron. Appl. 2016, 6(4), 19; https://doi.org/10.3390/jlpea6040019 - 30 Sep 2016
Cited by 3 | Viewed by 7055
Abstract
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM [...] Read more.
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2015)
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3041 KiB  
Article
A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs
by Yu Huang, Aatmesh Shrivastava, Laura E. Barnes and Benton H. Calhoun
J. Low Power Electron. Appl. 2016, 6(3), 11; https://doi.org/10.3390/jlpea6030011 - 23 Jun 2016
Cited by 3 | Viewed by 7615
Abstract
This paper presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter supports [...] Read more.
This paper presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter supports energy harvesting systems that need to use very low voltages. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2015)
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4633 KiB  
Article
A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications
by Divya Akella Kamakshi, Aatmesh Shrivastava and Benton H. Calhoun
J. Low Power Electron. Appl. 2016, 6(2), 10; https://doi.org/10.3390/jlpea6020010 - 15 Jun 2016
Cited by 15 | Viewed by 10674
Abstract
We propose a fully on-chip CMOS temperature sensor in which a sub-threshold (sub-VT) proportional-to-absolute-temperature (PTAT) current element starves a current-controlled oscillator (CCO). Sub-VT design enables ultra-low-power operation of this temperature sensor. However, such circuits are highly sensitive to process variations, [...] Read more.
We propose a fully on-chip CMOS temperature sensor in which a sub-threshold (sub-VT) proportional-to-absolute-temperature (PTAT) current element starves a current-controlled oscillator (CCO). Sub-VT design enables ultra-low-power operation of this temperature sensor. However, such circuits are highly sensitive to process variations, thereby causing varying circuit currents from die to die. We propose a bit-weighted current mirror (BWCM) architecture to resist the effect of process-induced variation in the PTAT current. The analog core constituting the PTAT, the CCO, and the BWCM is operational down to 0.2 V supply voltage. A digital block operational at 0.5 V converts the temperature information into a digital code that can be processed and used by other components in a system-on-chip (SoC). The proposed temperature sensor system also supports resolution-power trade-off for Internet-of-things (IoT) applications with different sampling rates and energy needs. The system power consumption is 23 nW and the maximum temperature inaccuracy is +1.5/−1.7 °C from 0 °C to 100 °C with a two-point calibration. The temperature sensor system was designed in a 130 nm CMOS technology and its total area is 250 × 250 μm2. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2015)
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Review

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1339 KiB  
Review
Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling
by Nadine Collaert
J. Low Power Electron. Appl. 2016, 6(2), 9; https://doi.org/10.3390/jlpea6020009 - 14 Jun 2016
Viewed by 8209
Abstract
In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be [...] Read more.
In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed for both density scaling (“more Moore”) and functional scaling to enhance on-chip functionality (“more than Moore”). Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2015)
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