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Article

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

1
Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA
2
Fermi National Accelerator Laboratory, Batavia, IL 60510, USA
*
Author to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2018, 8(3), 25; https://doi.org/10.3390/jlpea8030025
Received: 15 June 2018 / Revised: 21 July 2018 / Accepted: 27 July 2018 / Published: 30 July 2018
(This article belongs to the Special Issue CMOS Low Power Design)
In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis. View Full-Text
Keywords: Content Addressable Memory (CAM); TCAM; multi-Vdd; multi supply; associative memory; tunable operation; standby power; searchline power; matchline power Content Addressable Memory (CAM); TCAM; multi-Vdd; multi supply; associative memory; tunable operation; standby power; searchline power; matchline power
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MDPI and ACS Style

Joshi, S.; Li, D.; Ogrenci-Memik, S.; Deptuch, G.; Hoff, J.; Jindariani, S.; Liu, T.; Olsen, J.; Tran, N. Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis. J. Low Power Electron. Appl. 2018, 8, 25. https://doi.org/10.3390/jlpea8030025

AMA Style

Joshi S, Li D, Ogrenci-Memik S, Deptuch G, Hoff J, Jindariani S, Liu T, Olsen J, Tran N. Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis. Journal of Low Power Electronics and Applications. 2018; 8(3):25. https://doi.org/10.3390/jlpea8030025

Chicago/Turabian Style

Joshi, Siddhartha, Dawei Li, Seda Ogrenci-Memik, Grzegorz Deptuch, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, and Nhan Tran. 2018. "Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis" Journal of Low Power Electronics and Applications 8, no. 3: 25. https://doi.org/10.3390/jlpea8030025

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