Special Issue "CMOS Power Amplifier Design and Applications"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microwave and Wireless Communications".

Deadline for manuscript submissions: 30 November 2020.

Special Issue Editors

Prof. Dr. Ilku Nam
Website
Guest Editor
Integrated Circuits & Systems Lab., Dept. of Electrical Engineering, Pusan National University, 2 Busandaehak-ro, Geumjeong-gu, Busan 46241, Korea
Interests: CMOS RF/mmWave/analog integrated circuits and systems for mobile communications, radar sensors and power applications
Prof. Dr. Ockgoo Lee
Website
Guest Editor
Wave Integrated Circuits and Systems Lab., Dept. of Electrical Engineering, Pusan National University, Busan 46241, Korea
Interests: power amplifier; high-frequency integrated circuits and system design for wireless communications

Special Issue Information

Dear Colleagues,

The design of CMOS power amplifiers continues to pose challenges in the design of wireless transceivers because of the low breakdown voltage in CMOS devices, the no-substrate via-hole in the CMOS process, and the low quality of the passive components. In particular, a highly linear power amplifier is required because of the high peak-to-average power ration and the wide bandwidth signal for 5G and next generation WLAN systems. The power amplifiers are required to operate in a large back-off point from the in a saturation power region, resulting in decreased efficiency. Also, recent wireless communication standards require power amplifiers supporting dual or multi-bands. On the other hand, it is important to develop a tunable power amplifier that can minimize the efficiency degradation under impedance mismatch conditions.
The objective of this Special Issue is to provide the latest research related to CMOS power amplifier design and applications. The topics span from passive device (e.g. transformer) design and modeling for CMOS power amplifiers, circuit technology improving output power, linearity and efficiency to transmitters, including CMOS power amplifiers.

This Special Issue of Electronics invites the submission of technical papers that may address, but are not limited to, the following:

  • CMOS power amplifiers for 5G systems, LTE, WLAN, etc.
  • CMOS power amplifiers with high power, high efficiency and/or high linearity
  • Dual-band or multi-band CMOS power amplifiers
  • Tunable CMOS power amplifiers
  • Envelope tracking power amplifiers
  • Doherty power amplifiers
  • Outphasing power amplifiers
  • Digital power amplifiers
  • Transmitters with CMOS power amplifiers

Prof. Dr. Ilku Nam
Prof. Dr. Ockgoo Lee
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1500 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • 5G millimeter-wave power amplifiers
  • Power amplifiers with high efficiency, high linearity and high output power
  • Dual-band or multi-band power amplifiers
  • Multi-mode power amplifiers
  • Advanced power amplifiers

Published Papers (6 papers)

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Research

Open AccessArticle
A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors
Electronics 2020, 9(10), 1600; https://doi.org/10.3390/electronics9101600 - 30 Sep 2020
Abstract
This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this [...] Read more.
This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this circuit is the wideband input match along with a reduced NF (5.5–9.6 dB) and, to the authors’ knowledge, the lowest die footprint reported (62 × 44 μm2 area). The implementation of the RF-VGA based on CCCII allows a wideband input match without the need of passive elements. Due to the nature of the circuit, when the gain is increased, the power consumption is reduced. The architecture is suitable for designing wideband, low-power, and low-noise amplifiers. The proposed design achieves a tunable gain of 6.7–18 dB and a power consumption of 1.7 mA with a ±1.5 V DC supply. At maximum gain, the proposed RF-VGA covers from DC up to 1 GHz and can find application in software design radios (SDRs), the low frequency medical implant communication system (MICS) or industrial, scientific, and medical (ISM) bands. Full article
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
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Open AccessArticle
Broadband Millimeter-Wave Power Amplifier Using Modified 2D Distributed Power Combining
Electronics 2020, 9(6), 899; https://doi.org/10.3390/electronics9060899 - 28 May 2020
Abstract
A broadband millimeter-wave (mmWave) power amplifier (PA) was implemented using a modified 2D distributed power combining technique. The proposed power combining was based on a single-ended dual-fed distributed combining (SEDFDC) design technique using zero-phase shifting (ZPS) transmission lines. To improve the input/output power [...] Read more.
A broadband millimeter-wave (mmWave) power amplifier (PA) was implemented using a modified 2D distributed power combining technique. The proposed power combining was based on a single-ended dual-fed distributed combining (SEDFDC) design technique using zero-phase shifting (ZPS) transmission lines. To improve the input/output power distribution of each power cell within a wide frequency range, N/2-way power dividers/combiners were inserted into the distributed combining structure. Modified ZPS lines also simplified the combining structure and curbed phase variation according to the frequency. These modifications enabled power combining cells to increase without degrading the power bandwidth. The proposed PA was fabricated with a commercial 0.15 μm GaAs pseudo high electron-mobility transistor (pHEMT) monolithic microwave-integrated circuit (MMIC) process. It exhibited 20.3 to 24.2 dBm output power (Pout), 12.9 to 21.8 dB power gain, and 5.2% to 12.7% power-added efficiency (PAE) between 26 and 56 GHz. Full article
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
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Open AccessArticle
A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors
Electronics 2020, 9(4), 617; https://doi.org/10.3390/electronics9040617 - 06 Apr 2020
Cited by 2
Abstract
In this paper, the influence of the DC-blocking capacitors leveraged in coplanar waveguide (CPW) matching networks is studied. CPW matching networks with series-connected DC-blocking capacitors are less sensitive to capacitance and are adopted in a 28 GHz power amplifier (PA). The PA targeting [...] Read more.
In this paper, the influence of the DC-blocking capacitors leveraged in coplanar waveguide (CPW) matching networks is studied. CPW matching networks with series-connected DC-blocking capacitors are less sensitive to capacitance and are adopted in a 28 GHz power amplifier (PA). The PA targeting fifth-generation (5G) phased array is developed in 90 nm silicon-on-insulator complementary-metal-oxide-semiconductor (SOI CMOS) technology. A stacked field-effect-transistor (FET) architecture is elected in the output stage to boost the output power and reduce the die area. The PA with a core area of 0.31 mm2 demonstrates a maximum small signal gain of 13.7 dB and a −3 dB bandwidth of 6.3 GHz (22.9–29.2 GHz). The PA achieves a measured saturated output power (Psat) of 14.4 dBm and a peak power added efficiency (PAE) of 25% for continuous wave signals. At 24/25.6/28 GHz, the PA achieves +7.87/+9.16/+10.7 dBm measured output power and 6.21%/8.11%/10.17% PAE at −25 dBc error vector magnitude(EVM) for a 250 MHz-wide 64-quadrature amplitude modulation (64-QAM). The developed linear PA provides a great potential for low-cost 5G phased array transceivers. Full article
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
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Open AccessFeature PaperArticle
A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications
Electronics 2020, 9(4), 562; https://doi.org/10.3390/electronics9040562 - 27 Mar 2020
Cited by 1
Abstract
A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and [...] Read more.
A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration. Full article
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
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Open AccessFeature PaperArticle
A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method
Electronics 2020, 9(2), 257; https://doi.org/10.3390/electronics9020257 - 03 Feb 2020
Abstract
This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is [...] Read more.
This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is much smaller. The outphasing operations of the transformer combiners and class-D switching PAs are also analyzed. A tuning inductor method is proposed to improve the efficiency of class-D power amplifiers (PAs) with power-combining transformers in the out-of-phase mode. The proposed PA was implemented with a standard 0.18 µm CMOS process. The measured maximum drain efficiency is 37.3% with an output power of 22.4 dBm at 1.7 GHz. A measured adjacent channel leakage ratio (ACLR) of less than −30 dBc is obtained for a long-term evolution (LTE) signal with a bandwidth of 10 MHz. Full article
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
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Open AccessFeature PaperArticle
Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity
Electronics 2020, 9(1), 103; https://doi.org/10.3390/electronics9010103 - 06 Jan 2020
Cited by 1
Abstract
We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to [...] Read more.
We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s. Full article
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
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Planned Papers

The below list represents only planned manuscripts. Some of these manuscripts have not been received by the Editorial Office yet. Papers submitted to MDPI journals are subject to peer-review.

Paper 1:

Antiphase Method of CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

Jiwon Kim, Changhyun Lee, Jinho Yoo and Changkun Park

School of Electric Engineering, Soongsil University, 369, Sangdo-ro, Dongjak-gu, Seoul, 06978, Korea

 Abstract: We present the possibility of a CMOS power amplifier (PA) using a driver stage composed of PMOS to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42-GHz PA using a 180-nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11n modulated signal with 64-QAM (MCS7) at 65 Mb/s.

 

Paper 2:

A Reconfigurable CMOS Inverter-Based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications

Dongmyeong Kim, Dongmin Kim and Donggu Im

Division of Electronic Engineering, Jeonbuk National University, Jollabuk-do 561-756, Korea

Abstract: A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend the impedance coverage maintaining the output power of greater than +2 dBm under the worst case for antenna impedance mismatch. The adopted process technology supports multi-threshold MOSFET devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing and output power under the given load condition. The NMOS and PMOS cascode transistors are added to the conventional inverter amplifier to provide a high output impedance and achieve a maximum output power into the high impedance load, and these cascode transistors also operate as digital switches by completely turning on them. This reconfigurable cascode inverter topology relaxes the breakdown issues when it is driven by 2xVDD supply voltage. By stacking two identical reconfigurable cascode inverter amplifiers and enabling one of them or both through digital switch control, the proposed PA achieves a maximum output power into the load impedance of 100, 50 and 25 ohms with high peak power added efficiency (PAE). The proposed PA was designed using a 65-nm CMOS process for low power short-range wireless communications, and it was driven by 2x1.2 V supply voltage without any reliability issues. In the simulation results, it showed the saturated output power (Psat) of +5.8 dBm and peak PAE of 41.7 % at 100 ohm load impedance, Psat of +3.6 dBm and peak PAE of 39.3 % at 50 ohm load impedance and Psat of +4.5 dBm and peak PAE of 34.9 % at 25 ohm load impedance, respectively, in the 2.4 GHz ISM band. Through only hardware re-configurability, the impedance coverage maintaining the output power of greater than +2 dBm of the proposed PA increased to double without sacrificing the power efficiency compared to the conventional inverter-based PA.

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