Special Issue "CMOS Power Amplifier Design and Applications"
Deadline for manuscript submissions: 30 November 2020.
Interests: CMOS RF/mmWave/analog integrated circuits and systems for mobile communications, radar sensors and power applications
Interests: power amplifier; high-frequency integrated circuits and system design for wireless communications
The design of CMOS power amplifiers continues to pose challenges in the design of wireless transceivers because of the low breakdown voltage in CMOS devices, the no-substrate via-hole in the CMOS process, and the low quality of the passive components. In particular, a highly linear power amplifier is required because of the high peak-to-average power ration and the wide bandwidth signal for 5G and next generation WLAN systems. The power amplifiers are required to operate in a large back-off point from the in a saturation power region, resulting in decreased efficiency. Also, recent wireless communication standards require power amplifiers supporting dual or multi-bands. On the other hand, it is important to develop a tunable power amplifier that can minimize the efficiency degradation under impedance mismatch conditions.
The objective of this Special Issue is to provide the latest research related to CMOS power amplifier design and applications. The topics span from passive device (e.g. transformer) design and modeling for CMOS power amplifiers, circuit technology improving output power, linearity and efficiency to transmitters, including CMOS power amplifiers.
This Special Issue of Electronics invites the submission of technical papers that may address, but are not limited to, the following:
- CMOS power amplifiers for 5G systems, LTE, WLAN, etc.
- CMOS power amplifiers with high power, high efficiency and/or high linearity
- Dual-band or multi-band CMOS power amplifiers
- Tunable CMOS power amplifiers
- Envelope tracking power amplifiers
- Doherty power amplifiers
- Outphasing power amplifiers
- Digital power amplifiers
- Transmitters with CMOS power amplifiers
Prof. Dr. Ilku Nam
Prof. Dr. Ockgoo Lee
Manuscript Submission Information
Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.
Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.
Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1500 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.
- 5G millimeter-wave power amplifiers
- Power amplifiers with high efficiency, high linearity and high output power
- Dual-band or multi-band power amplifiers
- Multi-mode power amplifiers
- Advanced power amplifiers
The below list represents only planned manuscripts. Some of these manuscripts have not been received by the Editorial Office yet. Papers submitted to MDPI journals are subject to peer-review.
Antiphase Method of CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity
Jiwon Kim, Changhyun Lee, Jinho Yoo and Changkun Park
School of Electric Engineering, Soongsil University, 369, Sangdo-ro, Dongjak-gu, Seoul, 06978, Korea
Abstract: We present the possibility of a CMOS power amplifier (PA) using a driver stage composed of PMOS to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42-GHz PA using a 180-nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11n modulated signal with 64-QAM (MCS7) at 65 Mb/s.
A Reconfigurable CMOS Inverter-Based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications
Dongmyeong Kim, Dongmin Kim and Donggu Im
Division of Electronic Engineering, Jeonbuk National University, Jollabuk-do 561-756, Korea
Abstract: A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend the impedance coverage maintaining the output power of greater than +2 dBm under the worst case for antenna impedance mismatch. The adopted process technology supports multi-threshold MOSFET devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing and output power under the given load condition. The NMOS and PMOS cascode transistors are added to the conventional inverter amplifier to provide a high output impedance and achieve a maximum output power into the high impedance load, and these cascode transistors also operate as digital switches by completely turning on them. This reconfigurable cascode inverter topology relaxes the breakdown issues when it is driven by 2xVDD supply voltage. By stacking two identical reconfigurable cascode inverter amplifiers and enabling one of them or both through digital switch control, the proposed PA achieves a maximum output power into the load impedance of 100, 50 and 25 ohms with high peak power added efficiency (PAE). The proposed PA was designed using a 65-nm CMOS process for low power short-range wireless communications, and it was driven by 2x1.2 V supply voltage without any reliability issues. In the simulation results, it showed the saturated output power (Psat) of +5.8 dBm and peak PAE of 41.7 % at 100 ohm load impedance, Psat of +3.6 dBm and peak PAE of 39.3 % at 50 ohm load impedance and Psat of +4.5 dBm and peak PAE of 34.9 % at 25 ohm load impedance, respectively, in the 2.4 GHz ISM band. Through only hardware re-configurability, the impedance coverage maintaining the output power of greater than +2 dBm of the proposed PA increased to double without sacrificing the power efficiency compared to the conventional inverter-based PA.