Special Issue "Energy Efficient Circuit Design Techniques for Low Power Systems"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (28 February 2021).

Special Issue Editor

Dr. Inhee Lee
E-Mail Website
Guest Editor
Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA 15261, USA
Interests: miniature sensor system development; low power & energy efficient analog/mixed-signal/digital circuit design; adaptive circuit design to tolerate environment and process variation; energy harvesting circuit; power/battery management circuit; sensor/sensor interface; voltage/current/timing reference
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Special Issue Information

Dear Colleagues,

Low-power systems have become attractive solutions in a variety of applications, such as biomedical, security, energy exploration, infrastructure, and internet-of-things. Low power consumption enables extension of system lifetime and also reduces the total system size by using smaller energy storage devices (battery or supercapacitor). One basic technique to reduce the average power consumption is “duty cycle” switching the operation between long ultra-low-power sleep mode and short high-performance mode. Based on this method, advanced systems have recently been developed by suppressing power consumption lower in sleep mode and improving energy efficiency of circuit operation in active mode. Also, circuits for energy harvesting, power conversion, and energy storage management are critical to extend the system lifetime and run load circuits more energy efficiently with the minimum margin.

Topics in this Special Issue include (but are not limited to):

  • Analog or digital circuit design techniques to enable low-power systems;
  • Ultra-low-power circuit designs for standby-mode operation;
  • Energy-efficient circuit designs for active-mode operation;
  • Circuit designs for energy harvesting and power conversion;
  • Smart management circuits or systems for energy storage devices;

Dr. Inhee Lee
Guest Editor

Manuscript Submission Information

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Keywords

  • energy efficient
  • low power
  • low energy
  • adaptive
  • energy harvesting
  • power management
  • sensor
  • sensor interface

Published Papers (13 papers)

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Research

Article
A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers
Electronics 2021, 10(7), 780; https://doi.org/10.3390/electronics10070780 - 25 Mar 2021
Viewed by 682
Abstract
This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock [...] Read more.
This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement
Electronics 2021, 10(6), 685; https://doi.org/10.3390/electronics10060685 - 15 Mar 2021
Cited by 1 | Viewed by 694
Abstract
To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged [...] Read more.
To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers
Electronics 2021, 10(2), 145; https://doi.org/10.3390/electronics10020145 - 11 Jan 2021
Cited by 2 | Viewed by 1186
Abstract
A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one [...] Read more.
A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Low Voltage Time-Based Matrix Multiplier-and-Accumulator for Neural Computing System
Electronics 2020, 9(12), 2138; https://doi.org/10.3390/electronics9122138 - 14 Dec 2020
Viewed by 751
Abstract
A time-based matrix multiply-and-accumulate (MAC) operation for a neural computing system is described. A simple and compact time-based matrix MAC structure is proposed that can perform multiplication and accumulation simultaneously in a single multiplier structure, and the hardware complexity is not affected by [...] Read more.
A time-based matrix multiply-and-accumulate (MAC) operation for a neural computing system is described. A simple and compact time-based matrix MAC structure is proposed that can perform multiplication and accumulation simultaneously in a single multiplier structure, and the hardware complexity is not affected by the matrix input size. To enhance the linearity of the weight factor, an offset-free pulse-width modulator is introduced. The proposed MAC architecture operates at a low supply voltage of 0.5 V while it consumes MAC energy of 0.38 pJ with a 32 nm low-power (LP) predictive technology model (PTM) CMOS process. In addition, the near-subthreshold operation can remove the level shifter to interface between the MAC operator and digital circuits such as static random-access-memory (SRAM) because both can utilize the same level of the supply voltage. The proposed MAC is based on a digital intensive pulse-width modulation, and thus it can further improve its performance and area with more advanced technologies. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Feasibility of Harvesting Solar Energy for Self-Powered Environmental Wireless Sensor Nodes
Electronics 2020, 9(12), 2058; https://doi.org/10.3390/electronics9122058 - 03 Dec 2020
Cited by 6 | Viewed by 829
Abstract
Energy harvesting has a vital role in building reliable Environmental Wireless Sensor Networks (EWSNs), without needing to replace a discharged battery. Solar energy is one of the main renewable energy sources that can be used to efficiently charge a battery. This paper introduces [...] Read more.
Energy harvesting has a vital role in building reliable Environmental Wireless Sensor Networks (EWSNs), without needing to replace a discharged battery. Solar energy is one of the main renewable energy sources that can be used to efficiently charge a battery. This paper introduces two solar energy harvesters and their power measurements at different light conditions in order to charge rechargeable AA batteries powering EWSN nodes. The first harvester is a primitive energy harvesting circuit that is built using elementary off-shelf components, while the second harvester is based on a commercial boost converter chip. To prove the effectiveness of harvesting solar energy, five EWSN nodes were distributed at a nature reserve (the Audubon Society of Western Pennsylvania, USA) and the sunlight at their locations was recorded for more than five months. For each recorded illumination, the corresponding harvested energy has been estimated and compared with the average energy consumption of the EWSN with the most power consumption. The results show that the daily harvested energy effectively compensates for the energy consumption of the EWSN nodes, and the battery charge capacity of 295 mAh can reliably support their daily dynamic energy consumption. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Novel Low-Complexity and Low-Power Flip-Flop Design
Electronics 2020, 9(5), 783; https://doi.org/10.3390/electronics9050783 - 10 May 2020
Viewed by 1202
Abstract
In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide [...] Read more.
In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Delta-Sigma Modulator-Based Step-Up DC–DC Converter with Dynamic Output Voltage Scaling
Electronics 2020, 9(3), 498; https://doi.org/10.3390/electronics9030498 - 18 Mar 2020
Cited by 1 | Viewed by 1233
Abstract
The switching noise and conversion efficiency of step-up DC-DC converters need to be improved to meet increasing demand. The delta-sigma modulation (DSM) technique is typically used to improve the performance of buck converters; however, this control scheme is not directly applicable for boost [...] Read more.
The switching noise and conversion efficiency of step-up DC-DC converters need to be improved to meet increasing demand. The delta-sigma modulation (DSM) technique is typically used to improve the performance of buck converters; however, this control scheme is not directly applicable for boost converters. This paper presents a boost DC–DC converter using a continuous-time delta-sigma modulator (DSM) controller for battery-powered and noise-sensitive applications. The proposed converter can adjust a wide range of output voltages dynamically by clamping the maximum duty cycle of the DSM, thus enabling stable and robust transient responses of the converter. The switching harmonics in the converter output are reduced effectively by the noise shaping property of the modulator. Moreover, the converter does not suffer from instability of mode switching due to the use of a fixed third-order DSM. Fabricated in a 180 nm CMOS, the converter occupies an active area of 0.76 mm2. It produced an output voltage ranging from 2.5 V to 5.0 V at an input voltage of 2.0 V and achieved a peak conversion efficiency of 95.5%. The output voltage ripples were maintained under 25 mV for all load conditions. A low noise output spectrum with a first spurious peak located −91 dBc from the signal was achieved. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Experimental Frequency Tuning Methodology of a Cantilever Piezoelectric Harvester Validated in a Multimodal Transportation
Electronics 2020, 9(1), 79; https://doi.org/10.3390/electronics9010079 - 01 Jan 2020
Cited by 5 | Viewed by 1023
Abstract
Piezoelectric energy harvesting is a promising technology that increases the autonomy of low power IoT devices in scenarios that are subjected to mechanical vibrations. This work shows the potential of this technology to power IoT devices with the energy that is harvested from [...] Read more.
Piezoelectric energy harvesting is a promising technology that increases the autonomy of low power IoT devices in scenarios that are subjected to mechanical vibrations. This work shows the potential of this technology to power IoT devices with the energy that is harvested from vibrations occurred during air and road transportation. Adjusting the natural resonance frequency of the piezoelectric generator (PEG) to the mechanical acceleration frequency that has the highest power spectral density is key to increase the harvested energy. Therefore, in this work a commercial PEG is tuned to the best spectrogram frequency of a real vibration signal following a two-phase tuning process. The harvested power generated by the PEG has been validated in real scenarios, providing 2.4 μ Wh during flight (take-off, cruise flight, and landing), 11.3 μ Wh during truck transportation in urban areas, and 4.8 μ Wh during intercity transportation. The PEG has been embedded in an ultra-low power IoT device to validate how much this harvested energy can increase the autonomy in a real scenario that is subjected to similar vibrations. An NFC temperature data logger is developed for perishable products that are transported by air and road transports. The energy harvested by the PEG tuned with the methodology proposed in this work has increased the autonomy of the data logger 16.7% during a real use case of 30 h, which validates the potential of the piezoelectric energy harvesting technology to increase the autonomy of future low power IoT devices used in scenarios with aperiodic vibrations. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
A Hybrid Microenergy Storage System for Power Supply of Forest Wireless Sensor Nodes
Electronics 2019, 8(12), 1409; https://doi.org/10.3390/electronics8121409 - 26 Nov 2019
Cited by 5 | Viewed by 989
Abstract
Wireless sensor nodes (WSNs) are widely used in the field of environmental detection; however, they face serious power supply problems caused by the complexity of the environmental layout. In this study, a new ultra-low-power hybrid energy harvesting (HEH) system for two types of [...] Read more.
Wireless sensor nodes (WSNs) are widely used in the field of environmental detection; however, they face serious power supply problems caused by the complexity of the environmental layout. In this study, a new ultra-low-power hybrid energy harvesting (HEH) system for two types of microenergy collection (photovoltaic (PV) and soil-temperature-difference thermoelectric (TE)) was designed to provide stable power to WSNs. The power supply capabilities of two microenergy sources were assessed by analyzing the electrical characteristics and performing continuous energy data collection. The HEH system consisted of two separated power converters and an electronic multiplexer circuit to avoid impedance mismatch and improve efficiency. The feasibility of the self-powered HEH system was verified by consumption analysis of the HEH system, the WSNs, and the data analysis of the collected microenergy. Taking the summation of PV and TEG input power of 1.26 mW (PPV:PTEG was about 3:1) as an example, the power loss of the HEH system accounted for 33.8% of the total input power. Furthermore, the ratio decreased as the value of the input power increased. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
A Systematic Equalizer Design Technique Using Backward Directional Design
Electronics 2019, 8(9), 1053; https://doi.org/10.3390/electronics8091053 - 18 Sep 2019
Viewed by 956
Abstract
This paper presents a systematic equalizer design methodology using a backward directional design (BDD). The proposed design method includes pre-emphasis and crosstalk cancellation design and offers a proper waveform solution for transmitters (TX). Since it is driven by a user-defined specification, it avoids [...] Read more.
This paper presents a systematic equalizer design methodology using a backward directional design (BDD). The proposed design method includes pre-emphasis and crosstalk cancellation design and offers a proper waveform solution for transmitters (TX). Since it is driven by a user-defined specification, it avoids over/under design, reducing wasted power. Furthermore, the proposed design procedure is summarized in systematic algorithms and provides an automated design environment. The procedure has been tested for various line conditions to verify the algorithms. The result shows that the proposed method successfully designs equalizers to within a 2.4% error. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Prototyping of an All-pMOS-Based Cross-Coupled Voltage Multiplier in Single-Well CMOS Technology for Energy Harvesting Utilizing a Gastric Acid Battery
Electronics 2019, 8(7), 804; https://doi.org/10.3390/electronics8070804 - 18 Jul 2019
Cited by 2 | Viewed by 1463
Abstract
A gastric acid battery and its charge storage in a capacitor are a simple and safe method to provide a power source to an ingestible device. For that method, the electromotive force of the battery should be boosted for storing a large amount [...] Read more.
A gastric acid battery and its charge storage in a capacitor are a simple and safe method to provide a power source to an ingestible device. For that method, the electromotive force of the battery should be boosted for storing a large amount of energy. In this study, we have proposed an all-p-channel metal-oxide semiconductor (pMOS)-based cross-coupled voltage multiplier (CCVM) utilizing single-well CMOS technology to achieve a voltage boosting higher than from a conventional complementary MOS (CMOS) CCVM. We prototyped a custom integrated circuit (IC) implemented with the above CCVMs and a ring oscillator as a clock source. The characterization experiment demonstrated that our proposed pMOS-based CCVM can boost the input voltage higher because it avoids the body effect problem resulting from an n-channel MOS transistor. This circuit was also demonstrated to significantly reduce the circuit area on the IC, which is advantageous as it reduces the chip size or provides an area for other functional circuits. This simple circuit structure based on mature and low-cost technologies matches well with disposal applications such as an ingestible device. We believe that this pMOS-based CCVM has the potential to become a useful energy harvesting circuit for ingestible devices. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
Novel Stochastic Computing for Energy-Efficient Image Processors
Electronics 2019, 8(6), 720; https://doi.org/10.3390/electronics8060720 - 25 Jun 2019
Cited by 8 | Viewed by 1797
Abstract
Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, [...] Read more.
Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, we propose an efficient yet simple stochastic computation technique for multipliers and adders by exchanging the wires used for their operation. The results demonstrate that the proposed design reduces the relative error in computation compared with the conventional designs and has smaller area compared to conventional designs. Then, a new energy-efficient and high-performance stochastic adder with acceptable error metrics is investigated. The proposed multiplier shows better error metrics than other existing stochastic multipliers, and significantly improves area utilization and power consumption compared to the exact binary multiplier. Finally, we apply the proposed stochastic architecture to an edge detection algorithm and achieve a significant reduction in area utilization (64%) and power consumption (96%). It is therefore demonstrated that the proposed stochastic architecture is suitable for energy-efficient hardware designs. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Article
A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs
Electronics 2019, 8(5), 589; https://doi.org/10.3390/electronics8050589 - 27 May 2019
Cited by 2 | Viewed by 1647
Abstract
A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual [...] Read more.
A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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