Special Issue "Energy Efficient Circuit Design Techniques for Low Power Systems"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 30 April 2020.

Special Issue Editor

Guest Editor
Dr. Inhee Lee

Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109, USA
Website | E-Mail
Interests: miniature sensor system development; low power & energy efficient analog/mixed-signal/digital circuit design; adaptive circuit design to tolerate environment and process variation; energy harvesting circuit; power/battery management circuit; sensor/sensor interface; voltage/current/timing reference

Special Issue Information

Dear Colleagues,

Low-power systems have become attractive solutions in a variety of applications, such as biomedical, security, energy exploration, infrastructure, and internet-of-things. Low power consumption enables extension of system lifetime and also reduces the total system size by using smaller energy storage devices (battery or supercapacitor). One basic technique to reduce the average power consumption is “duty cycle” switching the operation between long ultra-low-power sleep mode and short high-performance mode. Based on this method, advanced systems have recently been developed by suppressing power consumption lower in sleep mode and improving energy efficiency of circuit operation in active mode. Also, circuits for energy harvesting, power conversion, and energy storage management are critical to extend the system lifetime and run load circuits more energy efficiently with the minimum margin.

Topics in this Special Issue include (but are not limited to):

  • Analog or digital circuit design techniques to enable low-power systems;
  • Ultra-low-power circuit designs for standby-mode operation;
  • Energy-efficient circuit designs for active-mode operation;
  • Circuit designs for energy harvesting and power conversion;
  • Smart management circuits or systems for energy storage devices;

Dr. Inhee Lee
Guest Editor

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

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Keywords

  • energy efficient
  • low power
  • low energy
  • adaptive
  • energy harvesting
  • power management
  • sensor
  • sensor interface

Published Papers (3 papers)

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Research

Open AccessArticle
Prototyping of an All-pMOS-Based Cross-Coupled Voltage Multiplier in Single-Well CMOS Technology for Energy Harvesting Utilizing a Gastric Acid Battery
Electronics 2019, 8(7), 804; https://doi.org/10.3390/electronics8070804
Received: 1 June 2019 / Revised: 10 July 2019 / Accepted: 13 July 2019 / Published: 18 July 2019
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Abstract
A gastric acid battery and its charge storage in a capacitor are a simple and safe method to provide a power source to an ingestible device. For that method, the electromotive force of the battery should be boosted for storing a large amount [...] Read more.
A gastric acid battery and its charge storage in a capacitor are a simple and safe method to provide a power source to an ingestible device. For that method, the electromotive force of the battery should be boosted for storing a large amount of energy. In this study, we have proposed an all-p-channel metal-oxide semiconductor (pMOS)-based cross-coupled voltage multiplier (CCVM) utilizing single-well CMOS technology to achieve a voltage boosting higher than from a conventional complementary MOS (CMOS) CCVM. We prototyped a custom integrated circuit (IC) implemented with the above CCVMs and a ring oscillator as a clock source. The characterization experiment demonstrated that our proposed pMOS-based CCVM can boost the input voltage higher because it avoids the body effect problem resulting from an n-channel MOS transistor. This circuit was also demonstrated to significantly reduce the circuit area on the IC, which is advantageous as it reduces the chip size or provides an area for other functional circuits. This simple circuit structure based on mature and low-cost technologies matches well with disposal applications such as an ingestible device. We believe that this pMOS-based CCVM has the potential to become a useful energy harvesting circuit for ingestible devices. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Open AccessArticle
Novel Stochastic Computing for Energy-Efficient Image Processors
Electronics 2019, 8(6), 720; https://doi.org/10.3390/electronics8060720
Received: 21 May 2019 / Revised: 17 June 2019 / Accepted: 21 June 2019 / Published: 25 June 2019
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Abstract
Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, [...] Read more.
Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, we propose an efficient yet simple stochastic computation technique for multipliers and adders by exchanging the wires used for their operation. The results demonstrate that the proposed design reduces the relative error in computation compared with the conventional designs and has smaller area compared to conventional designs. Then, a new energy-efficient and high-performance stochastic adder with acceptable error metrics is investigated. The proposed multiplier shows better error metrics than other existing stochastic multipliers, and significantly improves area utilization and power consumption compared to the exact binary multiplier. Finally, we apply the proposed stochastic architecture to an edge detection algorithm and achieve a significant reduction in area utilization (64%) and power consumption (96%). It is therefore demonstrated that the proposed stochastic architecture is suitable for energy-efficient hardware designs. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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Open AccessArticle
A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs
Electronics 2019, 8(5), 589; https://doi.org/10.3390/electronics8050589
Received: 9 April 2019 / Revised: 20 May 2019 / Accepted: 23 May 2019 / Published: 27 May 2019
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Abstract
A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual [...] Read more.
A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation. Full article
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
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