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Article

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

1
Electrical, Electronic and Information Engineering Department “Guglielmo Marconi”, University of Bologna, Viale Risorgimento 2, 40123 Bologna, Italy
2
Advanced Research Center on Electronic Systems “Ercole De Castro”, University of Bologna, 40123 Bologna, Italy
3
STMicroelectronics, 20864 Agrate Brianza e Cornaredo, Italy
*
Author to whom correspondence should be addressed.
Academic Editor: Inhee Lee
Electronics 2021, 10(7), 780; https://doi.org/10.3390/electronics10070780
Received: 28 February 2021 / Revised: 20 March 2021 / Accepted: 22 March 2021 / Published: 25 March 2021
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups. View Full-Text
Keywords: clock and data recovery (CDR); Internet of things (IoT); nanowatt data receiver; ultra-low-power; wake-up receiver (WuRx) clock and data recovery (CDR); Internet of things (IoT); nanowatt data receiver; ultra-low-power; wake-up receiver (WuRx)
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MDPI and ACS Style

D’Addato, M.; Elgani, A.M.; Perilli, L.; Franchi Scarselli, E.; Gnudi, A.; Canegallo, R.; Ricotti, G. A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers. Electronics 2021, 10, 780. https://doi.org/10.3390/electronics10070780

AMA Style

D’Addato M, Elgani AM, Perilli L, Franchi Scarselli E, Gnudi A, Canegallo R, Ricotti G. A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers. Electronics. 2021; 10(7):780. https://doi.org/10.3390/electronics10070780

Chicago/Turabian Style

D’Addato, Matteo, Alessia M. Elgani, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, and Giulio Ricotti. 2021. "A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers" Electronics 10, no. 7: 780. https://doi.org/10.3390/electronics10070780

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