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Open AccessArticle

A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs

Ocean Collage, Zhejiang University, Zhejiang 316021, China
Author to whom correspondence should be addressed.
Electronics 2019, 8(5), 589;
Received: 9 April 2019 / Revised: 20 May 2019 / Accepted: 23 May 2019 / Published: 27 May 2019
(This article belongs to the Special Issue Energy Efficient Circuit Design Techniques for Low Power Systems)
A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation. View Full-Text
Keywords: dual-modulus prescaler; high-speed; low-power; E-TSPC DFF dual-modulus prescaler; high-speed; low-power; E-TSPC DFF
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Shen, T.; Liu, J.; Song, C.; Xu, Z. A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs. Electronics 2019, 8, 589.

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