New Advances in Semiconductor Devices/Circuits

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Semiconductor Devices".

Deadline for manuscript submissions: 15 June 2025 | Viewed by 7627

Special Issue Editor


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Guest Editor
1. ATV Automatisierung Technik Voigt, Heilbronner Str.17, 01089 Dresden, Germany
2. MPI Corporation, Advanced Semiconductor Test Division, Chungho St. 155, Chupei, Hsinchu 302, Taiwan
Interests: vector network analyzer calibration; automated measurement systems; high-frequency noise; harmonic distortion; low-frequency noise; vectorial and passive load pull characterization of on-wafer SiGe and AIIIBV HBTs, CMOS; HEMTs and emerging technology devices (CNTs, graphene FETs); characterization of MMICs, particularly LNA, PA, mixers, frequency multipliers and other circuits
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Special Issue Information

Dear Colleagues,

Recent advances in SiGe- and InP-based HBT technology have enabled the realization of monolithic microwave-integrated circuits (MMICs) including, for example, LNA, power amplifiers (PAs), MMIC receiver front-end devices, oscillators, and frequency multipliers. Based on InP HBT, a MMIC PA operating at G-band and yielding a 8.9dB gain and 90mW output power was realized. SiGe and InP HBTs are among the fastest transistors available today. For example, a 130 nm SiGe HBT with a collector–emitter breakdown voltage of BVCE0 = 3.5V exhibits a maximum transit and oscillation frequency of fT/fmax = 505/720 GHz, and a 250 nm InP HBT features a frequency of fT/fmax = 380/450GHz, a minimum noise figure of (NFmin) = 1.5/2.5dB at 1/50GHz and a PAE = 35%. Extremely scaled InP HBTs with a 12.5 nm base width are able to yield a record fT = 765 GHz, with a reasonable BVCE0 = 1.65V. SiGe HBT also features a low NFmin = 0.5/1.5dB at 1/50 GHz, good cryogenic performance, excellent reliability and radiation hardness, a low dc power consumption and a high PAE.

This Special Issue welcomes research papers that describe recent advances in semiconductor devices and circuits, not only limited to InP and SiGe HBTs, but also addressing advanced CMOS and AIIIBV. The scope of this Special Issue includes, but is not limited, to the following topics:

(1) High-frequency power amplifiers, LNAs, frequency multipliers, noise sources.

(2) Frequency multipliers.

(3) THz detection.

(4) High-frequency noise in advanced semiconductor devices.

(5) Harmonic distortion, load pull, device linearization.

(6) Advanced-technology semiconductor devices.

(7) Compact modeling.

Dr. Paulius Sakalas
Guest Editor

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Keywords

  • SiGe HBTs
  • InP DHBTs
  • fT
  • fmax scaled CMOS
  • GaN HEMT
  • high frequency circuits
  • power amplifier
  • low noise amplifier
  • noise parameters
  • harmonic distortion
  • linearity
  • THz detection

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Published Papers (6 papers)

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Research

17 pages, 9213 KiB  
Article
Automated Transformer Selection for RFIC Design: Accelerating Development with a Comprehensive Database
by Jeffrey Torres-Clarke, Neda Mendoza-Calvo, Javier del Pino, Sunil Khemchandani and David Galante-Sempere
Electronics 2025, 14(3), 615; https://doi.org/10.3390/electronics14030615 - 5 Feb 2025
Viewed by 691
Abstract
The design of transformers, a key component of radio frequency integrated circuits (RFICs), is traditionally carried out through an iterative process involving extensive electromagnetic simulations. While process design kits (PDKs) offer tools based on interpolation or fitting equations to simplify parameter estimation, these [...] Read more.
The design of transformers, a key component of radio frequency integrated circuits (RFICs), is traditionally carried out through an iterative process involving extensive electromagnetic simulations. While process design kits (PDKs) offer tools based on interpolation or fitting equations to simplify parameter estimation, these tools are restricted to standard geometries, leaving designers to manually simulate and optimize custom designs. This approach is inefficient and resource intensive. This paper proposes an automated process to generate a database containing the physical and electrical parameters of a wide range of transformers. This database is part of a tool designed to efficiently identify the desired transformer. To evaluate the tool’s effectiveness in reducing the time required for design, a millimeter-wave (mm-Wave) 69.4–74.2 GHz differential low-noise amplifier (LNA) is designed using GlobalFoundries 45 nm silicon-on-insulator (SOI) technology. This circuit demonstrates a noise figure (NF) of 4.1 dB, a gain of 10.1 dB, an input third-order intercept point (IIP3) of −10.78 dBm, and a power consumption of 4.7 mW from a 0.406 V DC supply. Moreover, the simulated performance achieves these specifications within a highly compact area of 0.12 mm2. The transformer selection process for the circuit takes only a few seconds, whereas the conventional method of manual transformer design and electromagnetic simulation would require a significantly greater amount of time. Full article
(This article belongs to the Special Issue New Advances in Semiconductor Devices/Circuits)
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13 pages, 5767 KiB  
Article
Wideband ASK-OOK Data Recovery Circuit for Data Transmission in Over-Coupled Mode of SWPDT System
by Naqeeb Ullah, Adel Barakat, Haruichi Kanaya and Ramesh K. Pokharel
Electronics 2025, 14(2), 355; https://doi.org/10.3390/electronics14020355 - 17 Jan 2025
Viewed by 725
Abstract
This paper presents an efficient wideband data recovery circuit (DRC) for forward data transfer in the over-coupled mode of dynamic SWPDT systems. In the over-coupled mode, where the operating frequency varies, conventional DRCs often become ineffective due to their limited operating frequency range. [...] Read more.
This paper presents an efficient wideband data recovery circuit (DRC) for forward data transfer in the over-coupled mode of dynamic SWPDT systems. In the over-coupled mode, where the operating frequency varies, conventional DRCs often become ineffective due to their limited operating frequency range. To address this issue, we propose a wideband DRC using amplitude shift keying (ASK) with on–off keying (OOK) modulation. The proposed circuit also eliminates the need for diodes and averaging circuits, which are typically required in traditional designs. The proposed circuit achieves data recovery by passing the OOK-modulated signal through a proposed Voltage-to-Time Converter (VTC), followed by a comparator and inverter. Implemented in 180 nm CMOS technology, the circuit occupies an area of 2440 μm2 and a power consumption of 52.08 μW. The circuit can operate across a wide range of carrier frequencies. It was tested and validated with OOK-modulated signals at 5 MHz, 50 MHz, and 150 MHz, confirming its versatility and robustness. The prototype circuit enables wireless data transmission in critically coupled, weakly coupled, and over-coupled modes of WPT systems, achieving a 2 Mb/s data rate without requiring receiver repositioning. Full article
(This article belongs to the Special Issue New Advances in Semiconductor Devices/Circuits)
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18 pages, 8189 KiB  
Article
Design of Voltage–Current Reference Source in CMOS Technology
by Tomasz Borejko and Witold Adam Pleskacz
Electronics 2024, 13(21), 4212; https://doi.org/10.3390/electronics13214212 - 27 Oct 2024
Viewed by 1610
Abstract
A design methodology for a resistorless low-power two-in-one voltage and current reference source working in subthreshold and moderate regions is described. The presented novel universal reference voltage–current source was implemented in ten different designs for seven different CMOS technologies. Six versions of these [...] Read more.
A design methodology for a resistorless low-power two-in-one voltage and current reference source working in subthreshold and moderate regions is described. The presented novel universal reference voltage–current source was implemented in ten different designs for seven different CMOS technologies. Six versions of these designs were silicon-proven using four different CMOS technologies. The example of implementation in 130 nm technology provides a reference current of 5 µA and reference voltage of 800 mV at supply voltages ranging from 0.9 V to 2.0 V with a total current consumption of 15 µA. The proposed circuit occupies a 1200 µm2 chip area and achieves 280 and 118 ppm/°C for all process corners and temperature variation from −40 °C to 125 °C. The power supply rejection ratio of output IREF without any filtering capacitor at 100 Hz and 10 MHz is 128 dB and 100 dB, respectively. The equivalent output current noise in the bandwidth from 1 Hz to 10 MHz reaches 9.1 nARMS. Full article
(This article belongs to the Special Issue New Advances in Semiconductor Devices/Circuits)
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23 pages, 21723 KiB  
Article
Dual-Band Low-Noise Amplifier for GNSS Applications
by Daniel Pietron, Tomasz Borejko and Witold Adam Pleskacz
Electronics 2024, 13(20), 4130; https://doi.org/10.3390/electronics13204130 - 21 Oct 2024
Viewed by 1579
Abstract
A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to [...] Read more.
A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively. Full article
(This article belongs to the Special Issue New Advances in Semiconductor Devices/Circuits)
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10 pages, 3422 KiB  
Article
High Quality Factor Miniaturized CMOS Transmission Lines Using Cascaded T-Networks for 60 GHz Millimeter Wave Applications
by Adel Barakat and Ramesh K. Pokharel
Electronics 2024, 13(18), 3748; https://doi.org/10.3390/electronics13183748 - 20 Sep 2024
Viewed by 1021
Abstract
This work presents an on-chip 60 GHz lumped element transmission line (TL) using cascaded T-networks with a high Quality factor. Each T-network consists of a series inductance with a shunt capacitance at its center. We have derived the design equations for this TL [...] Read more.
This work presents an on-chip 60 GHz lumped element transmission line (TL) using cascaded T-networks with a high Quality factor. Each T-network consists of a series inductance with a shunt capacitance at its center. We have derived the design equations for this TL configuration and proved that a TL whose electrical length ≥ 60° achieves additional miniaturization when implemented with three or more cascaded T-networks. The inductance is implemented using a straight wire model with no ground below it, while the capacitance is implemented using a parallel plate model with a grounding pedestal. Both configurations guarantee maximum inductance per unit length and capacitance per unit area to further improve the miniaturization level. A quarter wavelength TL with three cascaded T-networks is fabricated as proof of concept. The measured and simulated results of the fabricated TL have good agreement, and the measured quality factor is 17 at 60 GHz. Full article
(This article belongs to the Special Issue New Advances in Semiconductor Devices/Circuits)
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15 pages, 7408 KiB  
Article
Schottky Barrier Formation Mechanism and Thermal Stability in Au-Free Cu/Metal–Silicide Contacts to GaN-Cap/AlGaN/AlN-Spacer/GaN-on-Si Heterostructure
by Marek Wzorek, Marek Ekielski, Krzysztof Piskorski, Jarosław Tarenko, Michał A. Borysiewicz, Ernest Brzozowski and Andrzej Taube
Electronics 2024, 13(17), 3429; https://doi.org/10.3390/electronics13173429 - 29 Aug 2024
Viewed by 1281
Abstract
In this study, metal–silicide-based contacts to GaN-cap/AlGaN/AlN-spacer/GaN-on-Si heterostructure were investigated. Planar Schottky diodes with Cu-covered anodes comprising silicide layers of various metal–silicon (M–Si) compositions were fabricated and characterized in terms of their electrical parameters and thermal stability. The investigated contacts included Ti–Si, Ta–Si, [...] Read more.
In this study, metal–silicide-based contacts to GaN-cap/AlGaN/AlN-spacer/GaN-on-Si heterostructure were investigated. Planar Schottky diodes with Cu-covered anodes comprising silicide layers of various metal–silicon (M–Si) compositions were fabricated and characterized in terms of their electrical parameters and thermal stability. The investigated contacts included Ti–Si, Ta–Si, Co–Si, Ni–Si, Pd–Si, Ir–Si, and Pt–Si layers. Reference diodes with pure Cu or Au/Ni anodes were also examined. To test the thermal stability, selected devices were subjected to subsequent annealing steps in vacuum at incremental temperatures up to 900 °C. The Cu/M–Si anodes showed significantly better thermal stability than the single-layer Cu contact, and in most cases exceeded the stability of the reference Au/Ni contact. The work functions of the sputtered thin layers were determined to support the discussion of the formation mechanism of the Schottky barrier. It was concluded that the barrier heights were dependent on the M–Si composition, although they were not dependent on the work function of the layers. An extended, unified Schottky barrier formation model served as the basis for explaining the complex electrical behavior of the devices under investigation. Full article
(This article belongs to the Special Issue New Advances in Semiconductor Devices/Circuits)
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