Special Issue "Energy Aware HPC Revisited: AI Concerns, Architectures and Optimization Strategies"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 30 September 2022 | Viewed by 6060

Special Issue Editors

Prof. Dr. Carlos Valderrama
E-Mail Website
Guest Editor
Electronics and Microelectronics, Polytechnic Faculty, University of Mons, 7000 Mons, Belgium
Interests: reconfigurable; embedded; edge computing; HPC; EDA/ESL
Prof. Dr. Fan YANG
E-Mail Website
Guest Editor
ImViA Laboratory, University of Burgundy, 21078 Dijon, France
Interests: artificial intelligence; computer vision; approximate computing; affective computing; embedded systems
Asst. Prof. Dr. Khaled Ben Khalifa
E-Mail Website
Guest Editor
Department of Electronics Engineering, Higher Institute of Applied Sciences and Technology of Sousse, Sousse 4003, Tunisia
Interests: artificial neural networks; real time embedded systems; HPC; reconfigurable architecture
Assoc. Prof. Dr. Marcelo A. C. Fernandes
E-Mail Website
Guest Editor
Department of Computer and Automation Engineering, Federal University of Rio Grande do Norte, Natal 59078-970, Brazil
Interests: artificial intelligence; reconfigurable computing; hardware designer
Prof. Dr. Chokri Souani
E-Mail Website
Guest Editor
Institut Supérieur des Sciences Appliquées et de Technologie, Université de Sousse, Sousse 4054, Tunisia
Interests: embedded system; software defined everything; embedded vision; intelligence; electronic applications
Dr. Eva Dokladalova
E-Mail Website
Guest Editor
LIGM Gaspard-Monge Computer Science Laboratory, UMR 8049, ESIEE Paris, University Gustave Eiffel, 44340 Bouguenais, France
Interests: computer vision; artificial intelligence; sensing; embedded systems; parallel algorithms
Dr. Arvind R Yadav
E-Mail Website
Guest Editor
Department of Electronics and Communication Engineering, Parul Institute of Engineering and Technology, Parul University, Vadodara, India
Interests: computer vision; image processing; artificial intelligence; reconfigurable; embedded system

Special Issue Information

Dear Colleagues,

This Special Issue invites original research papers that report on the state-of-the-art and recent advancements in energy-aware high-performance computing (HPC) and optimization strategies in applications supporting artificial intelligence (AI).

Energy efficiency is one of the main concerns of today’s computer systems, particularly in HPC, where energy consumption has a significant impact on both operational and environmental costs. There are several approaches to this problem at different levels, such as developing more efficient software, hardware, and architectures, as well as improving power management software or even the associated cooling system.

Although the only measures that were considered in the past were flops, with the advent of artificial intelligence and big data, the HPC community has realized that this form of design contributes to supercomputers, which consume a lot of electricity. Indeed, the growing demand on power processing shows that high energy consumption HPC systems need to evolve, and the attempt to achieve energy-efficient HPC architectures has increased in recent years.

These features expose the tradeoffs between performance and power consumption, leaving room for the production of more energy-efficient algorithms and operating systems. Indeed, adequate computation is an emerging paradigm, in which the accuracy of computational results can be achieved, for example, for energy savings and performance improvement at run time. This concept explores how IT systems (from embedded devices to HPC) can be improved to be "more energy-efficient, faster, and less complex", by relaxing the requirement that they should be exactly correct. For example, several recent approaches attempt to design CNN models and hardware architectures to jointly maximize accuracy throughput, while minimizing energy and costs. Approaches like this are sometimes based on an approximate calculation of the aforementioned AI algorithms, by reducing the precision of the arithmetic operation, by reducing the number of operands or by building adequate functional units. 

This Special Issue is focused on sharing and showing new proposals regarding energy aware HPC optimization strategies in the context of novel applications supporting AI. Prospective authors are invited to submit high-quality original contributions and reviews to this Special Issue. Potential topics include, but are not limited to, the following:

  • Cost efficient HPC architectures, topologies, and strategies
  • Energy aware HPC algorithm and architecture adequacy
  • Approximate computing
  • Low-power reconfigurable accelerators for heterogeneous HPC
  • Configurable, custom, optimized CNNs topologies for energy aware HPC

Prof. Dr. Carlos Valderrama
Prof. Dr. Fan YANG
Asst. Prof. Dr. Khaled Ben Khalifa
Assoc. Prof. Dr. Marcelo A. C. Fernandes
Prof. Dr. Chokri Souani
Dr. Eva Dokladalova
Dr. Arvind R Yadav
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • high-performance computing
  • artificial intelligence
  • green computing
  • low-power hardware accelerators

Published Papers (4 papers)

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Research

Article
A Minimally Intrusive Approach for Automatic Assessment of Parallel Performance Scalability of Shared-Memory HPC Applications
Electronics 2022, 11(5), 689; https://doi.org/10.3390/electronics11050689 - 23 Feb 2022
Viewed by 389
Abstract
High-performance computing systems have become increasingly dynamic, complex, and unpredictable. To help build software that uses full-system capabilities, performance measurement and analysis tools exploit extensive execution analysis focusing on single-run results. Despite being effective in identifying performance hotspots and bottlenecks, these tools are [...] Read more.
High-performance computing systems have become increasingly dynamic, complex, and unpredictable. To help build software that uses full-system capabilities, performance measurement and analysis tools exploit extensive execution analysis focusing on single-run results. Despite being effective in identifying performance hotspots and bottlenecks, these tools are not sufficiently suitable to evaluate the overall scalability trends of parallel applications. Either they lack the support for combining data from multiple runs or collect excessive data, causing unnecessary overhead. In this work, we present a tool for automatically measuring and comparing several executions of a parallel application according to various scenarios characterized by the input arrangements, the number of threads, number of cores, and frequencies. Unlike other existing performance analysis tools, the proposed work covers some gaps in specialized features necessary to better understand computational resources scalability trends across configurations. In order to improve scalability analysis and productivity over the vast spectrum of possible configurations, the proposed tool features automatic instrumentation, direct mapping of parallel regions, accuracy-preserving data reductions, and ease of use. As it aims at accurately understanding scalability trends of parallel applications, detailed single-run performance analyses show minimal intrusion (less than 1% overhead). Full article
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Article
Performance Analysis of a Dynamic Virtual Machine Management Method Based on the Power-Aware Integral Estimation
Electronics 2021, 10(21), 2581; https://doi.org/10.3390/electronics10212581 - 22 Oct 2021
Viewed by 314
Abstract
The latest cloud resource management research has revealed that virtual machine (VM) consolidation allows for effectively managing the physical resources of cloud data centers. However, a tremendous waste of power and physical resources has been pointed as one of the research challenges related [...] Read more.
The latest cloud resource management research has revealed that virtual machine (VM) consolidation allows for effectively managing the physical resources of cloud data centers. However, a tremendous waste of power and physical resources has been pointed as one of the research challenges related to the development of new methods for VM management in a cloud data center in order to deliver a wide range of IT services to clients effectively. This paper investigates a problem of power-aware VM consolidation under dynamic workloads, uncertainty, and a changing number of VMs. For this purpose, the authors propose a dynamic VM management method based on a beam search that takes into account four types of resources (CPU, memory, network throughput, and storage throughput) and six quality metrics. Optimal beam search algorithm parameters for the defined problem are determined using a new power-aware integral estimation method. The SLA violation minimization allows significant improvement of SLA quality metrics, accompanied by the decreased number of VM migrations and slight deterioration in the power consumption. The proposed method is evaluated using common widespread hardware configurations and Bitbrains workload traces. The experiments show that the proposed approach can ensure the efficient use of cloud resources in terms of SLA violation and the number of VM migrations. Full article
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Article
Bi-Objective Workflow Scheduling on Heterogeneous Computing Systems Using a Memetic Algorithm
Electronics 2021, 10(2), 209; https://doi.org/10.3390/electronics10020209 - 18 Jan 2021
Cited by 2 | Viewed by 668
Abstract
Due to the high power bills and the negative environmental impacts, workflow scheduling with energy consciousness has been an emerging need for modern heterogeneous computing systems. A number of approaches have been developed to find suboptimal schedules through heuristics by means of slack [...] Read more.
Due to the high power bills and the negative environmental impacts, workflow scheduling with energy consciousness has been an emerging need for modern heterogeneous computing systems. A number of approaches have been developed to find suboptimal schedules through heuristics by means of slack reclamation or trade-off functions. In this article, a memetic algorithm for energy-efficient workflow scheduling is proposed for a quality-guaranteed solution with high runtime efficiency. The basic idea is to retain the advantages of population-based, heuristic-based, and local search methods while avoiding their drawbacks. Specifically, the proposed algorithm incorporates an improved non-dominated sorting genetic algorithm (NSGA-II) to explore potential task priorities and allocates tasks to processors by an earliest finish time (EFT)-based heuristic to provide a time-efficient candidate. Then, a local search method integrated with a pruning technique is launched with a low possibility, to exploit the feasible region indicated by the candidate schedule. Experimental results on workflows from both randomly-generated and real-world applications suggest that the proposed algorithm achieves bi-objective optimization, improving makespan, and energy saving by 4.9% and 24.3%, respectively. Meanwhile, it has a low time complexity compared to the similar work HECS. Full article
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Article
Rotation Invariant Networks for Image Classification for HPC and Embedded Systems
Electronics 2021, 10(2), 139; https://doi.org/10.3390/electronics10020139 - 10 Jan 2021
Cited by 3 | Viewed by 4083
Abstract
Convolutional Neural Network (CNNs) models’ size reduction has recently gained interest due to several advantages: energy cost reduction, embedded devices, and multi-core interfaces. One possible way to achieve model reduction is the usage of Rotation-invariant Convolutional Neural Networks because of the possibility of [...] Read more.
Convolutional Neural Network (CNNs) models’ size reduction has recently gained interest due to several advantages: energy cost reduction, embedded devices, and multi-core interfaces. One possible way to achieve model reduction is the usage of Rotation-invariant Convolutional Neural Networks because of the possibility of avoiding data augmentation techniques. In this work, we present the next step to obtain a general solution to endowing CNN architectures with the capability of classifying rotated objects and predicting the rotation angle without data-augmentation techniques. The principle consists of the concatenation of a representation mapping transforming rotation to translation and a shared weights predictor. This solution has the advantage of admitting different combinations of various basic, existing blocks. We present results obtained using a Gabor-filter bank and a ResNet feature backbone compared to previous other solutions. We also present the possibility to select between parallelizing the network in several threads for energy-aware High Performance Computing (HPC) applications or reducing the memory footprint for embedded systems. We obtain a competitive error rate on classifying rotated MNIST and outperform existing state-of-the-art results on CIFAR-10 when trained on up-right examples and validated on random orientations. Full article
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