Special Issue "New CMOS Devices and Their Applications"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics and Optoelectronics".

Deadline for manuscript submissions: 30 June 2020.

Special Issue Editor

Dr. Myounggon Kang
E-Mail Website
Guest Editor
Department of Electronics Engineering, Korea National University of Transportation, Chungju 27469, Korea
Interests: advanced CMOS devices; volatile/nonvolatile memory devices; device modeling and simulation; circuit design; reliability analysis (HCI/BTI/radiation)

Special Issue Information

Dear Colleagues,

The next decade promises to be full of challenges and opportunities for next-generation CMOS devices. The surge of Big Data, Internet of Things, Artificial Intelligence, and 5G mobile networks will not only require an unprecedented amount of storage capacity, but also demand CMOS technologies be capable of fulfilling quite a variety of requirements related to cost, performance, and reliability. To take full advantage of the new market needs and keep their leading role in the semiconductor device area, the sub-10-nm multi-gate MOSFET, 3D stacked NAND Flash Memory, DRAM, and Emerging memory technologies will have to keep evolving, exploiting new integration schemes, new materials, and new working conditions able to prolong their historical scaling trends.  This Special Issue of Electronics aims at presenting an in-depth discussion of the new CMOS devices and technologies that will have an impact on the electronics world in the next decade. Papers are solicited on next-generation CMOS devices, 3D NAND Flash Memory, neuromorphic devices, and any other technology able to take up the challenges of the next ten years. Topics of interest include, but are not limited to: 

  • Sub-10-nm multi-gate MOSFET (FinFET, nanowire, nanoplate, etc.);
  • Next-generation CMOS devices (tunnel FETs, negative capacitance FETs, etc.);
  • Characterization of 3D stacked NAND Flash Memory and DRAM;
  • Emerging memories and neuromorphic devices;
  • Applications of new CMOS devices;
  • Design, modeling, simulation, and reliability of new devices/circuits;
  • Devices and circuits for high-frequency applications.

Dr. Myounggon Kang
Guest Editor

Manuscript Submission Information

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Keywords

  • Sub-10-nm multi-gate MOSFET (FinFET, nanowire, nanoplate, etc.)
  • Next-generation CMOS devices (tunnel FETs, negative capacitance FETs, etc.)
  • Characterization of 3D stacked NAND Flash Memory and DRAM
  • Emerging memories and neuromorphic devices
  • Applications of new CMOS devices
  • Design, modeling, simulation, and reliability of new devices/circuits
  • Devices and circuits for high-frequency applications.

Published Papers (4 papers)

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Research

Open AccessArticle
Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications
Electronics 2019, 8(10), 1138; https://doi.org/10.3390/electronics8101138 - 09 Oct 2019
Abstract
In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching [...] Read more.
In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications)
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Open AccessArticle
Investigation on Temperature Dependency of Recessed-Channel Reconfigurable Field-Effect Transistor
Electronics 2019, 8(10), 1124; https://doi.org/10.3390/electronics8101124 - 06 Oct 2019
Abstract
Current-voltage (I-V) characteristics of a recessed-channel reconfigurable field-effect transistor (RC-RFET) is discussed, herein, depending on the variation of temperature (T) to understand the operation mechanisms, in depth. Assuming that RC-RFET can be simply modeled as a channel resistance ( [...] Read more.
Current-voltage (I-V) characteristics of a recessed-channel reconfigurable field-effect transistor (RC-RFET) is discussed, herein, depending on the variation of temperature (T) to understand the operation mechanisms, in depth. Assuming that RC-RFET can be simply modeled as a channel resistance (RCH) and a Schottky contact resistance (RSC) connected in series, the validity has been examined by a technology computer-aided design (TCAD) simulation with different Schottky barrier heights (SBHs) and carrier mobilities (μ). As a result, it was clearly determined that the drain current (ID) of RC-RFET is dominated by the bigger component, since RCH and RSC have an opposite correlation with T. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications)
Open AccessArticle
Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel
Electronics 2019, 8(9), 988; https://doi.org/10.3390/electronics8090988 - 04 Sep 2019
Abstract
Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and [...] Read more.
Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications)
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Open AccessArticle
Development of an Advanced TDDB Analysis Model for Temperature Dependency
Electronics 2019, 8(9), 942; https://doi.org/10.3390/electronics8090942 - 27 Aug 2019
Abstract
This paper proposes a hybrid model to describe the temperature dependence of the time-dependent dielectric breakdown (TDDB) phenomenon. TDDB can be expressed in terms of two well-known representative degradation mechanisms: The thermo-chemical (TC) mechanism and the anode hole injection (AHI) mechanism. A single [...] Read more.
This paper proposes a hybrid model to describe the temperature dependence of the time-dependent dielectric breakdown (TDDB) phenomenon. TDDB can be expressed in terms of two well-known representative degradation mechanisms: The thermo-chemical (TC) mechanism and the anode hole injection (AHI) mechanism. A single model does not account for the measured lifetime, due to TDDB under different temperature conditions. Hence, in the proposed model, two different degradation mechanisms are considered simultaneously in an appropriate manner to describe the trap generation in the dielectric layer. The proposed model can be used to simulate the generation of the percolation path in a dielectric layer, and it is in agreement with the measured lifetime because of TDDB at different temperatures. Therefore, the proposed model can be used to predict guarantee time or initial failure detection, using the accelerated life test for industrial purposes. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications)
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