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Electronics, Volume 5, Issue 1 (March 2016)

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Open AccessFeature PaperReview
Graphene and Two-Dimensional Materials for Optoelectronic Applications
Electronics 2016, 5(1), 13; https://doi.org/10.3390/electronics5010013
Received: 21 January 2016 / Revised: 28 February 2016 / Accepted: 4 March 2016 / Published: 21 March 2016
Cited by 24 | Viewed by 3864 | PDF Full-text (2388 KB) | HTML Full-text | XML Full-text
Abstract
This article reviews optoelectronic devices based on graphene and related two-dimensional (2D) materials. The review includes basic considerations of process technology, including demonstrations of 2D heterostructure growth, and comments on the scalability and manufacturability of the growth methods. We then assess the potential [...] Read more.
This article reviews optoelectronic devices based on graphene and related two-dimensional (2D) materials. The review includes basic considerations of process technology, including demonstrations of 2D heterostructure growth, and comments on the scalability and manufacturability of the growth methods. We then assess the potential of graphene-based transparent conducting electrodes. A major part of the review describes photodetectors based on lateral graphene p-n junctions and Schottky diodes. Finally, the progress in vertical devices made from 2D/3D heterojunctions, as well as all-2D heterostructures is discussed. Full article
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Open AccessArticle
High Electron Confinement under High Electric Field in RF GaN-on-Silicon HEMTs
Electronics 2016, 5(1), 12; https://doi.org/10.3390/electronics5010012
Received: 28 December 2015 / Revised: 11 March 2016 / Accepted: 14 March 2016 / Published: 18 March 2016
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Abstract
We report on AlN/GaN high electron mobility transistors grown on silicon substrate with highly optimized electron confinement under a high electric field. The fabricated short devices (sub-10-nm barrier thickness with a gate length of 120 nm) using gate-to-drain distances below 2 µm deliver [...] Read more.
We report on AlN/GaN high electron mobility transistors grown on silicon substrate with highly optimized electron confinement under a high electric field. The fabricated short devices (sub-10-nm barrier thickness with a gate length of 120 nm) using gate-to-drain distances below 2 µm deliver a unique breakdown field close to 100 V/µm while offering high frequency performance. The low leakage current well below 1 µA/mm is achieved without using any gate dielectrics which typically degrade both the frequency performance and the device reliability. This achievement is mainly attributed to the optimization of material design and processing quality and paves the way for millimeter-wave devices operating at drain biases above 40 V, which would be only limited by the thermal dissipation. Full article
(This article belongs to the Special Issue Microwave/ Millimeter-Wave Devices and MMICs)
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Open AccessArticle
Effect of Edge Roughness on Static Characteristics of Graphene Nanoribbon Field Effect Transistor
Electronics 2016, 5(1), 11; https://doi.org/10.3390/electronics5010011
Received: 13 September 2015 / Revised: 8 March 2016 / Accepted: 14 March 2016 / Published: 18 March 2016
Cited by 8 | Viewed by 2559 | PDF Full-text (3625 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, we present a physics-based analytical model of GNR FET, which allows for the evaluation of GNR FET performance including the effects of line-edge roughness as its practical specific non-ideality. The line-edge roughness is modeled in edge-enhanced band-to-band-tunneling and localization regimes, [...] Read more.
In this paper, we present a physics-based analytical model of GNR FET, which allows for the evaluation of GNR FET performance including the effects of line-edge roughness as its practical specific non-ideality. The line-edge roughness is modeled in edge-enhanced band-to-band-tunneling and localization regimes, and then verified for various roughness amplitudes. Corresponding to these two regimes, the off-current is initially increased, then decreased; while, on the other hand, the on-current is continuously decreased by increasing the roughness amplitude. Full article
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Open AccessArticle
FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems
Electronics 2016, 5(1), 10; https://doi.org/10.3390/electronics5010010
Received: 21 December 2015 / Revised: 23 February 2016 / Accepted: 4 March 2016 / Published: 11 March 2016
Cited by 10 | Viewed by 3220 | PDF Full-text (5631 KB) | HTML Full-text | XML Full-text
Abstract
Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation [...] Read more.
Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576) resolution video streams directly coming from the camera. Full article
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Open AccessReview
Electrolytic Gated Organic Field-Effect Transistors for Application in Biosensors—A Review
Received: 10 December 2015 / Revised: 3 February 2016 / Accepted: 16 February 2016 / Published: 25 February 2016
Cited by 33 | Viewed by 4167 | PDF Full-text (8968 KB) | HTML Full-text | XML Full-text
Abstract
Electrolyte-gated organic field-effect transistors have emerged in the field of biosensors over the last five years, due to their attractive simplicity and high sensitivity to interfacial changes, both on the gate/electrolyte and semiconductor/electrolyte interfaces, where a target-specific bioreceptor can be immobilized. This article [...] Read more.
Electrolyte-gated organic field-effect transistors have emerged in the field of biosensors over the last five years, due to their attractive simplicity and high sensitivity to interfacial changes, both on the gate/electrolyte and semiconductor/electrolyte interfaces, where a target-specific bioreceptor can be immobilized. This article reviews the recent literature concerning biosensing with such transistors, gives clues to understanding the basic principles under which electrolyte-gated organic field-effect transistors work, and details the transduction mechanisms that were investigated to convert a receptor/target association into a change in drain current. Full article
(This article belongs to the Special Issue Recent Advances in Organic Bioelectronics and Sensors)
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Open AccessArticle
FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool
Received: 10 November 2015 / Revised: 17 January 2016 / Accepted: 26 January 2016 / Published: 4 February 2016
Cited by 8 | Viewed by 3080 | PDF Full-text (3963 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA) using Xilinx System Generator (XSG) and the Nexys-4 [...] Read more.
In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA) using Xilinx System Generator (XSG) and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls. Full article
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Open AccessArticle
Effects of the Particle Size and the Solvent in Printing Inks on the Capacitance of Printed Parallel-Plate Capacitors
Received: 30 November 2015 / Revised: 18 January 2016 / Accepted: 22 January 2016 / Published: 2 February 2016
Viewed by 1788 | PDF Full-text (1209 KB) | HTML Full-text | XML Full-text
Abstract
Parallel-plate capacitors were fabricated using a printed multi-layer structure in order to determine the effects of particle size and solvent on the capacitance. The conductive-dielectric-conductive layers were sequentially spun using commercial inks and by intermediate drying with the aid of a masking polymeric [...] Read more.
Parallel-plate capacitors were fabricated using a printed multi-layer structure in order to determine the effects of particle size and solvent on the capacitance. The conductive-dielectric-conductive layers were sequentially spun using commercial inks and by intermediate drying with the aid of a masking polymeric layer. Both optical and scanning electron microscopy were used to characterize the morphology of the printed layers. The measured capacitance was larger than the theoretically calculated value when ink with small-sized particles was used as the top plate. Furthermore, the use of a solvent whose polarity was similar to that of the underlying dielectric layer enhanced the penetration and resulted in an increase in capacitance. The functional resistance-capacitance low-pass filter was implemented using printed resistors and capacitors, a process that may be scalable in the future. Full article
(This article belongs to the Special Issue Printed Electronics)
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Open AccessEditorial
Acknowledgement to Reviewers of Electronics in 2015
Received: 21 January 2016 / Accepted: 21 January 2016 / Published: 22 January 2016
Viewed by 1199 | PDF Full-text (144 KB) | HTML Full-text | XML Full-text
Abstract
The editors of Electronics would like to express their sincere gratitude to the following reviewers for assessing manuscripts in 2015. [...] Full article
Open AccessArticle
Hardware Activation by Means of PUFs and Elliptic Curve Cryptography in Field-Programmable Devices
Received: 17 July 2015 / Revised: 21 December 2015 / Accepted: 8 January 2016 / Published: 18 January 2016
Cited by 6 | Viewed by 1931 | PDF Full-text (551 KB) | HTML Full-text | XML Full-text
Abstract
Reusable design using IP cores requires of efficient methods for protecting the Intellectual Property of the designer and the corresponding license agreements. In this work, a new protection procedure establishing an activation protocol in a similar way to the activation process in the [...] Read more.
Reusable design using IP cores requires of efficient methods for protecting the Intellectual Property of the designer and the corresponding license agreements. In this work, a new protection procedure establishing an activation protocol in a similar way to the activation process in the software world is presented. The procedure, named SEHAS (Secure Hardware Activation System) allows the distribution of cores in either Blocked (not functioning) or Demo (functioning with limited features) modes, while ensuring the license agreements by identifying not only the IP core but also the implementation device, using Physically Unclonable Functions (PUF). Moreover, SEHAS secures the exchange of information between the core and the core vendor using an Elliptic Curve Cryptosystem (ECC). This secure channel allows the IP core vendor to send a unique Activation Code to the core in order to switch it to the Activated Mode, thus enabling all its features. Full article
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Open AccessArticle
Acoustic Wake-Up Receivers for Home Automation Control Applications
Received: 3 September 2015 / Revised: 24 December 2015 / Accepted: 24 December 2015 / Published: 15 January 2016
Cited by 4 | Viewed by 2774 | PDF Full-text (1734 KB) | HTML Full-text | XML Full-text
Abstract
Automated home applications are to ease the use of technology and devices around the house. Most of the electronic devices, like shutters or entertainment products (Hifi, TV and even WiFi), are constantly in a standby mode, where they consume a considerable amount of [...] Read more.
Automated home applications are to ease the use of technology and devices around the house. Most of the electronic devices, like shutters or entertainment products (Hifi, TV and even WiFi), are constantly in a standby mode, where they consume a considerable amount of energy. The standby mode is necessary to react to commands triggered by the user, but the time the device spends in a standby mode is considered long. In our work, we present a receiver that is attached to home appliances that allows the devices to be activated while they are completely turned off in order to reduce the energy consumed in the standby mode. The receiver contains a low power wake-up module that reacts to an addressable acoustic 20-kHz sound signal that controls home devices that are connected to it. The acoustic wake-up signal can be sent by any kind of speaker that is available in commercial smartphones. The smartphones will operate as transmitters to the signals. Our wake-up receiver consists of two parts: a low power passive circuit connected to a wake-up chip microcontroller and an active micro-electromechanical system (MEMS) microphone that receives the acoustic signal. A duty cycle is required to reduce the power consumption of the receiver, because the signal reception occurs when the microphone is active. The current consumption was measured to be 15 μA in sleep mode and 140 μA in active mode. An average wake-up range of 10 m using a smartphone as a sender was achieved. Full article
(This article belongs to the Special Issue Home Automation Systems)
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Open AccessFeature PaperArticle
Simulation of 50-nm Gate Graphene Nanoribbon Transistors
Received: 2 November 2015 / Revised: 22 December 2015 / Accepted: 29 December 2015 / Published: 12 January 2016
Cited by 9 | Viewed by 2431 | PDF Full-text (2384 KB) | HTML Full-text | XML Full-text
Abstract
An approach to simulate the steady-state and small-signal behavior of GNR MOSFETs (graphene nanoribbon metal-semiconductor-oxide field-effect transistor) is presented. GNR material parameters and a method to account for the density of states of one-dimensional systems like GNRs are implemented in a commercial device [...] Read more.
An approach to simulate the steady-state and small-signal behavior of GNR MOSFETs (graphene nanoribbon metal-semiconductor-oxide field-effect transistor) is presented. GNR material parameters and a method to account for the density of states of one-dimensional systems like GNRs are implemented in a commercial device simulator. This modified tool is used to calculate the current-voltage characteristics as well the cutoff frequency fT and the maximum frequency of oscillation fmax of GNR MOSFETs. Exemplarily, we consider 50-nm gate GNR MOSFETs with N = 7 armchair GNR channels and examine two transistor configurations. The first configuration is a simplified MOSFET structure with a single GNR channel as usually studied by other groups. Furthermore, and for the first time in the literature, we study in detail a transistor structure with multiple parallel GNR channels and interribbon gates. It is shown that the calculated fT of GNR MOSFETs is significantly lower than that of GFETs (FET with gapless large-area graphene channel) with comparable gate length due to the mobility degradation in GNRs. On the other hand, GNR MOSFETs show much higher fmax compared to experimental GFETs due the semiconducting nature of the GNR channels and the resulting better saturation of the drain current. Finally, it is shown that the gate control in FETs with multiple parallel GNR channels is improved while the cutoff frequency is degraded compared to single-channel GNR MOSFETs due to parasitic capacitances of the interribbon gates. Full article
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Open AccessArticle
Self-Aligned Metal Electrodes in Fully Roll-to-Roll Processed Organic Transistors
Received: 30 November 2015 / Revised: 23 December 2015 / Accepted: 4 January 2016 / Published: 7 January 2016
Cited by 6 | Viewed by 2601 | PDF Full-text (3964 KB) | HTML Full-text | XML Full-text
Abstract
We demonstrate the production of organic bottom gate transistors with self-aligned electrodes, using only continuous roll-to-roll (R2R) techniques. The self-alignment allows accurate <5 µm layer-to-layer registration, which is usually a challenge in high-speed R2R environments as the standard registration methods are limited to [...] Read more.
We demonstrate the production of organic bottom gate transistors with self-aligned electrodes, using only continuous roll-to-roll (R2R) techniques. The self-alignment allows accurate <5 µm layer-to-layer registration, which is usually a challenge in high-speed R2R environments as the standard registration methods are limited to the millimeter range—or, at best, to tens of µm if online cameras and automatic web control are utilized. The improved registration enables minimizing the overlap between the source/drain electrodes and the gate electrode, which is essential for minimizing the parasitic capacitance. The complete process is a combination of several techniques, including evaporation, reverse gravure, flexography, lift-off, UV exposure and development methods—all transferred to a continuous R2R pilot line. Altogether, approximately 80 meters of devices consisting of thousands of transistors were manufactured in a roll-to-roll fashion. Finally, a cost analysis is presented in order to ascertain the main costs and to predict whether the process would be feasible for the industrial production of organic transistors. Full article
(This article belongs to the Special Issue Printed Electronics)
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Open AccessArticle
On the Stability and Electronic Structure of Transition-Metal Dichalcogenide Monolayer Alloys Mo1−xXxS2−ySey with X = W, Nb
Received: 2 November 2015 / Revised: 30 November 2015 / Accepted: 15 December 2015 / Published: 30 December 2015
Cited by 3 | Viewed by 3342 | PDF Full-text (3154 KB) | HTML Full-text | XML Full-text
Abstract
Layered transition-metal dichalcogenides have extraordinary electronic properties, which can be easily modified by various means. Here, we have investigated how the stability and electronic structure of MoS 2 monolayers is influenced by alloying, i.e., by substitution of the transition metal Mo by W [...] Read more.
Layered transition-metal dichalcogenides have extraordinary electronic properties, which can be easily modified by various means. Here, we have investigated how the stability and electronic structure of MoS 2 monolayers is influenced by alloying, i.e., by substitution of the transition metal Mo by W and Nb and of the chalcogen S by Se. While W and Se incorporate into the MoS 2 matrix homogeneously, forming solid solutions, the incorporation of Nb is energetically unstable and results in phase separation. However, all three alloying atoms change the electronic band structure significantly. For example, a very small concentration of Nb atoms introduces localized metallic states, while Mo 1 - x W x S 2 and MoS 2 - y Se y alloys exhibit spin-splitting of the valence band of strength that is in between that of the pure materials. Moreover, small, but evident spin-splitting is introduced in the conduction band due to the symmetry breaking. Therefore, transition-metal dichalcogenide alloys are interesting candidates for optoelectronic and spintronic applications. Full article
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Electronics EISSN 2079-9292 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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