Evaluation of Dynamic Response and Power Quality Performance in Type-3 Fuzzy Logic Controlled PWM Rectifiers

Abstract

In three-phase PWM rectifiers, abrupt load changes and parameter variations challenge DC-bus voltage regulation and degrade the performance of conventional controllers. To ensure robust regulation under nonlinear and time-varying conditions, this study proposes a type-3 fuzzy logic controller (T3-FLC) for DC-bus voltage regulation. The T3-FLC enhances the conventional type-1 framework by employing a three-dimensional membership structure that captures both vertical and horizontal uncertainties in the fuzzy inference process. This structure improves adaptability and stability in the face of system disturbances. The proposed controller was compared with a conventional proportional-integral (PI) controller and a type-1 fuzzy logic controller (T1-FLC) under different operating conditions: constant reference, reference tracking, load variation, regenerative operation, and grid disturbances. Under reference tracking mode, it settles within approximately 12 ms for the largest reference step, with the overshoot kept below 0.3%, whereas the T1-FLC and PI controllers require noticeably longer settling times and exhibit higher overshoot. In regenerative operation, the T3-FLC maintains tight DC-bus regulation with recovery times of 10–12 ms and an overshoot of about 2.7%, outperforming the benchmark controllers. Power quality analysis further shows that the proposed controller maintains low input-current distortion, with THD approximately 5–13%, and a near-unity power factor across all scenarios. These results confirm the T3-FLC as an effective control strategy for power converters.

1. Introduction

Conventional rectifiers, especially those based on diodes and thyristors, have been widely used in power electronics applications for many years. The basic advantages of these rectifiers include a simple structure, low cost, and high reliability. However, they have significant disadvantages, such as serious harmonic distortions in input current, low power factor (PF), and the inability to provide bidirectional power flow (BPF) [1,2,3]. Such structures have negative effects, especially on grid quality, and are insufficient in terms of harmonic current limitations and energy efficiency.

To overcome the limitations mentioned above, pulse-width modulation (PWM) rectifiers were developed, offering significant advantages over traditional rectifiers. PWM rectifiers have advantages, such as drawing sinusoidal current from the grid, maintaining input PF close to unity, and enabling regenerative operation by BPF. Furthermore, PWM rectifiers represent an attractive solution for industrial applications due to their low DC-bus voltage ripple and high dynamic performance [4,5].

The proportional-integral-derivative (PID) controller is a common choice for PWM rectifiers. Its appeal lies in its simple structure, easy implementation, and low computational cost [6,7]. Even so, when the system is nonlinear, as in PWM rectifiers with time-varying parameters and disturbances, fixed-gain PID often fails to maintain its performance across operating conditions. It works well when the system can be treated as fixed and linear, but in practice, rectifiers face parameter variations, inherent nonlinearities, and abrupt load transients. Under those conditions, PID can trigger instability, oscillations, and voltage overshoot. The issue becomes pronounced during reference-voltage changes: the controller should drive the system quickly and stably to the new operating point, yet classical PID often exhibits delayed response, long settling time, and weak disturbance rejection. The literature traces these shortcomings to limited adaptivity to changing dynamics and modest robustness to external disturbances [8].

Due to the limitations of fixed-gain PID controllers in nonlinear systems, various advanced control strategies have been investigated. The main alternatives are briefly reviewed below to position the proposed method. Within this framework, sliding-mode control provides strong robustness to modeling errors and disturbances, but it is susceptible to chattering unless higher-order or filtered designs are employed [9,10]. By contrast, backstepping offers a Lyapunov-based framework for regulating $V_{dc}$ and the synchronous d–q frame currents. However, its recursive structure increases design complexity and parameter sensitivity [11,12]. Nonlinear MPC, in turn, delivers high multivariable performance at the expense of an online optimization burden that can hinder embedded real-time implementation [13,14]. Feedback linearization simplifies controller design by canceling nonlinear terms. However, it depends on an accurate model and can lose performance under parameter uncertainty [15,16,17,18]. Passivity-based control leverages energy shaping and damping injection, while practical deployment often hinges on constructing a suitable storage function [19,20]. Although nonlinear methods can improve control performance, their complex equations, high computational load, and stringent modeling requirements often limit their practicality. Accordingly, controllers with reduced model dependence that learn from system behavior and adapt to uncertainty have become increasingly desirable, motivating more flexible, learning-based, and adaptive control solutions.

In this direction, artificial intelligence-based control methods have emerged as a strong alternative for controlling nonlinear systems. Methods such as fuzzy logic, artificial neural networks, genetic algorithms, and fuzzy-neural systems reduce dependence on the system model and adapt more effectively to changing operating conditions [21,22,23]. These methods can create appropriate control laws by learning the behavior of the system based on experience. They offer effective results, especially in systems with model uncertainty or complex dynamic structures [24]. These methods have also been widely applied in the control of PWM rectifiers. Although type-1 fuzzy logic controllers (T1-FLCs) offer low computational cost with fixed membership functions (MFs), they may not provide sufficient performance in cases of high uncertainty. Type-1-based approaches have yielded successful results in controlling three-phase PWM rectifiers [25]. However, their performance is directly related to the definition of the rules and the sensitivity of the MFs. To overcome these limitations, type-2 fuzzy logic controllers (T2-FLCs) have been developed. Type-2 systems offer a more flexible and stable control structure by incorporating uncertainties into the model’s MFs [26]. However, the applications of these structures are more limited due to the high computational requirements [27]. While T1-FLCs only work with precise MFs [28], type-2 systems have a more flexible structure, especially in cases such as measurement noise and parameter uncertainty. However, these systems can only model second-order uncertainties [29]. Type-3 fuzzy logic controller (T3-FLC), on the other hand, provides a third-order uncertainty model on top of MFs, allowing more complex and multi-layered uncertainties to be managed [30,31].

Recent advances in T3-FLCs have followed two primary research directions: control applications and system optimization. In control applications, type-3 fuzzy sets demonstrate superior capability in handling third-order uncertainty, leading to consistent improvements in transient performance and robustness against parameter variations and external disturbances compared to conventional fuzzy controllers [32]. This is further supported by evidence showing that T3-FLC enhances transient metrics and strengthens maximum power point tracking stability under nonlinear regimes induced by operating condition variations, such as temperature and pressure [33]. Concurrently, in the field of optimization, significant progress has been made in developing practical implementation methods for type-3 fuzzy logic systems (T3-FLS). For hydrogen fuel-cell applications, interval type-3 PID designs have achieved notable improvements in tracking accuracy and disturbance rejection, leveraging the additional tuning flexibility inherent in type-3 modeling [34]. The integration of T3-FLS with optimization frameworks has yielded substantial benefits, including enhanced parameter tuning through harmony search algorithms [35] and enhanced search efficiency using interval type-3 adaptation in bee colony optimization [36]. Further advancing the field, a self-structuring approach based on invasive weed optimization has been developed to simultaneously optimize multiple parameters, including rule-base size, MF shapes, and secondary-membership parameters [37]. The foundations for the practical online adaptation of type-3 systems were established earlier through an online-learning interval type-3 control framework for power and energy management applications [38]. T3-FLCs can enhance dynamic performance, particularly due to their more robust structures against sudden changes [39]. With these features, they offer an effective solution by benefiting from both the simplicity of type-1 and the uncertainty management of type-2 [40].

Recent intelligent control strategies for three-phase PWM rectifiers have increasingly moved beyond conventional linear regulators. Early fuzzy-logic-based rectifier control demonstrated that three-phase PWM rectifiers can achieve satisfactory DC-bus voltage regulation and unity power-factor operation [25,41,42]. This direction was extended to neuro-fuzzy approaches, where nonlinear mapping capability was exploited to improve voltage regulation and synchronous-frame current control in PWM rectifiers [43]. More recent type-2 fuzzy neural network strategies have been reported to cope with uncertainty and parameter variations, including experimentally validated PD-type-2 fuzzy neural network control [44] and artificial-bee-colony-based type-2 fuzzy neural network control for DC-link voltage regulation under step changes, disturbances, unbalanced grid conditions, and regenerative operation [7]. Optimization-assisted interval type-2 fuzzy neural controllers have also shown improved transient behavior and robustness under different operating conditions [2]. In addition to fuzzy/neuro-fuzzy regulators, predictive and hybrid intelligent methods have been investigated for improved transient behavior and power quality (PQ) indices in PWM rectifiers [13,14,45]. Learning-oriented smart direct power control concepts have also been explored for ripple suppression and transient enhancement in three-phase PWM rectifiers [46]. Despite these developments, a systematic application of higher-order fuzzy uncertainty modeling, particularly type-3 fuzzy logic systems, to DC-bus voltage regulation in three-phase PWM rectifiers remains limited. This study aims to address this research gap through a systematic evaluation of the proposed T3-FLC for outer-loop DC-bus voltage regulation in a three-phase PWM rectifier and benchmarking it against PI and type-1 fuzzy logic baselines under a unified set of nominal, disturbed, and regenerative operating scenarios, clearly highlighting the novelty of the proposed approach.

In this study, a T3-FLC is designed and implemented in the outer control loop of a three-phase PWM rectifier. The control structure consists of two basic loops. The outer control loop aims to keep the DC output voltage of the system constant at the desired reference value, and the reference d-axis current obtained as the output of this loop is sent to the inner control loop. To ensure that the rectifier operates at a unity PF, the q-axis current reference is set to zero. The inner control loop performs high-bandwidth current control by monitoring the currents in the synchronous d–q frame separately in line with the obtained reference values. In both control loops, the structure is designed to be robust and to respond quickly to the system’s nonlinear dynamics. The developed T3-FLC provides both high accuracy output voltage regulation and high adaptability to system performance and disturbances.

For this evaluation, a detailed MATLAB/Simulink (R2023b, MathWorks, USA) model was developed to accurately represent the PWM rectifier’s control dynamics. The performance of the proposed controller was comprehensively evaluated under different operating scenarios: constant reference input performance, reference tracking, load disturbance rejection, regenerative operation, distorted grid voltage, grid voltage sag, grid voltage swell, and unbalanced grid. First, the operation at a constant reference DC-bus voltage was analyzed to examine the controller’s capability to maintain voltage regulation with minimal steady-state error and low ripple content. Second, the response to sudden changes in the reference DC-bus voltage was investigated, with emphasis on assessing overshoot and undershoot characteristics, as well as the settling time required for the system to reach its new equilibrium. Third, the system’s stability and regulation performance were tested under load variations on the DC side of the rectifier, allowing evaluation of its robustness to disturbances. The regenerative operating mode was simulated to analyze the system’s ability to reverse power flow, provide energy feedback to the grid, and preserve stability. Furthermore, the controller’s robustness was validated under four additional grid disturbances. The distorted grid voltage test evaluated harmonic immunity and its impact on total harmonic distortion (THD). The grid-voltage sag and swell scenarios assessed dynamic response, specifically the controller’s ability to maintain DC-bus voltage regulation during sudden voltage drops and to prevent over-voltage during voltage increases. Finally, the unbalanced grid test evaluated stability and ripple rejection performance under asymmetric conditions.

Based on these comprehensive simulation studies, the proposed T3-FLC exhibits superior performance in terms of both voltage regulation and system stability. Simulation results further confirm its robustness to uncertainties and sudden dynamic variations compared to T1-FLC and traditional PI controllers. The study’s results show that T3-FLCs are a promising alternative for PWM rectifier applications.

The main contributions of this study can be summarized as follows:

• To the best of the authors’ knowledge, this study is the first to systematically investigate a cascaded control scheme employing a type-3 fuzzy logic controller for the outer DC-bus loop, integrated with PI regulators for the inner synchronous d–q current loops.
• The T3-FLC improves transient performance in the examined scenarios, yielding shorter settling times and markedly lower overshoot than PI and T1-FLC in most operating conditions.
• Under dynamic operating scenarios, including sudden load transients and regenerative operation, the T3-FLC maintains tight DC-bus regulation with minimal overshoot/undershoot and exhibits strong disturbance-rejection capability.
• Across all investigated conditions, it maintains a near-unity PF and generally achieves competitive THD compared with the benchmark controllers, thereby enhancing PQ.

2. Three-Phase PWM Rectifier

The schematic representation of the three-phase PWM rectifier is shown in Figure 1. It consists of a three-phase AC source connected through line inductors $L_s$ and resistors $R_s$ to a voltage-source converter, where six IGBT switches ($S_A$, $S_B$, and $S_C$) operate under PWM control to regulate the DC-bus voltage $V_{dc}$. The DC side includes a smoothing capacitor C, and a resistive load $R_L$ [47]. The mathematical model is derived under the standard assumptions of balanced three-phase grid voltages, identical line impedances, and negligible switching and converter losses.

Figure 1. Schematic of the three-phase PWM rectifier. The red dashed lines denote the PWM control signals, whereas the solid black arrows represent the direction of current flow.

The three-phase mathematical model of the rectifier on the AC side, derived from Kirchhoff’s Voltage Law, is presented in Equation (1) [48].

$$v_{\mathrm{grid}-abc}=L_s{\displaystyle \frac{d{i}_{abc}}{dt}}+R_s{i}_{abc}+v_{\mathrm{rec}-abc}$$

(1)

The three-phase AC grid voltages are given by Equation (2).

$$\begin{array}{cc}\hfill v_{\mathrm{grid}-a}& =v_{m}sin\left(\omega t\right)\hfill \\ \hfill v_{\mathrm{grid}-b}& =v_{m}sin(\omega t-2\pi /3)\hfill \\ \hfill v_{\mathrm{grid}-c}& =v_{m}sin(\omega t+2\pi /3)\hfill \end{array}$$

(2)

The input voltages of the three-phase rectifier are written as follows:

$$\begin{array}{cc}\hfill v_{\mathrm{rec}-a}& =\left[S_a-{\displaystyle \frac{1}{3}}(S_a+S_b+S_c)\right]V_{dc}\hfill \\ \hfill v_{\mathrm{rec}-b}& =\left[S_b-{\displaystyle \frac{1}{3}}(S_a+S_b+S_c)\right]V_{dc}\hfill \\ \hfill v_{\mathrm{rec}-c}& =\left[S_c-{\displaystyle \frac{1}{3}}(S_a+S_b+S_c)\right]V_{dc}\hfill \end{array}$$

(3)

where $S_a,S_b,S_c$ denote the phase switching functions (or duty ratios). The power rectifiers employ a DC-bus capacitor to stabilize the voltage. The current through the capacitor located on the DC side is given by Equation (4).

$$C{\displaystyle \frac{d{V}_{dc}}{dt}}=S_a{i}_a+S_b{i}_b+S_c{i}_c-{\displaystyle \frac{V_{dc}}{R_L}}$$

(4)

Substituting Equation (3) into Equation (1) yields Equation (5).

$$\begin{array}{cc}\hfill L_s{\displaystyle \frac{d{i}_a}{dt}}& =v_{\mathrm{grid}-a}-R_s{i}_a+{\displaystyle \frac{S_b+S_c-2S_a}{3}}{V}_{dc}\hfill \\ \hfill L_s{\displaystyle \frac{d{i}_b}{dt}}& =v_{\mathrm{grid}-b}-R_s{i}_b+{\displaystyle \frac{S_a+S_c-2S_b}{3}}{V}_{dc}\hfill \\ \hfill L_s{\displaystyle \frac{d{i}_c}{dt}}& =v_{\mathrm{grid}-c}-R_s{i}_c+{\displaystyle \frac{S_a+S_b-2S_c}{3}}{V}_{dc}\hfill \end{array}$$

(5)

Applying the Park transformation to Equation (5) yields the AC-side model of the rectifier in the synchronous d–q frame as in Equation (6). This representation facilitates the synthesis of current controllers, as follows [48,49]:

$$\begin{array}{cc}\hfill L_s{\displaystyle \frac{d{i}_d}{dt}}& =v_{\mathrm{grid}-d}-R_s{i}_d+\omega L_s{i}_q-v_{\mathrm{rec}-d}\hfill \\ \hfill L_s{\displaystyle \frac{d{i}_q}{dt}}& =v_{\mathrm{grid}-q}-R_s{i}_q-\omega L_s{i}_d-v_{\mathrm{rec}-q}\hfill \end{array}$$

(6)

where $v_{\mathrm{rec}-d}=S_d{V}_{dc}$ and $v_{\mathrm{rec}-q}=S_q{V}_{dc}$ are the converter synchronous d–q frame voltages produced by the modulation signals $S_d,S_q$. The DC-side dynamics are given by [48]:

$$C{\displaystyle \frac{d{V}_{dc}}{dt}}={\displaystyle \frac{3}{2}}\left(S_d{i}_d+S_q{i}_q\right)-{\displaystyle \frac{V_{dc}}{R_L}}$$

(7)

For controller design, we introduce the decoupled virtual inputs as [48]:

$$\begin{array}{cc}\hfill u_{\mathrm{rec}-d}^{\prime }& =v_{\mathrm{grid}-d}-v_{\mathrm{rec}-d}+\omega L_s{i}_q\hfill \\ \hfill u_{\mathrm{rec}-q}^{\prime }& =v_{\mathrm{grid}-q}-v_{\mathrm{rec}-q}-\omega L_s{i}_d\hfill \end{array}$$

(8)

which cancel the cross-coupling terms $\pm \omega L_s{i}_{q,d}$ and feedforward the grid voltages. Substituting Equations (8) into Equation (6) yields the first-order current dynamics.

$$L_s{\displaystyle \frac{d{i}_d}{dt}}=-R_s{i}_d+u_{\mathrm{rec}-d}^{\prime },L_s{\displaystyle \frac{d{i}_q}{dt}}=-R_s{i}_q+u_{\mathrm{rec}-q}^{\prime }$$

(9)

Equations (9) are consistent with the control algorithm in which the voltage commands are formed by adding $R_s{i}_{d,q}$ feedforward and PI feedback to the decoupling terms [50].

3. Type-3 Fuzzy Logic Control

In this section, the fundamental concept and operating principles of the T3-FLC are introduced, covering its input–output structure, MF formulation, fuzzy rule base, and defuzzification process. Recently, T3-FLCs have emerged as an effective alternative for modeling and controlling highly uncertain and nonlinear systems [32,51]. While traditional T1-FLC and T2-FLC model uncertainty using crisp and interval-based MFs, respectively, T3-FLCs allow uncertainty to be represented with higher accuracy using three-dimensional MFs [52,53]. The overall fuzzy inference structure consists of conventional fuzzy operations: fuzzification, rule evaluation, aggregation, and defuzzification [54,55]. With type-3 MFs, both fuzzification and aggregation explicitly handle higher-dimensional uncertainty. The proposed controller is used for DC-bus voltage regulation of a three-phase PWM rectifier.

3.1. Overview of the T3-FLC Structure

Before presenting the mathematical formulation, this subsection provides an intuitive overview of the proposed T3-FLC. Figure 2 summarizes the main processing stages [56].

Figure 2. Conceptual structure of the T3-FLC. Arrows indicate the sequential flow of signal processing from crisp inputs to final control action.

The controller operates on two crisp inputs: the DC-bus voltage error e and its change $\Delta e$, as shown in the first block of Figure 2. These signals are first scaled or normalized by multiplying them with appropriate gains to map them to the required ranges for fuzzification. In the type-3 fuzzification stage, the scaled inputs are converted into type-3 fuzzy sets using three linguistic terms (Negative, Zero, Positive) for each variable. Unlike type-1 and type-2 fuzzifiers, the type-3 fuzzifier assigns a set of horizontally sliced membership surfaces to each term, representing different levels of uncertainty [30,52,53].

The membership evaluation stage computes the upper and lower membership degrees for each fuzzy set. These membership values drive the rule-activation block, where the if-then rules are triggered. Each rule expresses a qualitative control action (e.g., “if e is Positive and $\Delta e$ is Positive, then apply a strong corrective effort”). For each activated rule, the firing-strength computation block determines its strength, after which the aggregation block combines the firing strengths into a single fuzzy output. The type-reduction and defuzzification stage then collapses this high-dimensional type-3 output set into an interval type-2 set and converts it to a crisp value [30,32]. The resulting crisp control signal u is applied as the final control action and is used to generate the d-axis current reference $i_d^{*}$ in the outer control loop.

3.2. Type-3 Membership Function Formulation

This subsection details the MFs used in the fuzzifier block of Figure 2, specifying how the interval type-3 sets for e and $\Delta e$ are constructed. The structure of the proposed type-3 MFs for the input variables is shown in Figure 3, where the primary and secondary membership dimensions illustrate the third-order uncertainty modeling capability. Each input $x_i$ ($i=1,2$) is associated with a set of type-3 MFs whose centers are collected in $c_i$ (for brevity, the elements of $c_1$ and $c_2$ are not enumerated). For a generic linguistic term, a type-3 MF is represented by upper and lower membership surfaces parameterized by a horizontal slicing parameter ${\gamma }_j$. Intuitively, the upper and lower surfaces capture the uncertainty bounds of the membership grade for the same rule slice, while the horizontal slice level ${\gamma }_j$ controls how the membership surface decays across the operating domain. Let $d_L$ denote the MF center, and ${\underline{\sigma }}_L$, ${\overline{\sigma }}_L$ the left and right spreads, respectively. Here, ${\underline{\sigma }}_L$ and ${\overline{\sigma }}_L$ determine the support/width of each MF on the left and right sides around the center $d_L$ (i.e., where the membership becomes zero). The upper surfaces are given by [52,53]

$${\overline{M}}_{L,{\overline{\gamma }}_j}\left(x\right)=\left\{\begin{array}{cc}1-{\left({\displaystyle \frac{|x-d_L|}{{\underline{\sigma }}_L}}\right)}^{{\overline{\gamma }}_j},\hfill & \mathrm{if}{d}_L-{\underline{\sigma }}_L<x\le d_L,\hfill \\ 1-{\left({\displaystyle \frac{|x-d_L|}{{\overline{\sigma }}_L}}\right)}^{{\overline{\gamma }}_j},\hfill & \mathrm{if}{d}_L<x\le d_L+{\overline{\sigma }}_L,\hfill \\ 0,\hfill & \mathrm{otherwise},\hfill \end{array}\right.$$

(10)

$${\overline{M}}_{L,{\underline{\gamma }}_j}\left(x\right)=\left\{\begin{array}{cc}1-{\left({\displaystyle \frac{|x-d_L|}{{\underline{\sigma }}_L}}\right)}^{{\underline{\gamma }}_j},\hfill & \mathrm{if}{d}_L-{\underline{\sigma }}_L<x\le d_L,\hfill \\ 1-{\left({\displaystyle \frac{|x-d_L|}{{\overline{\sigma }}_L}}\right)}^{{\underline{\gamma }}_j},\hfill & \mathrm{if}{d}_L<x\le d_L+{\overline{\sigma }}_L,\hfill \\ 0,\hfill & \mathrm{otherwise},\hfill \end{array}\right.$$

(11)

and the lower surfaces are

$${\underline{M}}_{L,{\overline{\gamma }}_j}\left(x\right)=\left\{\begin{array}{cc}1-{\left({\displaystyle \frac{|x-d_L|}{{\underline{\sigma }}_L}}\right)}^{1/{\overline{\gamma }}_j},\hfill & \mathrm{if}{d}_L-{\underline{\sigma }}_L<x\le d_L,\hfill \\ 1-{\left({\displaystyle \frac{|x-d_L|}{{\overline{\sigma }}_L}}\right)}^{1/{\overline{\gamma }}_j},\hfill & \mathrm{if}{d}_L<x\le d_L+{\overline{\sigma }}_L,\hfill \\ 0,\hfill & \mathrm{otherwise},\hfill \end{array}\right.$$

(12)

$${\underline{M}}_{L,{\underline{\gamma }}_j}\left(x\right)=\left\{\begin{array}{cc}1-{\left({\displaystyle \frac{|x-d_L|}{{\underline{\sigma }}_L}}\right)}^{1/{\underline{\gamma }}_j},\hfill & \mathrm{if}{d}_L-{\underline{\sigma }}_L<x\le d_L,\hfill \\ 1-{\left({\displaystyle \frac{|x-d_L|}{{\overline{\sigma }}_L}}\right)}^{1/{\underline{\gamma }}_j},\hfill & \mathrm{if}{d}_L<x\le d_L+{\overline{\sigma }}_L,\hfill \\ 0,\hfill & \mathrm{otherwise}.\hfill \end{array}\right.$$

(13)

where x is the scalar input (with centers collected in $c_1$ or $c_2$), $d_L$ is the MF center, ${\underline{\sigma }}_L$ and ${\overline{\sigma }}_L$ are the left/right spreads, and ${\overline{\gamma }}_j,{\underline{\gamma }}_j$ are upper/lower shape (slice) exponents for horizontal slice j.

Figure 3. Type-3 MF representation for the T3-FLC inputs. The magenta curves denote the secondary MFs, while the green shaded regions represent the primary MFs; black lines indicate their boundaries.

With this definition, the membership grade reaches 1 at the center ($x=d_L$) and becomes 0 outside the support interval set by the spreads. Moreover, the slice exponents ${\overline{\gamma }}_j$ and ${\underline{\gamma }}_j$ shape the curvature/steepness of the upper and lower surfaces, respectively, thereby controlling how rapidly the membership decreases as the input moves away from the MF center.

As illustrated in Figure 3, for each input variable of the T3-FLC, only three MFs (L, Z, and R) are employed. The L/Z/R partitions provide a compact linguistic cover for negative, near-zero, and positive operating regions of the input, while the uncertainty is represented through the additional upper/lower bounds and the slice exponents $(\sigma ,\gamma )$. Although this number is smaller than the five- or seven-term partitions commonly used in T1-FLCs, each type-3 MF contains four independent bounds, providing a richer representation of uncertainty. Therefore, three linguistic terms are sufficient to cover the full operating range while keeping the rule base compact.

In practice, $\sigma$ mainly determines how wide each linguistic region remains active, whereas $\gamma$ mainly governs how sharp the membership drop is for each horizontal slice, which together support good coverage with a small rule set. This structure reduces the online computational burden and avoids generating a large number of low-firing or inactive rules, thereby improving real-time feasibility without sacrificing control accuracy or dynamic performance [52].

The nonlinear input–output mapping realized by the proposed T3-FLC is illustrated in Figure 4. The surface shows how the controller maps the DC-bus voltage error e and its change $\Delta e$ to the normalized control output u. For a wide range of negative and positive errors, the surface remains relatively smooth and bounded, indicating that the T3-FLC avoids excessively aggressive control actions while still providing sufficient corrective effort. The repeating dome-shaped patterns reflect the activation of different rule combinations as $(e,\Delta e)$ move across the operating space, allowing the controller to modulate its response to both the magnitude and the rate of change of the voltage deviation.

Figure 4. Rule surface of the implemented T3-FLC mapping the DC-bus voltage error e and its change $\Delta e$ to the control output u.

3.3. Fuzzy Rule Base and Firing Strength Computation

This subsection formalizes the rule-base and firing-strength computation stages depicted in Figure 2, focusing on the structure of the former and the derivation of firing strengths for each type-3 rule. The rule base maps linguistic terms from input 1 (with centers denoted by $c_1$) and input 2 (with centers denoted by $c_2$) to a specific set of singleton consequents. A generic rule is given by [52,53]:

$$\mathrm{IF}{x}_1\mathrm{is}{\tilde{A}}_1\mathrm{AND}{x}_2\mathrm{is}{\tilde{A}}_2,\mathrm{THEN}y\mathrm{is}\tilde{B}.$$

For a given horizontal slice level ${\gamma }_j$, the product t-norm is used to compute the four firing strengths (upper–upper, lower–lower, upper–lower, and lower–upper):

$${\overline{\mu }}_{{\overline{\gamma }}_j^l}={\overline{M}}_{L,{\overline{\gamma }}_j}\left(x_1\right){\overline{M}}_{L,{\overline{\gamma }}_j}\left(x_2\right)$$

(14)

$${\overline{\mu }}_{{\underline{\gamma }}_j^l}={\overline{M}}_{L,{\underline{\gamma }}_j}\left(x_1\right){\overline{M}}_{L,{\underline{\gamma }}_j}\left(x_2\right)$$

(15)

$${\underline{\mu }}_{{\overline{\gamma }}_j^l}={\underline{M}}_{L,{\overline{\gamma }}_j}\left(x_1\right){\underline{M}}_{L,{\overline{\gamma }}_j}\left(x_2\right)$$

(16)

$${\underline{\mu }}_{{\underline{\gamma }}_j^l}={\underline{M}}_{L,{\underline{\gamma }}_j}\left(x_1\right){\underline{M}}_{L,{\underline{\gamma }}_j}\left(x_2\right)$$

(17)

where $l\in \{1,\dots ,R\}$ indexes the fuzzy rules; R is the total number of rules. The four firing strengths correspond to upper–upper, lower–lower, upper–lower, and lower–upper slice combinations obtained by product t-norm.

3.4. Output Computation and Defuzzification

Once the firing strengths are determined, the aggregation stage—as depicted in Figure 2—combines them into partial outputs. For the upper and lower sides at slice ${\gamma }_j$, these are obtained by taking normalized weighted sums of the singleton consequents as follows [52,53]:

$${\overline{f}}_j={\displaystyle \frac{{\sum }_{l=1}^R\left({\overline{\mu }}_{{\overline{\gamma }}_j^l}{\overline{w}}_l+{\underline{\mu }}_{{\overline{\gamma }}_j^l}{\underline{w}}_l\right)}{{\sum }_{l=1}^R\left({\overline{\mu }}_{{\overline{\gamma }}_j^l}+{\underline{\mu }}_{{\overline{\gamma }}_j^l}\right)}}$$

(18)

$${\underline{f}}_j={\displaystyle \frac{{\sum }_{l=1}^R\left({\overline{\mu }}_{{\underline{\gamma }}_j^l}{\overline{w}}_l+{\underline{\mu }}_{{\underline{\gamma }}_j^l}{\underline{w}}_l\right)}{{\sum }_{l=1}^R\left({\overline{\mu }}_{{\underline{\gamma }}_j^l}+{\underline{\mu }}_{{\underline{\gamma }}_j^l}\right)}}$$

(19)

where ${\overline{w}}_l$ and ${\underline{w}}_l$ are the aggregated upper/lower singleton consequents of rule l (in implementation, ${\overline{w}}_l$ collects $w_l^{uu},w_l^{\mathcal{l}\mathcal{l}}$, and ${\underline{w}}_l$ collects $w_l^{u\mathcal{l}},w_l^{\mathcal{l}u}$). If needed, a small regularizer $\epsilon >0$ can be added to denominators to avoid division by zero. The crisp output of T3-FLC $u_{\mathrm{T}3}$ is computed as a convex combination of the slice endpoints as follows [52,53]:

$$u_{\mathrm{T}3}={\displaystyle \frac{{\sum }_{j=1}^K\left({\underline{\gamma }}_j{\underline{f}}_j+{\overline{\gamma }}_j{\overline{f}}_j\right)}{{\sum }_{j=1}^K\left({\underline{\gamma }}_j+{\overline{\gamma }}_j\right)}}$$

(20)

where K is the number of horizontal slices; ${\underline{\gamma }}_j$, ${\overline{\gamma }}_j$ are nonnegative slice weights, and ${\underline{f}}_j$, ${\overline{f}}_j$ are the lower/upper partial outputs at slice j. In our implementation, $K=1$, so $u_{\mathrm{T}3}$ reduces to the average of the two endpoints. A single slice is adopted to minimise the online computational burden whilst preserving the essential upper–lower uncertainty structure of the type-3 output.

4. The Proposed Control Method

The proposed cascaded control scheme, illustrated in Figure 5, consists of a T3-FLC-based DC-bus voltage controller (outer control loop) and inner current control loops in the synchronous frame. The architecture cleanly separates slow DC-bus energy regulation (outer control loop) from fast current dynamics (inner synchronous d–q frame loops), enabling loop-by-loop tuning and robust execution of the commanded converter voltages that are finally mapped to sinusoidal PWM.

Figure 5. Proposed cascaded control architecture: T3-FLC for DC-bus voltage regulation and inner PI-controlled d–q current loops with decoupling. Note: Asterisks on variables denote reference signals.

Phase voltages $v_{\mathrm{grid}-abc}$ and line currents $i_{abc}$ are measured. A phase-locked loop (PLL) estimates the grid phase angle $\theta$; the currents are then mapped to the synchronous d–q frame via the Clarke–Park transformations, as expressed in the following equation.

$$\left[\begin{array}{c}{i}_d\\ i_q\end{array}\right]=\mathcal{P}\left(\theta \right)\mathcal{C}{i}_{abc}$$

(21)

where $i_d$ and $i_q$ are the currents on the d- and q-axes, while $\mathcal{C}$ and $\mathcal{P}\left(\theta \right)$ represent the Clarke and Park transformation operators, respectively. The d-axis is aligned with the grid voltage; therefore, $v_{\mathrm{grid}-q}\approx 0$ and $v_{\mathrm{grid}-d},v_{\mathrm{grid}-q}$ represent the frame components synchronous d–q of the grid voltage.

4.1. Outer Control Loop: DC-Bus Voltage Regulation with a T3-FLC

The outer control loop regulates the DC-bus voltage $V_{dc}$ around its reference $V_{dc}^{★}$. In continuous time, the voltage error and its time derivative are defined as

$$e\left(t\right)=V_{dc}^{★}\left(t\right)-V_{dc}\left(t\right),\dot{e}\left(t\right)={\displaystyle \frac{de\left(t\right)}{dt}}$$

(22)

The T3-FLC receives two normalized inputs derived from the scaled forms of these quantities:

$$s_1\left(t\right)=M_{1}e\left(t\right),s_2\left(t\right)=M_2\dot{e}\left(t\right)$$

(23)

where $M_1,M_2>0$ are input scaling factors. In the digital implementation with sampling period $T_s$, the error and its rate of change are computed as

$$e\left[k\right]=V_{dc}^{★}\left[k\right]-V_{dc}\left[k\right],\Delta e\left[k\right]=e\left[k\right]-e[k-1]$$

(24)

and the normalized inputs of the T3-FLC become

$$s_1\left[k\right]=M_{1}e\left[k\right],s_2\left[k\right]=M_2\Delta e\left[k\right]$$

(25)

These two input variables are converted into fuzzy sets through a fuzzification process using the predefined type-3 MFs. The fuzzified inputs are processed by the T3-FLC rule base, and the inference mechanism produces a fuzzy output, which is then defuzzified into a crisp control signal. The T3-FLC output $u_{\mathrm{T}3}\left(t\right)$ represents the rate of change of the d-axis current reference:

$$u_{\mathrm{T}3}\left(t\right)={\displaystyle \frac{d{i}_d^{★}\left(t\right)}{dt}}$$

(26)

and the integrator block $1/s$ yields

$$i_d^{★}\left(t\right)=i_d^{★}\left(0\right)+M_3{\int }_0^t{u}_{\mathrm{T}3}\left(\tau \right)d\tau$$

(27)

where $M_3$ is the output scaling factor. In this study, the scaling factors $M_1$, $M_2$, and $M_3$ were all set to unity ($M_1=M_2=M_3=1$), so that the voltage error e, its derivative $\Delta e$, and the defuzzified output are used directly without additional scaling. Tuning was performed by adjusting the type-3 MF parameters—the centers $d_L$, the left and right spreads ${\underline{\sigma }}_L$ and ${\overline{\sigma }}_L$, and the slice exponents ${\underline{\gamma }}_j$ and ${\overline{\gamma }}_j$—rather than the input or output gains, thus keeping the controller structure simple and focusing the design effort on the fuzzy sets that define the nonlinear mapping. The MF parameters were tuned manually through iterative trial-and-error simulations, guided by performance metrics such as DC-bus voltage overshoot, settling time, and steady-state ripple. Initial values for the spreads and slice exponents were chosen from ranges commonly used in type-3 fuzzy control; fine-tuning was conducted over several simulation runs until the closed-loop response met acceptable specifications. The chosen parameters were validated by comparing T3-FLC performance with PI and T1-FLC under the same test conditions (Section 5), confirming that the manually tuned configuration yields competitive or superior regulation.

To prevent over-current and integrator windup, a saturation mechanism ensures $i_d^{★}\in [i_{min},i_{max}]$. To keep the PF close to unity, the current reference of the q-axis is set to $i_q^{★}=0$. In discrete time, the reference is updated as

$$i_d^{★}\left[k\right]=\mathrm{sat}\left(i_d^{★}[k-1]+T_s{u}_{\mathrm{T}3}\left[k\right]\right)$$

(28)

Thus, the T3-FLC directly shapes the evolution of the current reference on the d-axis, linking the fuzzy decision-making process to the physical current control loop.

4.2. Inner Control Loops: d–q Current Control and Decoupling

The synchronous-frame currents are regulated by PI controllers augmented with cross-coupling feedforward based on the line inductance $L_s$ and the grid angular frequency $\omega$ (from the PLL); the line resistance $R_s$ may be neglected if sufficiently small. The resulting synchronous d–q frame voltage commands are

$$\begin{array}{cc}\hfill v_{\mathrm{rec}-d}^{★}& =v_{\mathrm{grid}-d}+\omega L_s{i}_q-\left(k_{pc}+{\displaystyle \frac{k_{ic}}{s}}\right)\left(i_d^{★}-i_d\right)\hfill \\ \hfill v_{\mathrm{rec}-q}^{★}& =v_{\mathrm{grid}-q}-\omega L_s{i}_d-\left(k_{pc}+{\displaystyle \frac{k_{ic}}{s}}\right)\left(i_q^{★}-i_q\right)\hfill \end{array}$$

(29)

where $v_{\mathrm{rec}-d}^{★}$ and $v_{\mathrm{rec}-q}^{★}$ are the d- and q-axis voltage commands of the converter, and $k_{pc},k_{ic}$ are the PI gains of the inner current loops. The terms $+\omega L_s{i}_q$ and $-\omega L_s{i}_d$ in Equation (29) provide the standard decoupling. The $v_{\mathrm{rec}-d}^{★}$ and $v_{\mathrm{rec}-q}^{★}$ are mapped back to the $abc$ frame through the inverse Park transformation and then applied to a sinusoidal PWM, thereby generating the gate pulses for the three phase PWM rectifier.

5. Results and Discussion

In this section, the performance of the proposed three-phase PWM rectifier system integrated with the T3-FLC is evaluated and compared with conventional PI and T1-FLC controllers. Both steady-state and transient behaviors are analyzed under multiple operating conditions using a common set of time-domain and PQ indices. The simulation framework, control architecture, and case-study results are detailed in the following subsections.

5.1. Simulation Framework and Control Architecture

To comprehensively evaluate the performance of the proposed three-phase PWM rectifier system controlled by the T3-FLC, four operating scenarios were simulated in MATLAB/Simulink: constant reference, reference tracking, load disturbance, and regenerative operation. PQ performance was also evaluated under harmonic injection, sag/swell, and voltage unbalance. The overall structure of the three-phase PWM rectifier system and its T3-FLC-based control sub-blocks are illustrated in Figures S1–S3, and all simulations were conducted with the system and controller settings summarized in Table 1. The detailed Simulink schematics of the model and its sub-blocks are provided in the Supplementary Material.

Table 1. System and controller parameters used in the study.

Parameter	Symbol	Value
Grid voltage	$v_{\mathrm{grid}}$	60 V
Grid frequency	f	50 Hz
Grid impedance	$R_s,L_s$	0.1 Ω, 3 mH
Carrier frequency	$f_c$	5 kHz
Modulation strategy	–	Sinusoidal PWM
DC-bus capacitor	C	3300  µF
DC-bus voltage	$V_{dc}$	200 V
DC load	$R_L$	40 Ω
Converter topology	–	3-phase, 2-level
IGBT on-state resistance	$R_{\mathrm{on}}$	30 mΩ
IGBT forward voltage	$V_{f,\mathrm{IGBT}}$	1 V
Diode forward voltage	$V_{f,\mathrm{D}}$	0.7 V
Snubber circuit	$R_{snub},C_{snub}$	$1\times {10}^6\Omega$, ∞
Sampling time	$T_s$	$5\times {10}^{-5}$ s
Solver type	–	ode45 (auto)
PI gains (voltage loop)	$k_{pv},k_{iv}$	0.4, 20
PI gains (current loop)	$k_{pc},k_{ic}$	35, 60

The DC-bus voltage responses of all controllers are comparatively illustrated, while detailed waveforms, such as the synchronous d–q frame currents, grid voltage–current profiles, and active–reactive power trajectories, are provided specifically for the T3-FLC to highlight its control dynamics. Furthermore, Section 5.3 presents PQ analysis, including input-current THD, PF, and efficiency evaluations, performed for both the main operating conditions and additional grid disturbances such as harmonic injection, voltage sag/swell, and voltage unbalance events.

Performance Metrics and Evaluation Methodology

To ensure a consistent and meaningful comparison of the PI, T1-FLC, and T3-FLC, a unified set of time-domain and PQ metrics are used for all operating conditions, including reference tracking, load disturbances, regenerative operation, and grid-side disturbances (harmonic injection, voltage sag/swell, and unbalance). The time-domain indicators primarily describe the DC-bus voltage response, whereas the PQ metrics characterize the quality of the grid currents and the overall energy conversion. The performance metrics used to evaluate the T3-FLC-based DC-bus voltage controlled rectifier are summarized below.

• Rise/fall time ($t_{\mathrm{rise}}$, $t_{\mathrm{fall}}$): the time required for the DC-bus voltage to traverse from 10% to 90% of the step change. For a step-up (reference increase), $t_{\mathrm{rise}}$ is measured; for a step-down (reference decrease), $t_{\mathrm{fall}}$ is measured.
• Settling time ($t_{\mathrm{settle}}$): the time required for the DC-bus voltage to enter and remain within a $\pm 2\%$ band around its final steady-state value after a disturbance or reference change.
• Recovery time ($t_{\mathrm{rec}}$): the time required for the DC-bus voltage to return to and remain within a $\pm 0.5\%$ band around its steady-state (or reference) value after a disturbance.
• Overshoot/undershoot ($M_{\mathrm{over}},M_{\mathrm{under}}$, %): the maximum positive (overshoot) and negative (undershoot) deviation of the DC-bus voltage with respect to its reference value during the transient interval, normalized to the reference voltage.
• DC-bus voltage ripple ($V_{dc,pp}$, %): the peak-to-peak variation of the DC-bus voltage in steady state, normalized to its steady-state value.
• Steady-state efficiency (${\overline{\eta }}_{\mathrm{ss}}$, %): the ratio of the average output active power on the DC side to the average input active power drawn from the grid under steady-state conditions.
• Steady-state power factor (${\mathrm{PF}}_{\mathrm{ss}}$): the ratio of the steady-state active power to apparent power at the grid side.
• Grid current THD (${\mathrm{THD}}_i$, %): the THD of the grid current in steady state, defined as the ratio of the rms value of all harmonic components to the rms value of the fundamental component, obtained from the FFT of the phase current.

By consistently applying this common set of indices across all simulations, a comprehensive comparison of the PI, T1-FLC, and T3-FLC controllers is achieved in terms of transient speed, robustness, voltage regulation, and overall PQ performance.

5.2. Dynamic Performance and Robustness Comparison

This subsection compares the dynamic performance and robustness of PI, T1-FLC, and T3-FLC under four operating conditions.

5.2.1. Response Under Constant Reference Input

This case study investigates the controllers’ performance under a constant DC-bus reference of 200 V to evaluate their transient response, steady-state regulation, and overall dynamic performance. The primary objective is to verify the effectiveness of the proposed T3-FLC in maintaining a smooth and accurate DC voltage regulation compared to conventional benchmarks.

The simulation results for Case Study 1 are presented in Figure 6. Figure 6a illustrates the comparative DC-bus voltage responses of the PI, T1-FLC, and T3-FLC controllers, while Figure 6b–e show the d-axis current, q-axis current, grid voltage–current waveforms, and active–reactive power characteristics obtained specifically for the T3-FLC. The corresponding quantitative performance metrics are summarized in Table 2.

Figure 6. Simulation results under constant 200 V DC-bus reference (Case Study 1): (a) DC-bus voltage, (b) d-axis current, (c) q-axis current, (d) phase a voltage and current, (e) active and reactive power. Note: The cyan dashed box indicates the zoomed transient region.

Table 2. Dynamic and steady-state performance metrics of controllers for Case Study 1.

Metric	PI	T1-FLC	T3-FLC
$t_{rise}$ (ms)	7.650	12.050	9.650
$M_{\mathrm{over}}$ (%)	13.580	0.300	0.180
$t_{settle}$ (ms)	74.850	22.450	15.650
$V_{dc,pp}$ (%)	0.283	0.228	0.221
THDi (%)	10.837	10.505	9.402
PFss	0.992	0.994	0.993
${\overline{\eta }}_{ss}$ (%)	98.97	98.95	98.93

A comparative evaluation of the rise time shows that the PI controller yields the fastest initial response of 7.65 ms, followed by the T3-FLC with 9.65 ms, while the T1-FLC exhibits the slowest response of 12.05 ms. Although the PI rise time is approximately 21% shorter than that of the T3-FLC, this marginal advantage is outweighed by its considerably longer settling time and excessive overshoot. In terms of settling time, the T3-FLC outperforms the other controllers, stabilizing the system within 15.65 ms, which is about 4.8 times faster than the PI controller with 74.85 ms and also notably faster than the T1-FLC with 22.45 ms. The overshoot analysis further highlights the effectiveness of T3-FLC, which limits the overshoot to only 0.18%, compared to 0.30% for the T1-FLC and a significantly higher 13.58% for the PI controller. The PF values remain close to unity for all controllers because the q-axis current reference was set to zero and the d–q current decoupling structure preserves reactive-power compensation. Therefore, the observed differences mainly appear in the THD_i. This metric is determined by how accurately the inner current loops track $i_d^{*}$ during each controller’s transient correction. Overall, these results indicate that the T3-FLC provides the most balanced transient performance, combining negligible overshoot with robust DC-bus voltage regulation.

5.2.2. Reference Tracking Response

This case evaluates the controller’s ability to track changes in the reference signal in terms of response speed, overshoot, and steady-state accuracy. Simulation results for Case Study 2 are depicted in Figure 7. Figure 7a compares the DC-bus voltage responses of PI, T1-FLC, and T3-FLC. Figure 7b–e present the d-axis current, q-axis current, grid voltage–current waveforms, and active–reactive power characteristics for T3-FLC. In this operating condition, the DC-bus reference voltage is varied stepwise: maintained at 200 V between 0–0.2 s, increased to 250 V between 0.2–0.4 s, and subsequently restored to 200 V between 0.4–0.6 s. The 250 V reference level, corresponding to a 25% increase, was selected to provide a moderate yet sufficiently challenging voltage step for evaluating the controllers’ transient tracking capability. This test setup provides a basis for evaluating the transient response characteristics of the controllers under reference variations. The corresponding quantitative performance indicators for Case Study 2 are summarized in Table 3.

Figure 7. Simulation results under step reference changes (200 V → 250 V → 200 V, Case Study 2): (a) DC-bus voltage, (b) d-axis current, (c) q-axis current, (d) phase a voltage and current, (e) active and reactive power. Note: The cyan and pink dashed boxes indicate the zoomed transient regions.

Table 3. Performance metrics of controllers in different time intervals for Case Study 2.

Metric	0.2–0.4 s (250 V)			0.4–0.6 s (200 V)
	PI	T1-FLC	T3-FLC	PI	T1-FLC	T3-FLC
$t_{\mathrm{rise}/\mathrm{fall}}$ (ms)	18.550	11.800	9.050	18.000	14.000	6.000
$M_{\mathrm{over}}$ (%)	2.608	0.312	0.256	n/a	n/a	n/a
$M_{\mathrm{under}}$ (%)	n/a	n/a	n/a	3.609	1.151	1.088
$t_{\mathrm{settle}}$ (ms)	62.950	15.600	11.500	63.050	18.950	7.700
$V_{dc,pp}$ (%)	0.368	0.215	0.222	0.325	0.294	0.180
THDi (%)	9.083	11.504	6.983	10.659	10.493	10.343
PFss	0.995	0.995	0.995	0.992	0.985	0.981
${\overline{\eta }}_{ss}$ (%)	98.90	98.85	98.82	98.95	98.82	98.79

n/a: Not applicable; the metric is not defined or not measurable for this interval.

With respect to rise/fall time, the T3-FLC exhibits the fastest transient response in both intervals, with rise/fall times of 9.05 ms in the 250 V step-up interval and 6.00 ms in the 200 V step-down interval. The PI controller exhibits the slowest dynamics, with rise/fall times of 18.55 ms and 18.00 ms, respectively. The T1-FLC yields intermediate responses of 11.80 ms and 14.00 ms across the tested intervals. Regarding settling time, the T3-FLC outperforms the other controllers, achieving steady-state operation within 11.50 ms in the step-up interval and 7.70 ms in the step-down interval. This is substantially faster than the PI controller, which requires 62.95 ms and 63.05 ms, and also superior to the T1-FLC, with settling times of 15.60 ms and 18.95 ms. These results underline the superior consistency and transient performance of the T3-FLC in handling reference changes. A comparative assessment of overshoot further substantiates these findings. In the step-up interval, T3-FLC limits overshoot to 0.256%, compared with 0.312% (T1-FLC) and 2.608% (PI). In the step-down interval, T3-FLC limits undershoot to 1.088%, which is lower than 1.151% (T1-FLC) and 3.609% (PI). In the reference-tracking case, the observed differences in THD_i across controllers stem from the coupling between the outer-loop voltage regulation and the inner d–q current tracking. The PI controller can provide slightly better harmonic cancellation in some intervals due to its fixed-gain behavior near steady operation, while T3-FLC prioritizes faster and more well-damped outer-loop corrections, resulting in a different transient modulation pattern. Collectively, the T3-FLC provides the most balanced transient performance, combining rapid settling times and minimal overshoot in the step-up response with a moderate and well-damped undershoot in the step-down response.

5.2.3. Disturbance Rejection Under Load Variations

This test evaluates the controllers’ robustness by subjecting them to sudden load changes, measuring their ability to maintain voltage stability and recover quickly with minimal deviation. The simulation results for Case Study 3 are presented in Figure 8. Figure 8a provides a comparative overview of the DC-bus voltage response under load disturbances for the three controllers (PI, T1-FLC, and T3-FLC), while Figure 8b–e illustrate the d-axis current, q-axis current, grid voltage–current waveforms, and active–reactive power characteristics specifically for the T3-FLC. In this case, the load resistance is reduced from 40 $\Omega$ to 20 $\Omega$ at 0.2 s and subsequently restored to 40 $\Omega$ at 0.4 s, allowing assessment of each controller’s disturbance rejection capability. The 40 $\Omega$ nominal load was selected to represent the rectifier’s rated operating condition, ensuring realistic current and power levels within the converter’s safe limits, while the 20 $\Omega$ step introduces a 100% load increase to test the controller’s robustness. The corresponding quantitative performance metrics are summarized in Table 4.

Figure 8. Simulation results under load variation (40 $\Omega$ → 20 $\Omega$ → 40 $\Omega$, Case Study 3): (a) DC-bus voltage, (b) d-axis current, (c) q-axis current, (d) phase a voltage and current, (e) active and reactive power.

Table 4. Performance metrics of controllers in different time intervals for Case Study 3.

Metric	0.2–0.4 s (20 Ω)			0.4–0.6 s (40 Ω)
	PI	T1-FLC	T3-FLC	PI	T1-FLC	T3-FLC
$t_{\mathrm{rec}}$ (ms)	71.950	11.250	7.350	63.800	11.450	7.150
$M_{\mathrm{over}}$ (%)	0.266	0.301	0.180	n/a	n/a	n/a
$M_{\mathrm{under}}$ (%)	n/a	n/a	n/a	0.324	0.155	0.113
$V_{dc,pp}$ (%)	0.485	0.396	0.348	0.431	0.252	0.280
THDi (%)	4.613	6.084	5.702	10.927	11.117	10.803
PFss	0.998	0.998	0.998	0.992	0.992	0.992
${\overline{\eta }}_{ss}$ (%)	98.66	98.68	98.69	98.96	98.94	98.94

n/a: Not applicable; the metric is not defined or not measurable for this interval.

As summarized in Table 4, this load disturbance scenario highlights the dynamic advantages of the T3-FLC. During the 0.2–0.4 s interval, the T3-FLC achieves the shortest recovery time of 7.35 ms, followed by the T1-FLC with 11.25 ms, whereas the PI controller requires 71.95 ms to restore the DC-bus voltage. In the subsequent 0.4–0.6 s interval, the same trend is preserved: the T3-FLC recovers within 7.15 ms, the T1-FLC within 11.45 ms, while the PI controller again exhibits a significantly slower response with a recovery time of 63.80 ms. The amplitude of the DC-bus deviation is also better controlled by the T3-FLC. For the load step-up interval, the T3-FLC limits the overshoot to 0.18%, compared to 0.301% for the T1-FLC and 0.266% for the PI controller.

Following the load reduction at 0.4 s, the T3-FLC achieves the smallest undershoot of 0.113%, while the T1-FLC and PI controllers exhibit undershoots of 0.155% and 0.324%, respectively. In terms of steady-state DC-bus ripple, the T3-FLC reduces $V_{dc,pp}$ to 0.348% in the 20 $\Omega$ interval and 0.280% in the 40 $\Omega$ interval. This consistently improves upon the PI controller, which shows ripples of 0.485% and 0.431%. The T1-FLC provides slightly lower ripple than the T3-FLC after the load decrease, with 0.252%, but at the cost of slower recovery. Regarding PQ, all controllers maintain nearly unity PF, with PF_ss equal to 0.998 at 20 $\Omega$ and 0.992 at 40 $\Omega$, and a very similar efficiency of 99%. The PI controller achieves the lowest current THD during the heavy-load interval, with THD_i equal to 4.613%, while the T3-FLC yields 5.702% and the T1-FLC 6.084%. However, after the load returns to 40 $\Omega$, the T3-FLC provides the lowest distortion, with a THD_i of 10.803%, slightly outperforming both the PI and T1-FLC controllers. During load transients, the transient modulation from the outer-loop controller affects the instantaneous current waveform and, in turn, the measured THD_i. The PI controller can yield lower THD_i in specific intervals where d-axis tracking remains close to a linear steady operating point, whereas T3-FLC achieves markedly faster recovery and better voltage damping. This yields competitive (but sometimes slightly higher) THD due to the distinct transient current-shaping induced by the fuzzy control effort. These results indicate that the T3-FLC offers a favorable compromise, achieving competitive PQ alongside very fast recovery and well-damped DC-bus deviations under abrupt load variations.

5.2.4. Performance in Regenerative Operation

This case examines controller stability during BPF, testing their ability to handle the reverse energy transfer from the DC side to the grid while maintaining voltage regulation. Simulation results for Case Study 4 are illustrated in Figure 9. Figure 9a shows the comparative DC-bus voltage response under regenerative operation for the three controllers (PI, T1-FLC, and T3-FLC). Figure 9b–e present the d-axis current, q-axis current, grid voltage–current waveforms, and active–reactive power characteristics corresponding to the T3-FLC. In this scenario, a 250 V DC source with an internal resistance of 3 $\Omega$ is connected to the DC side at 0.2 s and disconnected at 0.4 s, triggering regenerative events. The DC source voltage is set approximately 25% higher than the nominal 200 V DC-bus reference to intentionally trigger a controlled regenerative event while maintaining system stability. This voltage difference should ensure sufficient potential for reverse energy transfer without exceeding the converter’s safe operating limits. The corresponding quantitative performance indicators are summarized in Table 5.

Figure 9. Simulation results under regenerative operation (250 V DC source connected at 0.2–0.4 s, Case Study 4): (a) DC-bus voltage, (b) d-axis current, (c) q-axis current, (d) phase a voltage and current, (e) active and reactive power showing BPF.

Table 5. Performance metrics of controllers in different time intervals for Case Study 4.

Metric	0.2–0.4 s			0.4–0.6 s
	PI	T1-FLC	T3-FLC	PI	T1-FLC	T3-FLC
$t_{\mathrm{rec}}$ (ms)	148.650	18.900	11.400	102.650	14.450	10.600
$M_{\mathrm{over}}$ (%)	11.073	4.244	2.675	n/a	n/a	n/a
$M_{\mathrm{under}}$ (%)	n/a	n/a	n/a	17.713	4.819	3.128
$V_{dc,pp}$ (%)	1.576	0.301	0.374	0.670	0.186	0.238
THDi (%)	4.068	5.771	4.655	10.819	11.253	10.800
PFss	−0.998	−0.998	−0.998	0.992	0.992	0.992
${\overline{\eta }}_{ss}$ (%)	98.36	98.30	98.27	98.95	98.74	98.76

n/a: Not applicable; the metric is not defined or not measurable for this interval.

All controllers successfully maintain stable operation under regenerative conditions. However, there are clear differences in the recovery, overshoot, and undershoot behavior. During the first regenerative interval from 0.2 s to 0.4 s, the T3-FLC achieves the fastest recovery, with a recovery time of 11.40 ms, followed by the T1-FLC with 18.90 ms. The PI controller requires 148.65 ms to re-establish steady-state operation. In the subsequent interval from 0.4 s to 0.6 s, the same trend holds: the T3-FLC recovers within 10.60 ms and the T1-FLC within 14.45 ms, while the PI controller again exhibits a much slower response with a recovery time of 102.65 ms. The amplitude of the DC-bus deviation is also significantly better controlled by the fuzzy controllers. In the first interval, the T3-FLC limits the overshoot to 2.675%, while the T1-FLC and PI controllers reach 4.244% and 11.073%, respectively. After the DC source is disconnected at 0.4 s, the undershoot becomes the dominant transient. In this interval, the T3-FLC confines the undershoot to 3.128%, compared with 4.819% for the T1-FLC and 17.71% for the PI controller. In terms of steady-state DC-bus ripple, the T1-FLC provides the lowest $V_{dc,pp}$, with 0.301% in the first interval and 0.186% in the second. The T3-FLC achieves slightly higher but still low values of 0.374% and 0.238%, respectively. The PI controller, by contrast, exhibits substantially larger ripples of 1.576% and 0.670%.

In the first interval, all controllers maintain an almost unity negative PF of $-0.998$, indicating that the grid current is nearly ${180}^{°}$ out of phase with the grid voltage. This behavior is illustrated in Figure 9e. In the second interval, PF is close to 0.992 across all controllers. The efficiencies are close to each other, 98.3–98.9%. The PI controller attains the lowest THD_i during the first regenerative interval, with THD_i equal to 4.068%, while the T3-FLC and T1-FLC yield 4.655% and 5.771%. In the second interval, the T3-FLC provides the lowest distortion, with a THD_i of 10.80%, slightly improving the PI and T1-FLC controllers. In regenerative operation, PF remains close to the expected values (including negative power factor when power flows back) due to the maintained current reference structure in the d–q frame. The remaining controller-dependent differences in THD_i are primarily linked to how quickly and smoothly the controllers re-establish $i_d^{*}$ after power-flow reversal, which shapes the harmonic content of the grid current. In brief, these results show that under regenerative operating conditions, the T3-FLC offers the most favorable compromise, combining very fast recovery and well-damped DC-bus deviations with competitive PQ performance.

Figure 10 summarizes the comparative performance of the PI, T1-FLC, and T3-FLC controllers over the four main simulation cases. Each subplot corresponds to one metric: (a) maximum overshoot, (b) settling/recovery time, (c) DC-bus voltage ripple, and (d) input current THD. Case Study 1 shows steady-state results at a fixed reference; Case Studies 2–4 show two intervals per case, with different hatching used to separate the two time windows (e.g., 0.2–0.4 s and 0.4–0.6 s). In general, the T3-FLC shows lower overshoot, shorter settling/recovery times, and reduced voltage ripple compared to PI and T1-FLC, while maintaining competitive THD levels.

Figure 10. Performance comparison of PI, T1-FLC, and T3-FLC controllers across four case studies: (a) Maximum overshoot ($M_{over}$, %), (b) Settling/recovery time ($t_{settle}$, ms), (c) DC bus voltage ripple ($V_{dc,pp}$, %), (d) Current total harmonic distortion (THD_i, %). For Case 2–4, results are shown for both intervals (0.2–0.4 s and 0.4–0.6 s) with different hatching patterns (diagonal and cross-hatching). Case 1 represents steady-state performance with a single interval.

5.3. Power Quality Analysis

A thorough assessment of PQ is essential for evaluating the effectiveness and robustness of PWM rectifier control strategies, particularly under distorted or dynamic operating conditions. In this study, PQ performance is examined through key indicators such as the THD_i, the PF_ss, and the ${\overline{\eta }}_{ss}$. These metrics collectively capture the controller’s ability to ensure sinusoidal grid current injection, maintain efficient power transfer, and regulate the DC-bus voltage with minimal ripple.

The analysis encompasses both nominal operation and various grid disturbance scenarios, including harmonic injection, voltage sag, voltage swell, and voltage unbalance. By systematically comparing the PI, T1-FLC, and T3-FLC controllers across these conditions, this section highlights the strengths and limitations of each control strategy from a PQ perspective.

5.3.1. Harmonic Distortion Case

This case is used to evaluate the controller’s performance under distorted grid conditions caused by injected voltage harmonics, focusing on DC-bus voltage regulation, current THD, and PF. In the harmonic distortion scenario, where 5% 5th- and 5% 7th-order voltage harmonics are injected into the grid, all three controllers are able to maintain acceptable steady-state performance, but with distinct trade-offs, as summarized in Table 6. The corresponding DC-bus voltage, AC grid voltage/current waveforms, and their harmonic spectra are illustrated in Figure 11a–d. In terms of DC-bus voltage ripple, the fuzzy controllers clearly outperform the PI controller: the T1-FLC achieves the lowest $V_{dc,pp}$ with 0.269%, followed by the T3-FLC with 0.309%, whereas the PI controller exhibits a significantly higher ripple of 0.510%. Conversely, the PI controller provides the lowest input-current distortion, with THD_i equal to 10.543%, while the T1-FLC and T3-FLC yield slightly higher values of 11.009% and 11.504%, respectively. Despite these differences, all controllers maintain the same steady-state PF of 0.992 under harmonic injection, indicating that the displacement and distortion effects are well controlled. From an efficiency standpoint, the T1-FLC offers the highest average efficiency of 98.49%, followed by the T3-FLC with 98.37% and the PI controller with 98.30%. In summary, these results indicate that the fuzzy controllers, particularly the T1-FLC, provide superior DC-bus voltage regulation and slightly higher efficiency under distorted grid conditions, while the PI controller retains a modest advantage in THD_i.

Table 6. Performance metrics of the controllers under harmonic voltage injection.

Metric	PI	T1-FLC	T3-FLC
$V_{dc,pp}$ (%)	0.510	0.269	0.309
THDi (%)	10.543	11.009	11.504
PFss	0.992	0.992	0.992
${\overline{\eta }}_{ss}$ (%)	98.30	98.49	98.37

Figure 11. Performance under distorted grid (5% 5th + 5% 7th harmonics): (a) DC-bus voltage, (b) phase a voltage and current, (c) grid voltage harmonic spectrum, (d) grid current harmonic spectrum.

Under harmonic injection, THD_i is influenced by the accuracy of d-axis current tracking under distorted grid voltages. PI shows the lowest THD_i because its fixed-gain regulation provides consistent steady-state harmonic compensation, even though it may introduce larger DC-bus ripple. By contrast, the fuzzy controllers reduce $V_{dc,pp}$ by generating smoother outer-loop voltage corrections; this improves voltage quality but leads to a modest increase in THD_i, indicating a practical trade-off between DC-bus ripple suppression and harmonic distortion. PF remains nearly identical across controllers because reactive power compensation is preserved by the q-axis reference choice and d–q decoupling.

5.3.2. Voltage Sag and Swell Cases

This case is used to evaluate the controller’s robustness against grid-voltage variations, such as sag and swell events, in terms of DC-bus voltage regulation, dynamic recovery, and PQ performance. In the voltage sag scenario, the grid voltage is reduced to 0.8 pu between 0.2 s and 0.4 s. The corresponding DC-bus voltage, AC grid voltages, and AC grid currents are shown in Figure 12a–c. In this operating condition, all controllers maintain stable operation but with clearly different dynamic behaviors, as summarized in Table 7. During the sag interval, the T1-FLC and T3-FLC restore the DC-bus voltage within one sampling period, with a negligible recovery time at the simulation time resolution. By contrast, the PI controller requires 53.75 ms and exhibits the largest undershoot of 1.594%, compared with about 0.426% for the T1-FLC and 0.413% for the T3-FLC. After the grid voltage returns to 1 pu, the T3-FLC again provides the fastest recovery, within one sampling period, and the smallest overshoot of 0.280%, whereas the PI controller is slower with 53.45 ms and shows a larger overshoot of 1.608%. The T1-FLC yields the lowest DC-bus ripple in both intervals, while all controllers preserve a high PF around 0.99 and very similar efficiencies close to 98.9%. THD_i is slightly lower for the PI controller, particularly during the sag, but at the cost of significantly poorer transient performance. Overall, the T3-FLC offers the most favorable compromise between fast voltage regulation and PQ under voltage sag conditions.

Figure 12. Performance comparison of the controllers under voltage-sag condition: (a) DC-bus voltage response, (b) three-phase grid voltage waveforms, and (c) three-phase grid current waveforms.

Table 7. Performance metrics of controllers in different time intervals for voltage sag.

Metric	0.2–0.4 s (0.8 pu)			0.4–0.6 s (1 pu)
	PI	T1-FLC	T3-FLC	PI	T1-FLC	T3-FLC
$t_{\mathrm{rec}}$ (ms)	53.750	0.000	0.000	53.450	4.750	0.000
$M_{\mathrm{over}}$ (%)	n/a	n/a	n/a	1.608	0.532	0.280
$M_{\mathrm{under}}$ (%)	1.594	0.426	0.413	n/a	n/a	n/a
$V_{dc,pp}$ (%)	0.309	0.244	0.293	0.363	0.252	0.257
THDi (%)	7.191	8.633	8.042	9.663	11.834	11.787
PFss	0.997	0.997	0.997	0.993	0.994	0.994
${\overline{\eta }}_{ss}$ (%)	98.78	98.78	98.79	98.95	98.96	98.96

n/a: Not applicable; the metric is not defined or not measurable for this interval.

In the voltage swell scenario, where the grid voltage is increased to 1.2 pu between 0.2 s and 0.4 s and kept at 1 pu in the remaining interval, the dynamic and steady-state behaviors of the controllers differ markedly, as summarized in Table 8. During the swell interval, both fuzzy controllers restore the DC-bus voltage within one sampling period, with a recovery time that is negligible at the chosen time resolution, whereas the PI controller requires 44.00 ms. In the same interval, the T3-FLC achieves the smallest overshoot of 0.273%, followed by the T1-FLC with 0.412%, while the PI controller reaches 1.191%. The DC-bus ripple is also lower for the fuzzy schemes, with $V_{dc,pp}$ equal to 0.366% for the T1-FLC and 0.419% for the T3-FLC, compared to 0.584% for the PI controller, although the PI controller provides the lowest current distortion with THD_i equal to 11.424%. After the grid voltage returns to 1 pu in the 0.4–0.6 s interval, the T1-FLC and T3-FLC again achieve recovery within one sampling period, while the PI controller requires 51.55 ms and exhibits the largest undershoot of 1.229%. The T3-FLC limits this undershoot to 0.256%, slightly below the 0.263% of the T1-FLC. It also yields the lowest DC-bus ripple, with $V_{dc,pp}$ equal to 0.230%. All controllers maintain a similar PF of 0.993 and identical efficiency of 98.96%, while THD_i is lowest for the T1-FLC in this interval. Collectively, the T3-FLC offers the best transient behavior and DC-bus regulation under swell conditions, with the fuzzy controllers trading a small increase in THD_i for significantly improved dynamic performance compared with the PI controller.

Table 8. Performance metrics of controllers in different time intervals for voltage swell.

Metric	0.2–0.4 s (1.2 pu)			0.4–0.6 s (1 pu)
	PI	T1-FLC	T3-FLC	PI	T1-FLC	T3-FLC
$t_{\mathrm{rec}}$ (ms)	44.000	0.000	0.000	51.550	0.000	0.000
$M_{\mathrm{over}}$ (%)	1.191	0.412	0.273	n/a	n/a	n/a
$M_{\mathrm{under}}$ (%)	n/a	n/a	n/a	1.229	0.263	0.256
$V_{dc,pp}$ (%)	0.584	0.366	0.419	0.253	0.244	0.230
THDi (%)	11.424	14.193	13.304	11.466	10.547	12.520
PFss	0.987	0.988	0.988	0.993	0.993	0.993
${\overline{\eta }}_{ss}$ (%)	99.054	99.052	99.05	98.96	98.96	98.96

n/a: Not applicable; the metric is not defined or not measurable for this interval.

Across sag/swell events, PI provides lower THD_i than the fuzzy controllers, which suggests better harmonic suppression in the inner current regulation during these grid-amplitude variations. However, PI exhibits poorer transient voltage damping (larger overshoot/undershoot or slower recovery), which increases $V_{dc,pp}$ and leads to a different overall PQ trade-off. Meanwhile, T3-FLC prioritizes fast and well-damped DC-bus recovery, slightly affecting the harmonic content due to its distinct transient modulation behavior.

5.3.3. Voltage Unbalance Case

In this voltage-unbalance scenario, the grid voltage is kept at 1 pu between 0 and 0.2 s, reduced to 0.95 pu between 0.2 and 0.4 s, and increased to 1.05 pu between 0.4 and 0.6 s, corresponding to $\pm 5\%$ unbalance conditions, as summarized in Table 9. The corresponding DC-bus response, grid voltage waveforms, and current waveforms under these unbalance conditions are illustrated in Figure 13a–c. In the $-5\%$ interval, all controllers maintain stable DC-bus regulation, with $V_{dc,pp}$ remaining below 0.322%. The T1-FLC provides the smallest ripple with $V_{dc,pp}=0.200\%$, followed by the PI controller ($0.243\%$), while the T3-FLC yields a ripple of $0.264\%$. At the same time, the T3-FLC achieves the best current quality, with THD_i$=8.309\%$, compared with 10.698% for the T1-FLC and 12.774% for the PI controller.

Table 9. Performance of the controllers under unbalanced grid conditions.

Metric	0.2–0.4 s (−5%)			0.4–0.6 s (+5%)
	PI	T1-FLC	T3-FLC	PI	T1-FLC	T3-FLC
$V_{dc,pp}$ (%)	0.243	0.200	0.264	0.322	0.204	0.271
THDi (%)	12.774	10.698	8.309	12.459	10.010	12.137
PFSS	0.993	0.994	0.993	0.992	0.993	0.993
${\overline{\eta }}_{ss}$ (%)	98.95	98.95	98.95	98.97	98.98	98.97

Figure 13. Controller performance under voltage unbalance conditions: (a) DC-bus voltage response, (b) three-phase grid voltage waveforms, and (c) three-phase grid current waveforms.

In the $+5\%$ interval (0.4–0.6 s), the T1-FLC again provides the lowest DC-bus ripple, with $V_{dc,pp}=0.204\%$, whereas the PI and T3-FLC controllers yield $0.322\%$ and $0.271\%$, respectively. In this interval, the T1-FLC also attains the lowest current distortion, with THD_i $=10.010\%$, while the PI and T3-FLC controllers result in THD_i $=12.459\%$ and 12.137%. Across both intervals, all controllers preserve a high PF, with PF_ss in the range 0.992–0.994, and very similar efficiencies, with ${\overline{\eta }}_{ss}$ between 98.95% and 98.98%. Under voltage unbalance, controller-dependent differences mainly originate from how the outer-loop voltage corrections shape the inner d–q current tracking error. In the negative-unbalance interval, T3-FLC yields the lowest THD_i because the type-3 uncertainty-aware inference provides more effective current regulation under asymmetric grid perturbations. T1-FLC achieves the smallest $V_{dc,pp}$ across intervals, indicating smoother DC-bus voltage correction. PI shows the weakest overall PQ performance since fixed gains cannot fully adapt the transient current waveform to asymmetric disturbances, resulting in higher harmonic distortion. In all cases, PF stays nearly unchanged because the q-axis current reference is maintained at zero and the decoupled control structure preserves reactive power compensation.

PF_ss remains close to unity across controllers due to the d–q current control structure and the zero q-axis reference, meaning that reactive-power compensation is not the main differentiator. The differences in THD_i reflect how each controller’s strategy (fixed-gain PI versus fuzzy type-1 versus type-3 uncertainty-aware outer-loop regulation) shapes the transient and steady-state current waveform through $i_d^{*}$ tracking. PI often provides lower THD_i in some disturbance regimes, while fuzzy controllers primarily improve DC-bus ripple and voltage damping. T3-FLC offers a practical balance by achieving fast, well-damped voltage recovery while maintaining competitive THD and PF across the tested scenarios.

The obtained grid-side current THD_i values, ranging from 4% to 13% across different operating cases, demonstrate compliance with major international PQ standards. According to IEEE Std. 519 [57], the recommended current THD limit at the point of common coupling for low-voltage systems ($V\le 1.0$ kV) is 8.0%; the current harmonic limits (expressed as total demand distortion) depend on the short-circuit to load current ratio, and the present THD_i values fall within ranges typically permitted for similar applications. The IEC 61000-3-2 standard [58] sets harmonic current emission limits for equipment connected to public low-voltage networks, with limits on individual harmonic orders that generally correspond to THD_i levels well below 20% for most equipment classes. The minimum THD_i value of 4% achieved in this study aligns with the performance of state-of-the-art PWM rectifiers reported in the literature [44,49], where values below 5% are considered indicative of effective harmonic mitigation.

5.4. Discussion

This section provides a consolidated discussion of the main findings of the study, examining the performance of the proposed T3-FLC in relation to conventional PI and T1-FLC controllers and situating the results within the broader context of the literature summarized in Table 10.

Table 10. Comparative summary of different control strategies for three-phase PWM rectifiers.

Study	Controller	Uncertainty	Online	Test Conditions	Dynamic Response Metrics	PQ Metrics
[45]	DPC–SVM	n/a	No	Transient & steady.	Not reported.	THD, PF
[59]	IT2–FNS (outer $V_{dc}$)	IT2	Yes	Transient/steady tests.	Rise time; overshoot/undershoot; settling time.	THD, PF; Sag/swell.
[44]	PD–IT2–FNN	IT2	Yes	Set-point step; load step; set-point under load.	Settling time; over/undershoot; steady-state error.	THD, PF.
[60]	IT2–FLC + DPC–SVM	IT2	No	Reference step; load variation.	Waveform-based tracking: $V_{dc}$ and $P/Q$.	THD, PF.
[61]	MP–DPC/MPC	n/a	No	Balanced & unbalanced grid; power-step tracking.	Fast dynamics at fixed $f_s$	THD; power ripple.
[62]	Modulated MPC	n/a	No	DC-bus reference step; load change.	$V_{dc}$ tracking; $P/Q$ tracking.	THD.
[63]	Multifunctional MPC + carrier-based PWM	n/a	No	Grid-mode transitions; symmetrical fault.	Fast, well-damped P steps; $V_{dc}$ error; response time.	n/a
[64]	Adaptive backstepping ± SMC	n/a	Yes	Parameter-variation tests.	Overshoot; settling time.	n/a
[65]	Passivity-based (PCH) + PI	n/a	No	$V_{dc}$ tracking; load change.	Rise time; settling time.	THD, PF.
This study (2026)	T3–FLC (outer $V_{dc}$) + PI $d-q$ inner	Type-3 (3D MFs; interval $\alpha$-cut)	Yes	Reference tracking; load variation; regenerative mode; H5/H7 cases; Sag/swell, unbalance	Rise time; overshoot/undershoot; settling time; $V_{dc}$ ripple (pp).	THD; PF; efficiency.

n/a: Not applicable; “Yes” and “No” in the “Online” column indicate the presence or absence of real-time adaptation capabilities.

5.4.1. Comparative Analysis of Dynamic Performance

Across all dynamic scenarios—including constant-reference operation, reference tracking, load disturbances, and regenerative events—the T3-FLC consistently demonstrates superior transient behavior. The controller achieves shorter settling and recovery times, well-damped overshoot and undershoot characteristics, and robust voltage regulation in the presence of abrupt operating changes. Compared with the PI controller, which exhibits large overshoots and significantly longer recovery durations, and the T1-FLC, which shows moderate improvements, the T3-FLC offers a more favorable balance between dynamic speed and transient stability. These results indicate that the additional modeling flexibility provided by the T3-FLC enhances the effectiveness of the outer control loop.

5.4.2. Power Quality-Oriented Evaluation Under Disturbances

The disturbance scenarios—including harmonic injection, voltage sag, swell, and unbalance—highlight complementary strengths among the controllers. The fuzzy controllers, particularly the T1-FLC, achieve lower DC-bus voltage ripple under distorted or fluctuating grid conditions, while the PI controller retains a modest advantage in minimizing current THD in several cases. The T3-FLC provides the most consistent compromise, maintaining low ripple, competitive THD performance, and consistently high PF and efficiency across all disturbance types. The controller’s capability to preserve PQ under both negative and positive voltage deviations further underscores its robustness in practical grid environments.

5.4.3. Positioning Within Existing Literature

The comparative survey in Table 10 shows that most existing strategies—such as DPC–SVM, MPC-based methods, or type-2 fuzzy/neural schemes—tend to focus on either fast dynamics, uncertainty handling, or specific disturbance types. In contrast, the present study evaluates a unified controller design across a broad spectrum of operating scenarios, including regenerative operation and multiple grid disturbances. The proposed T3-FLC offers a middle ground: enhanced nonlinearity-handling capability compared with type-1 and PI controllers, yet with a simpler structure and lower implementation burden than MPC or high-dimensional IT2/IT3 counterparts. This positions the T3-FLC as an effective and practical alternative for real-world PWM rectifier applications.

5.5. Computational Complexity and Real-Time Feasibility

To address practical deployability, the computational burden of the three controllers (PI, T1-FLC, and T3-FLC) was analyzed using operation-count and memory-footprint criteria, and then interpreted with respect to the implemented sampling period ($T_s=50$ µs). For the proposed T3-FLC, two inputs (e and $\Delta e$), seven linguistic terms per input, and a $7\times 7$ rule base ($R=49$) are used. In each control update, the controller computes four membership grades per term (upper–upper, upper–lower, lower–upper, and lower–lower), evaluates rule firing strengths by product t-norm, and performs normalized weighted sums for type-reduction/defuzzification. With $K=1$ horizontal slice in the present implementation, the output stage is simplified to averaging two interval endpoints.

The PI controller performs a few arithmetic operations per sample (proportional and integral terms, anti-windup), typically on the order of 10–20 floating-point operations. The T1-FLC requires membership evaluations, rule firing, and defuzzification; for a comparable $7\times 7$ rule base, this corresponds to roughly 80–120 operations per sample. The T3-FLC adds type-3 membership computations (four bounds per term) and type-reduction, increasing the per-sample cost to approximately 250–400 operations. Table 11 summarizes the estimated computational burden of the three controllers. Execution time on a typical 100–200 MHz embedded processor is on the order of 1–3 µs for PI, 8–15 µs for T1-FLC, and 20–40 µs for T3-FLC, all well below the 50 µs sampling period. Memory usage is modest for all controllers; the T3-FLC parameter set (MF centers, spreads, slice exponents, rule consequents) fits in approximately 2–4 kB. Given the selected switching/sampling settings ($f_c=5$ kHz, $T_s=50$µs), the above complexity remains feasible for standard industrial controllers. Therefore, although the T3-FLC is computationally more demanding than PI and T1-FLC, its real-time implementation is practical for embedded PWM rectifier control.

Table 11. Estimated computational burden of PI, T1-FLC, and T3-FLC controllers.

Metric	PI	T1-FLC	T3-FLC
Operations per sample	∼15	∼100	∼300
Parameter memory	<0.1 kB	∼1 kB	∼3 kB
Execution time @ 150 MHz	∼2 µs	∼10 µs	∼25 µs
Compatible with $T_s=50$µs	Yes	Yes	Yes

Limitations and Future Work

A key limitation of the present study is that the evaluation was performed entirely through simulation. Although a comprehensive range of operating scenarios was considered, experimental validation is required to assess the controller’s behavior under non-ideal conditions such as measurement noise, parameter variations, and switching delays. A further limitation is that the rectifier plant is represented using a control-oriented averaged model to enable simplified controller design and validation; in this modeling choice, switching losses and converter nonlinearities (e.g., semiconductor conduction drops, switching energy dissipation, and dead-time effects) are neglected when deriving the state equations. While this approximation preserves the core DC-bus and synchronous d–q current dynamics used for control, it may affect the fidelity of loss- and efficiency-related predictions and high-frequency nonlinear effects, which can slightly modify voltage ripple and THD under more extreme operating conditions. Future work will focus on hardware-in-the-loop verification and laboratory prototyping that incorporates device-level parameters and dead-time. Additional comparisons with adaptive and predictive control schemes may also provide further insights into the scalability and generality of the T3-FLC approach.

6. Conclusions

This study introduced a T3-FLC-based control strategy for regulating the DC-bus voltage of a three-phase PWM rectifier and benchmarked it against conventional PI and T1-FLC controllers. The evaluation was carried out using a unified set of dynamic and PQ metrics under constant-reference operation, reference tracking, load disturbances, regenerative operation, and several grid-disturbance scenarios. The main findings are summarized below.

• Under nominal and reference-tracking conditions, T3-FLC reduced settling time from 74.85 ms (PI) to 15.65 ms and overshoot from 13.58% to 0.18%, indicating a faster and better-damped transient response. For 200 V to 250 V reference steps, it also delivered lower rise/fall times than PI and maintained overshoot/undershoot near 1%.
• In load-disturbance and regenerative cases, T3-FLC consistently achieved the fastest recovery and the smallest voltage deviations. For 40 $\Omega$ ↔ 20 $\Omega$ load steps, recovery remained below 8 ms, and in regenerative operation, overshoot/undershoot were limited to about 2.675%/3.128%, versus more than 11%/17% for PI.
• Under distorted and unbalanced grid conditions, all controllers maintained high PF (0.992–0.997) and efficiencies near 99%, while fuzzy controllers reduced DC-bus ripple relative to PI. In harmonic injection, T3-FLC kept ripple near 0.3% (vs. ∼0.5% for PI), and under $\pm 5\%$ unbalance, it provided the lowest THD_i in the negative-unbalance interval.

Additionally, the computational analysis confirms that the T3-FLC can be implemented in real time on typical embedded platforms, supporting its deployability in practical PWM rectifier applications. The T3-FLC delivered the most favorable compromise among the three controllers, combining a fast dynamic response, strong disturbance rejection, and robust PQ performance in a wide range of operating scenarios. These results indicate that T3-FLC is a promising control solution for three-phase PWM rectifiers.