Search Results (34)

Quartz wafer dicing technologies primarily rely on mechanical cutting and etching processes. Mechanical cutting is easy to generate the micro-cracks along the wafer edges, which compromises component precision. Furthermore, etching processes are associated with long processing times, high manufacturing costs, and environmental concerns. To address these limitations, this study proposes an electrochemical discharge cutting machining (ECDCM) method using a micro-tungsten carbide helical electrode performing orbital circular cutting (OCC) to evaluate the feasibility and optimization of quartz wafer dicing. Experimental studies were conducted to evaluate the effects of applied voltage, pulse duration, Z-axis feed rate, and duty factor on slot width, slot depth, slot surface quality and tool electrode wear. The results demonstrate that employing an OCC of micro-electrode facilitates the efficient flow of electrolyte into the machining zone, thereby enhancing discharge stability and slot quality. Compared to circular path cutting (CPC) with a rotating electrode, the proposed method reduces machining time by nearly four times and decreases material loss during circular quartz wafer cutting by approximately 50%. These findings indicate that the proposed machining approach provides high efficiency and high-quality quartz wafer cutting. Full article

To investigate how the process parameters of ultra-thin diamond grinding wheel dicing affect the dicing quality of silicon carbide (SiC) wafers, single-factor experiments were designed. This study examined the influence of key process parameters, including spindle speed, feed rate, and first dicing depth, on the maximum chip width on the front side W₁ and the maximum chip width on the back side W₂, thereby determining their optimal parameter ranges. Subsequently, a quadratic polynomial prediction model was established using response surface analysis to analyze the interactive effects among the grinding wheel dicing process parameters. Finally, the prediction model was optimized using the genetic algorithm NSGA-II, and the optimal parameter combination for the two response variables was determined: a spindle speed of 31,960 r/min, a feed rate of 2.0019 mm/s, and a first dicing depth of 197.51 μm, yielding an average W₁ of 4.8852 μm and W₂ of 18.5360 μm. The relative errors between the predicted and average experimental values are 2.83% for W₁ and 4.43% for W₂. Both errors are below 5%, confirming the validity of the model. Therefore, the model serves as a practical reference for planning subsequent dicing processes using ultra-thin diamond grinding wheels. Full article

To address the critical challenges of edge chipping and poor processing quality in sapphire precision dicing, this paper proposes a femtosecond laser filamentation-guided dicing technology. By systematically investigating the influence of pulse overlap rate, energy, and scan counts on damage evolution, the physical differences between 343 nm UV and 515 nm visible lasers in suppressing plasma shielding and breaking through processing saturation limits are revealed. The results indicate that an extremely high pulse overlap rate (>98%) significantly inhibits lateral energy dissipation and drives the efficient propagation of the filament deep along the optical axis; furthermore, the 343 nm laser demonstrates superior removal rates and localisation compared to the 515 nm laser. Using super-resolution imaging, the precision cleavage cross-section is clearly categorised into four evolutionary stages: general ablation, filament ablation, transition, and mechanical cleavage. To mitigate morphological degradation induced by multiple scans, a sacrificial-layer-assisted strategy is innovatively proposed to achieve spatial damage transfer and in situ self-polishing, effectively eliminating longitudinal damage striations and residual stress-induced hackles. Finally, taper-free, high-precision separation of 1 mm × 450 μm micro-units is successfully achieved on a 220-μm-thick sapphire wafer. This technology not only achieves ultra-low-loss dicing but also establishes a highly efficient, contamination-free in situ characterisation paradigm for buried structures in hard and brittle materials. Full article

Dicing is an important process in the packaging segment of the semiconductor manufacturing process, and due to the high hardness and brittleness of 4H-SiC wafers, they are prone to crack propagation and severe chipping during the dicing process. To reduce chipping defects, this study investigates the effects of key process parameters on the chipping behavior of 4H-SiC wafers, as well as the associated chipping formation and material removal mechanisms during dicing. Firstly, a spindle current measurement scheme was designed to indirectly reflect changes in grinding force during the cutting process, and the change in the cutting process in a single pass was analyzed. Secondly, experiments controlling single-factor variables were designed to explore the influence of laws of process parameters, including depth of cut, spindle speed, feed speed, and the dicing blade parameter, abrasive grain size, on the quality of chipping, and the optimal process parameters were obtained. Thirdly, the morphology of the 4H-SiC cutting contact arc area, front–back chipping, and sidewalls was analyzed in order to investigate the chipping formation and material removal mechanism. This study contributes to a fundamental understanding of material removal mechanisms during the cutting of 4H-SiC wafers and other advanced semiconductor materials and provides guidance for optimizing cutting process parameters. Full article

The rapid advancement of high-performance electronics has intensified the demand for wide-bandgap semiconductor materials capable of operating under high-power and high-temperature conditions. Among these, silicon carbide (SiC) has emerged as a leading candidate due to its superior thermal conductivity, chemical stability, and mechanical strength. However, the high cost and complexity of SiC wafer fabrication, particularly in slicing and exfoliation, remain significant barriers to its widespread adoption. Conventional methods such as wire sawing suffer from considerable kerf loss, surface damage, and residual stress, reducing material yield and compromising wafer quality. Additionally, techniques like smart-cut ion implantation, though capable of enabling thin-layer transfer, are limited by long thermal annealing durations and implantation-induced defects. To overcome these limitations, ultrafast laser-based processing methods, including laser slicing and stealth dicing (SD), have gained prominence as non-contact, high-precision alternatives for SiC wafer exfoliation. This review presents the current state of the art and recent advances in laser-based precision SiC wafer exfoliation processes. Laser slicing involves focusing femtosecond or picosecond pulses at a controlled depth parallel to the beam path, creating internal damage layers that facilitate kerf-free wafer separation. In contrast, stealth dicing employs laser-induced damage tracks perpendicular to the laser propagation direction for chip separation. These techniques significantly reduce material waste and enable precise control over wafer thickness. The review also reports that recent studies have further elucidated the mechanisms of laser–SiC interaction, revealing that femtosecond pulses offer high machining accuracy due to localized energy deposition, while picosecond lasers provide greater processing efficiency through multipoint refocusing but at the cost of increased amorphous defect formation. The review identifies multiphoton ionization, internal phase explosion, and thermal diffusion key phenomena that play critical roles in microcrack formation and structural modification during precision SiC wafer laser processing. Typical ultrafast-laser operating ranges include pulse durations from 120–450 fs (and up to 10 ps), pulse energies spanning 5–50 µJ, focal depths of 100–350 µm below the surface, scan speeds ranging from 0.05–10 mm/s, and track pitches commonly between 5–20 µm. In addition, the review provides quantitative anchors including representative wafer thicknesses (250–350 µm), typical laser-induced crack or modified-layer depths (10–40 µm and extending up to 400–488 µm for deep subsurface focusing), and slicing efficiencies derived from multi-layer scanning. The review concludes that these advancements, combined with ongoing progress in ultrafast laser technology, represent research opportunities and challenges in transformative shifts in SiC wafer fabrication, offering pathways to high-throughput, low-damage, and cost-effective production. This review highlights the comparative advantages of laser-based methods, identifies the research gaps, and outlines the challenges and opportunities for future research in laser processing for semiconductor applications. Full article

The review is intended to systematize the latest achievements and the most promising methods in polycrystalline diamond saw blade dressing used for dicing Si and SiC wafers. Dicing, or die singulation, is important in IC assembly, and the quality of the die edges influences the final product quality. Reducing chipping size and width has been a scientific problem over the last few decades. Many techniques were proposed to solve it. The most practical solutions involved optimizing processing factors and cutting direction in accordance with the crystallographic structure of the wafers, since silicon and silicon carbide are hard and brittle materials with low fracture toughness, high hardness, and high thermal conductivity. Wear of the PCD saw blade is also a contributing factor to the formation of chipping and cracks. Dressing allows the bond material removal and diamond grain liberation, where grit size plays a critical role. Dressing techniques were divided into two groups depending on the nature of the exposure, and a combined technique of dressing–coating–redressing was also observed. The less significant chipping size effect was observed for the combined technique in dicing Si wafers when the effect of the techniques based on the mechanical and electrophysical exposures was more significant. Full article

The traditional semiconductor packaging training process is time-consuming and carries the risk of damaging precision equipment due to improper operation. Additionally, the retirement of experienced trainers has led to loss of specialized training and testing expertise. To address these challenges, digital twin technology is applied to training packaging engineers. We conducted an empirical study at the packaging production line of the Minghsin University of Science and Technology to address talent training bottlenecks and imbalances between supply and demand. First, an integrated software and hardware system was designed by combining digital twin and mixed reality (MR). The development process of the digital twin system for the wafer-dicing machine includes on-site visits, machine operation instructions, certification content development, expert validity construction, small-scale testing and modifications. We compared the pre- and post-experiment scores of industry experts to evaluate the operation time of five participants and their feedback. Digital twin and MR for simulated training increased proficiency in operation. The digital twin training and certification model developed in this study improved students’ pass rates in certification exams. Full article

The demand for integrated circuit (IC) chips has risen markedly across various industries in conjunction with advancements in global technology. Prior to packaging, IC elements undergo several processes, including wafer dicing, wire bonding, and encapsulation. Scanning Acoustic Tomography (SAT) effectively analyzes the internal structures of integrated circuit products, thereby preventing the supply of defective components, including chip fractures, delamination, voids, and adhesion issues. The study aims to reduce operator eye strain, enhance productivity, and minimize employee turnover rates by proposing the use of convolutional neural networks (CNN) to develop a predictive model for automating defect detection in integrated circuit (IC) products within SAT images, replacing traditional visual inspections. To enhance the accuracy of the CNN model, we implement the flood-fill algorithm as the primary augmentation strategy and create an image augmentation model in Python. This method produces a training set that accurately reflects the true characteristics of defects, thereby mitigating the problem of limited defect data and ensuring the model is trained on reliable information. The incorporation of various rates and scaling factors into SAT defect images, along with the manipulation of the original defect, contributes to the development of a robust dataset suitable for real-world testing. The CNN model is trained using various batch sizes, resulting in customized training datasets and predictive models to improve accuracy. Key findings indicate that employing 40× augmentation alongside a batch size of 32 enhances the model’s performance, yielding a missed detection rate below 0.4% and a false alarm rate of 0.1%. This model offers an improved solution to the issue of manual inspections on assemblies, thereby alleviating operator stress and establishing a robust framework for automated integrated circuit quality management. Full article

The key equipment for performing aerodynamic testing of objects, such as road and railway vehicles, aircraft, and wind turbines, as well as stationary objects such as bridges and buildings, are multichannel pressure measurement instruments (pressure scanners). These instruments are typically based on arrays of separate pressure sensors built in an enclosure that also contains temperature sensors used for temperature compensation. However, there are significant limitations to such a construction, especially when increasing requirements in terms of miniaturization, the number of pressure channels, and high measurement performance must be met at the same time. In this paper, we present the development and realization of an innovative MEMS multisensor chip, which is designed with the intention of overcoming these limitations. The chip has four MEMS piezoresistive pressure-sensing elements and two resistive temperature-sensing elements, which are all monolithically integrated, enabling better sensor matching and thermal coupling while providing a high number of pressure channels per unit area. The main steps of chip development are preliminary chip design, numerical simulations of the chip’s mechanical behavior when exposed to the measured pressure, final chip design, fabrication processes (photolithography, thermal oxidation, diffusion, layer deposition, micromachining, anodic bonding, and wafer dicing), and electrical testing. Full article

Silicon carbide (SiC) stands out for its remarkable hardness, thermal stability, and chemical resistance, making it a critical material in advanced engineering applications, particularly in power electronics, aerospace, and semiconductor industries. However, its inherent brittleness and relatively low fracture toughness pose significant challenges during precision manufacturing processes, particularly during the laser stealth dicing—a pivotal process for wafer separation. This review provides a comprehensive analysis of the fracture toughness of SiC, exploring its dependence on microstructural factors, such as grain size, fracture mode (transgranular vs. intergranular), and toughening mechanisms, including the crack deflection and bridging. The effects of temperature and mechanical anisotropy on the fracture resistance of SiC are discussed. Particular attention is given to how SiC’s low fracture toughness and brittle nature affect the controlled crack propagation critical to the dicing process. The review synthesizes key experimental findings from various fracture-toughness measurement techniques, highlighting their relevance for optimizing the laser processing parameters. By linking the fracture mechanics of SiC to its performance in laser stealth dicing, this review provides critical guidance for enhancing the process, ensuring greater efficiency and reliability in SiC wafer separation for advanced technologies. Full article

As stacking technologies, such as 2.5D and 3D packages, continue to accelerate in advanced semiconductor components, the singulation and thinning of Si wafers are becoming increasingly critical. Despite their importance in producing thinner and more reliable Si chips, achieving high reliability remains a challenge, and comprehensive research on the effects of these processing techniques on Si chip integrity is lacking. In this study, the impacts of wafer thinning and singulation on the fracture strength of Si wafers were systematically compared. Three different grinding processes, namely fine grinding, poly-grinding, and polishing, were used for thinning, and the resulting surface morphology and roughness were analyzed using scanning electron microscopy and an interferometer. In addition, the residual mechanical stress on the wafer surface was measured using Raman spectroscopy. The fracture strength of Si wafers and chips was assessed through three-point bending tests. Singulation, including blade dicing, laser dicing, and stealth dicing, was evaluated for its impact on fracture strength. Among these processes, polishing for wafer thinning exhibited the lowest full-width half maximum and intensity ratio of Raman shifts (I480/I520), indicating minimal residual stress and surface defects. Consequently, Si wafers and chips processed through polishing demonstrated the highest fracture strength. Moreover, the 60 µm thick Si wafers and chips showed the highest fracture strength compared with those with thicknesses of 90 and 120 µm, possibly because of the increased flexibility, which mitigates stress. Among the singulation methods, stealth dicing yielded the highest fracture strength, outperforming blade and laser dicing. The combination of wafer thinning via polishing and singulation via stealth dicing presents an optimal solution for producing highly reliable Si chips for 2.5D and 3D packaging. These findings may be valuable in selecting optimal processing technologies for high-reliability Si chip production in industrial settings. Full article

The key technologies for the ultrathin small outline package (TSOP) of large-sized high-speed chips have been designed and developed in this paper. The designing techniques, such as a 25 µm precise positioning dice attaching technique, a lead frame unit structure without a base island, and a lead co-plane layout inside the frame, were developed. The TSO package outline with a large number of leads, a frame unit arrangement, and a frame distribution with a base island and without one were improved. The technological problems, including the reduction in thickness, wafer cutting, chip sticking bonding, and plastic sealing, were successfully solved. The designed large-sized package products have many advantages, such as high availability, low cost, high reliability, and a short production cycle. This package technique can be widely used in various intellectual application regions. Full article

Our previous study utilized importance analysis, random forest, and Barnes–Hut t-SNE dimensionality reduction to analyze critical dicing parameters and used bidirectional long short-term memory (BLSTM) to predict wafer chipping occurrence successfully in a single dicing machine. However, each dicing machine of the same type may produce unevenly distributed non-IID dicing signals, which may lead to the undesirable result that a pre-trained model trained by dicing machine #1 could not effectively predict chipping occurrence in dicing machine #2. Therefore, regarding the model robustness, this study introduces an ensemble meta-learning-based model that can evaluate many dicing machines for chipping prediction with high stability and accuracy. This approach constructs several base learners, such as the hidden Markov model (HMM), the variational autoencoder (VAE), and BLSTM, to form an ensemble learning. We use model-agnostic meta-learning (MAML) to train and test the ensemble learning model by several prediction tasks from machine #1. After MAML learning, we call the trained model a meta learner. Then, we successfully apply a retrieved data set from machine #2 to the meta learner for training and testing wafer chipping occurrence in this machine. As a result, our contribution to the robust chipping prediction on cross-machines can improve the yield of wafer dicing with a prediction accuracy of 93.21%, preserve the practical wearing of dicing kerfs, and significantly cut wafer manufacturing costs. Full article

The existing instruments for aerodynamic pressure measurements are usually built around an array of discrete pressure sensors, placed in the same housing together with a few discrete temperature sensors. However, this approach is limiting, especially regarding miniaturization, sensor matching, and thermal coupling. In this work, we intend to overcome these limitations by proposing a novel MEMS multisensor chip, which has a monolithically integrated matrix of four piezoresistive MEMS pressure-sensing elements and two resistive temperature-sensing elements. After finishing the preliminary chip design, we performed computer simulations in order to assess its mechanical behavior when measured pressure is applied. Subsequently, the final chip design was completed, and the first batch was fabricated. The used technological processes included photolithography, thermal oxidation, diffusion, sputtering, micromachining (wet chemical etching), anodic bonding, and wafer dicing. Full article

A new cleaning agent for silicon contamination in the wafer dicing process was formulated in this research. Ammonium bifluoride was introduced as the main ingredient in the formula, and MSA and sulfuric acid were added as the solvent and buffer solution against metal corrosion. It was confirmed that the new formula cleaning agent could be used in the cleaning of silicon contamination from dicing. Silicon contamination is common in the wafer dicing process and consists of silicon powder and relevant metal particles during cutting, all of which are mixed with some adhesive residues. These contaminating particles on the IC surface are exposed to cleaning agents. However, while it is imperative to clean the wafer, the exposed surface is also vulnerable to damage from the solution. This further complicates the procedure because there is currently no ideal cleaning agent for the process. Our proposed formula hopefully provides an ideal chemical for use in wafer cleaning (SC-1, SC-2, BOE), since it uses a less toxic compound, ammonium bifluoride, which yielded good results during our experiments. Full article