Search Results (685)

The integration of complementary metal–oxide–semiconductor (CMOS) and micro-electromechanical systems (MEMSs) technologies for miniaturized biosensor fabrication enables unprecedented spatiotemporal resolution in monitoring the bioelectrical activity of the nervous system. Wafer-level CMOS technology incurs high costs, but multi-project wafer (MPW) runs mitigate this by allowing multiple users to share a single wafer. Still, monolithic CMOS biosensors require specialized surface materials or device geometries incompatible with standard CMOS processes. Performing MEMS post-processing on the few square millimeters available in MPW dies remains a significant challenge. In this paper, we present a MEMS post-processing workflow tailored for CMOS dies that supports both surface material modification and layout shaping for intracortical biosensing applications. To address lithographic limitations on small substrates, we optimized spray-coating photolithography methods that suppress edge effects and enable reliable patterning and lift-off of diverse materials. We fabricated a needle-like, 512-channel simultaneous neural recording active pixel sensor (SiNAPS) technology based neural probe designed for integration with optical fibers for optogenetic studies. To mitigate photoelectric effects induced by light stimulation, we incorporated a photoelectric shield through simple modifications to the photolithography mask. Optical bench testing demonstrated >96% light-shielding effectiveness at 3 mW of light power applied directly to the probe electrodes. In vivo experiments confirmed the probe’s capability for high-resolution electrophysiological measurements. Full article

FLASH radiotherapy requires real-time, non-invasive beam monitoring systems capable of operating under ultra-high dose rate (UHDR) conditions without perturbing the therapeutic beam. In this work, we characterized the extraction system of Supersonic Gas Curtain-based Ionization Profile Monitor (SGC-IPM) for its capabilities as a transverse beam profile and position monitor for FLASH protons. The monitor utilizes a tilted gas curtain intersected by the incident beam, leading to the generation of ions that are extracted through a tailored electrostatic field, and detected using a two stage microchannel plate (MCP) coupled to a phosphor screen and CMOS camera. CST Studio Suite was employed to conduct electrostatic and particle tracking simulations evaluating the ability of the extraction system to measure both beam profile and position. The ion interface, at the interaction region of proton beam and gas curtain, was modeled with realistic proton beam parameters and uniform gas curtain density distributions. The ion trajectory was tracked to evaluate the performance across multiple beam sizes. The simulations suggest that the extraction system can reconstruct transverse beam profiles for different proton beam sizes. Simulations also supported the system’s capability as a beam position monitor within the boundary defined by the beam size, the dimensions of the extraction system, and the height of the gas curtain. Some simulation results were benchmarked against experimental data of 28 MeV proton beam with 70 nA average beam current. This study will further help to optimize the design of the extraction system to facilitate the integration of SGC-IPM in medical accelerators. Full article

This paper reports the results of a system-level total ionizing dose (TID) effect simulation study on a SMIC 130 nm LEON2 processor. Firstly, the device-level simulations of the 130 nm NMOS transistors are performed using the Sentaurus TCAD software to analyze the effects of a bias condition, channel width, and irradiation dose on a TID-induced leakage current. Based on the TCAD simulation results, a Verilog-A-based compact model is developed for NMOS transistors to describe the TID-induced leakage current, and it is then embedded into target nodes of the SPICE netlist for the LEON2 processor, enabling system-level TID simulations. The simulation results reveal the processor’s failure threshold and corresponding failure mechanism; meanwhile, the increase in the power supply current with the irradiation dose is also observed. The research reported in this paper can provide beneficial guidance for radiation performance evaluation and radiation hardening by design (RHBD) in 130 nm bulk CMOS processors. Full article

A lens-coupled high-speed X-ray camera, “Hayaka”, was developed for quick imaging of X-ray absorption fine structure (XAFS) and time-resolved high-speed computed tomography (CT) using synchrotron radiation (SR). This camera is a lens-coupled type, composed of a scintillator, an imaging lens system, and a high-speed visible light sCMOS, capable of imaging with a minimum exposure time of 1 μs and a maximum frame rate of 5000 frames/s (fps). A feasibility study using white and monochromatic SR at the beamline BL07 of the SAGA Light Source showed that fine X-ray images with a spatial resolution of 77 μm can be captured with an exposure time of 10 μs. Furthermore, quick imaging XAFS, combined with high-speed energy scanning of a small Ge double crystal monochromator of the same beamline, enabled spectral image data to be acquired near the Cu K-edge in a minimum of 0.5 s. Additionally, an in coquendo 4DCT (time-resolved 3D observation of cooking processes) observation combined with a high-speed rotation table revealed the boiling process of Japanese somen noodles over 150 s with a time resolution of 0.5 s. Full article

The designs of lossless data compression architectures create a natural trade-off between throughput, power consumption, and compression efficiency, making it difficult for designers to identify an optimal configuration that satisfies all three criteria. This paper proposes a Configurable Dual-Path Huffman/Arithmetic Encoder (CDP-HAE), which offers an architecture that supports the use of shared preprocessing, parallel path encoding using Huffman and Arithmetic, as well as selectable output. The CDP-HAE’s design prevents the waste of excess bandwidth by sending only one selected bit stream at a time. This also enables adaptation to the dynamically changing statistical characteristics of the input data. CDP-HAE’s architecture underwent ASIC synthesis in 90 nm CMOS technology and is implemented on an Artix-7 (A7-100T) using the Vivado EDA tool, confirming the scalability of the architecture to both devices. Synthesis results show that CDP-HAE improves operating frequency by 28.6% and reduces critical path delay by 27.2% compared to reference designs. Additionally, the dual-path design has a slight increase in area; the area utilization remains within reasonable limits. Power analysis indicates that optimizing logic sharing and minimizing switching activity reduces total power consumption by 34.4%. Compression tests show that the CDP-HAE delivers performance comparable to that of a conventional Huffman Encoder using application-specific datasets. Furthermore, the proposed CDP-HAE achieves performance comparable to conventional Huffman encoders on application-specific datasets, while providing up to 10% improvement in compression ratio over Huffman-only encoding. Full article

This paper describes the radio-frequency (RF) characteristics of stacked metal–insulator–metal (MIM) capacitors used in RF CMOS technology. To ensure accurate analysis, various de-embedding methods for stacked MIM capacitors were verified, and an improved RF model was constructed accordingly. To develop an equivalent circuit for the improved RF model by analyzing the RF characteristics of stacked MIM capacitors, we compared de-embedding methods for measured stacked MIM capacitors: one-step (open-pattern or short-pattern) de-embedding and two-step (combined open-pattern and short-pattern) de-embedding. For the analysis of stacked MIM capacitors, at least two-step de-embedding was used, while for precise de-embedding, three-step de-embedding using a thru pattern was employed. Based on the measured values obtained using these two-step de-embedding methods, a modified equivalent circuit was constructed. This circuit was analyzed based on various parameters, including MIM capacitance, quality factor, S-parameter, and Y-parameter, and the results were comparatively examined. The findings highlight outstanding accuracy of the modified model, which is maintained even in high frequency bands. Full article

This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ($P_{sat}$) of 20.2 dBm, and a maximum large-signal gain ($G_{max}$) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes. Full article

Atmospheric turbulence, quantified by the refractive index structure parameter (${C_n}^2$), degrades the performance of optical systems. Reliable ${C_n}^2$ estimation is critical for free-space optical communication, remote sensing, and astronomy. This study compares frame-based and event-based approaches to turbulence strength estimation. A high-speed CMOS camera (180/90/30 frames per second (FPS)) and an event camera were deployed along a 300 m outdoor path, with a scintillometer providing ground truth. Event streams were segmented into 5 s windows, features were extracted, and predictions were made using an Extreme Gradient Boosting regressor (XGBoost). A hybrid model was also tested, combining CMOS-based predictions with event features. Results show that CMOS accuracy is strongly dependent on frame rate, with diminishing returns beyond 90 FPS under weak turbulence. Event-based models achieved higher correlation with ground truth in strong turbulence but produced larger errors in weak regimes. The hybrid approach yielded the best overall performance in moderate-to-strong turbulence, reducing mean estimation error by ~35% compared to CMOS-only at 180 FPS. These findings demonstrate the complementary strengths of frame and event modalities. Frame cameras provide stability in weak turbulence, while event sensors capture fast fluctuations under stronger conditions. Together, they enable more robust ${C_n}^2$ estimation and motivate further research into advanced hybrid sensing strategies for operational turbulence monitoring. Full article

A deterministic platform for engineering epitaxial strain in CaMnO_3-δ (CMO) thermoelectric thin films is demonstrated using pulsed laser deposition, enabling precise control of the interplay between strain state and oxygen vacancy formation. High-quality epitaxial CMO films are grown on four different single crystalline substrates, which impose fully relaxed, partially relaxed, low tensile, and high tensile strain states, respectively. Increasing tensile strain induces a monotonic expansion of the unit cell volume and a systematic rise in oxygen vacancy concentration. Oxygen vacancies increase carrier concentration but decrease mobility due to enhanced scattering. Reducing tensile strain suppresses scattering of electrons by oxygen vacancies and increases both electrical conductivity (σ) and the Seebeck coefficient (S), mitigating the conventional inverse relationship between S and σ. Fully relaxed films exhibit σ approximately four orders of magnitude higher at room temperature than highly tensile strained films. These relaxed films also show the highest power factor (PF = S²·σ), exceeding strained films by up to six orders of magnitude. Strain-controlled oxygen vacancies thus provide a direct route to optimize charge transport and maximize the thermoelectric performance of CMO thin films. Full article

In this article, the authors present an in-depth analysis of a PTAT sensor and its role as one of the analogue blocks in a test ASIC. The authors propose some modifications to the PTAT sensor to reduce output signal non-linearities observed following measurements that are more accurate than those in their previous article on a PTAT sensor. The obtained PTAT sensor linearity ranges from R² = 0.9990 to R² = 0.9999 in a temperature range from −40 °C to 150 °C for the entire set of measured specimens, and the details of these test sessions are discussed in this manuscript. Moreover, it is demonstrated that at least some of the implemented circuits may have a discernible impact on the operation of the others. This is particularly evident regarding the bandgap reference, whose operation is also presented and analysed. The integrated circuit specimens containing all analysed circuits were manufactured using custom 3 µm CMOS technology on an n-type wafer. Measurements showed that some circuits containing p-diff resistors behave differently compared to those consisting solely of MOS transistors in symmetrical and matched configurations. The spread of resistor values is approximately 20%, thus requiring their skilful operation in this technology. The likely cause of the bandgap reference’s operation modification has been identified, and promising results have been obtained by recreating its malfunction via simulation. The authors found that in this technology, analogue circuits should be designed with a large margin for component dimensions, especially those implanted in p-wells. Full article

In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near $V_{\mathrm{DD}}/4$ per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows $|S_{21}|$ = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power $P_{\mathrm{sat}}=8.67$ dBm at $V_{\mathrm{DD}}=4$ V, with $S_{11}<-15$ dB and reverse isolation $\approx -16$ dB. The layout occupies $1.6\times 1.6$ mm² and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of $P_{\mathrm{sat}}$ and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs ($\pm 10\%$ devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends. Full article

A 3.0 V bandgap reference (BGR) for battery management integrated circuit (BMIC) is presented, achieving a low temperature coefficient (TC) and a high power supply rejection ratio (PSRR). Precision is enhanced through two techniques: (1) a base current correction technique eliminates errors from the bipolar junction transistor (BJT) base current, and (2) a high-order temperature compensation circuit counteracts the inherent nonlinearity of the BJT’s base-emitter voltage (V_BE). Furthermore, an improved flipped voltage follower (FVF) pre-regulation structure is integrated for efficient power supply noise suppression. The circuit is designed based on a 180 nm BiCMOS process, occupying a layout area of 0.0459 mm². Post-layout simulation results demonstrate that the BGR achieves a temperature coefficient of 1.59 ppm/°C over the −40 °C to 125 °C temperature range. Within a supply voltage range of 4.7 V to 5.3 V, the line regulation is 0.00058 mV/V. At a 5.0 V supply voltage, the quiescent current is 23 μA, and the PSRR is −128.89 dB@1 Hz and −102.9 dB@1 kHz. Full article

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit. Full article

We propose and demonstrate a novel motion blur-free hybrid image sensing technique. Unlike the previous hybrid image sensors, we developed a homogeneous hybrid image sensing technique including 60 fps CMOS Image Sensor (CIS) and 1440 fps pseudo Dynamic Vision Sensor (DVS) image frames without any performance degradation caused by static bad pixels. To achieve the fast readout, we implemented two one-side ADCs on two photodiodes (PDs) and the pixel output settling time can be reduced significantly by using the column switch control. The high-speed pseudo DVS frame can be obtained by differentiating fast-readout CIS frames, by which, in turn, the world’s smallest pseudo DVS pixel (1.8 μm) can be achieved. In addition, we confirmed that CIS (50 Mp resolution) and DVS (0.78 Mp resolution) data obtained from the hybrid image sensor can be transmitted over the MIPI (4.5 Gb/s four-lane D-PHY) interface without signal loss. The results showed that the motion blur of a 60 fps CIS frame image can be compensated dramatically by using the proposed pseudo DVS frames together with a deblur algorithm. Finally, using the event simulation, we verified that a 1440 fps pseudo DVS frame can compensate the motion blur of the CIS image captured in the situation of jogging at a 3 m distance. Full article

This paper presents an enhanced Ant Colony Optimization (ACO) algorithm tailored for optimizing CMOS physical design in VLSI circuits. As device complexity escalates, traditional placement techniques struggle with multiobjective goals such as minimizing layout area, wirelength, and achieving effective aspect ratios. The proposed ACO framework simulates artificial ant colonies exploring layout configurations and reinforcing promising solutions through a pheromone-guided heuristic. Evaluated on a benchmark containing ten typical logic blocks—Adder, Multiplier, Shifter, MUX, Register, ALU, Decoder, Control, Cache, and Buffer—the ACO method achieves a maximum layout area reduction of 27.27% (from 1760 to 1280 units²) and improves the aspect ratio from 3.64 to 5.0 compared to traditional layouts. The mean area reduction observed across different parameter settings is approximately 20%. The system also includes a fully configurable and modular automation tool designed for flexible parameter tuning and the rapid benchmarking of the ACO algorithm. This tool enables users to easily adjust key parameters such as number of ants, iteration count, pheromone evaporation rate, and heuristic influences, allowing for a comprehensive exploration of the optimization space. Experimental results demonstrate ACO’s scalability, adaptability, and effectiveness, establishing it as a viable approach for automation in complex physical designs. Future work will focus on hybrid algorithms and multi-objective optimization extensions. Full article