Efficient mmWave PA in 90 nm CMOS: Stacked-Inverter Topology, L/T Matching, and EM-Validated Results

Abstract

In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near $V_{\mathrm{DD}}/4$ per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows $|S_{21}|$ = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power $P_{\mathrm{sat}}=8.67$ dBm at $V_{\mathrm{DD}}=4$ V, with $S_{11}<-15$ dB and reverse isolation $\approx -16$ dB. The layout occupies $1.6\times 1.6$ mm² and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of $P_{\mathrm{sat}}$ and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs ($\pm 10\%$ devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends.

1. Introduction

The rapid evolution of wireless communication technologies has brought millimeter-wave (mmWave) systems to the forefront of modern research, particularly for applications such as wideband wireless communication, satellite radio, and automotive radar. These advancements are driven by the need for higher data rates, improved spectral efficiency, and compact system integration. Among the critical building blocks, power amplifiers (PAs) play a central role as the final stage of the transmitter chain, providing the required output power to the antenna. The development of efficient mmWave PAs has, therefore, become a focal point of ongoing research, with complementary metal-oxide-semiconductor (CMOS) technology emerging as a promising candidate due to its low cost and small footprint; also, CMOS is compatible with on-chip integration [1].

Despite these advantages, the design of high-power and efficient CMOS PAs at mmWave frequencies remains challenging. CMOS devices suffer from limited breakdown voltage, high knee voltage, and reduced gain, along with poor-quality on-chip passive components. In advanced technology nodes, issues such as gate oxide breakdown and hot-carrier effects further constrain achievable output power and long-term reliability [2,3,4]. These challenges necessitate innovative circuit techniques to meet the stringent requirements of mmWave front-ends.

One major consideration is the design of output matching networks that transform the inherently low impedance of CMOS transistors to the standard 50 Ω antenna load. While device scaling and transistor sizing can increase drain current to boost output power, this approach lowers input impedance, making impedance matching more complex [5]. Achieving watt-level output often requires large impedance transformations, which can introduce additional losses and reduce efficiency. In portable applications, where the PA is a dominant power consumer, improving efficiency is critical for extending battery life and enhancing overall system performance [6,7,8].

Several CMOS PA architectures have been explored to address these challenges. Cascode amplifiers provide high gain and isolation but suffer from limited voltage headroom in scaled processes [9]. Doherty amplifiers improve back-off efficiency for modulated signals, yet their implementation in nanoscale CMOS is hindered by parasitics and complex matching requirements [7]. Distributed amplifiers offer wide bandwidth but typically consume large silicon area and achieve relatively low peak power-added efficiency (PAE) [10]. These trade-offs have motivated alternative approaches such as inverter-based stacked topologies, which distribute voltage stress across devices, eliminate bulky RF chokes, and simplify integration [11,12].

Progress in CMOS PA design across technology nodes reflects steady innovation. Sowlati and Leenaerts [9] demonstrated a 2.4 GHz cascode PA in 180 nm CMOS with modest efficiency, while Huang [13] presented a 60 GHz distributed PA in 90 nm CMOS that achieved wideband performance but low PAE. Barton [14] explored Doherty architectures at 28 GHz in 130 nm CMOS with improved back-off efficiency, whereas Son et al. [11] introduced a stacked n/pMOS PA at 1.8 GHz in 180 nm CMOS. Kiumarsi et al. [12] further advanced inverter-stacked PAs in 65 nm CMOS, highlighting their potential despite efficiency constraints.

More recent work has pushed the limits of CMOS PAs. Chakrabarti and Krishnaswamy [15] reported a 45 nm SOI stacked Class-E-like PA at 45 GHz achieving a peak PAE of 34.6% with $P_{\mathrm{sat}}$ of 17.6 dBm in a two-stack configuration, and 19.4% PAE with $P_{\mathrm{sat}}$ of 20.3 dBm in a four-stack version. Ogunnika and Valdes-Garcia [16] demonstrated a 32 nm SOI Class-E tuned PA at 60 GHz with nearly 30% PAE. At 29.5 GHz, Oulu University researchers [17] designed a dual-input stacked PA in 22 nm FD-SOI, achieving 11.5 dB gain, 19.5 dBm $P_{\mathrm{sat}}$, and 17% PAE. A GlobalFoundries 22FDX^® 28 GHz dual-stage PA reported peak PAE of 31.5%, while Mayeda et al. [18] showcased a broadband PA covering 24–43.5 GHz in 22 nm FD-SOI. Most recently, Yamamoto et al. [19] demonstrated a 28 nm CMOS D-band PA operating from 110–170 GHz with 7.6% PAE, illustrating ongoing efforts to extend CMOS PA performance into higher frequency ranges.

Together, these prior works highlight both the advances and persistent limitations of CMOS PA design across architectures, technology nodes, and frequency bands. The stacked-inverter PA proposed in this work leverages inverter-based gain enhancement and transistor stacking to overcome voltage stress limitations, improve efficiency, and simplify circuit integration. One effective approach is the use of stacking of multiple transistors to form a composite structure which allows the power amplifier (PA) to handle higher voltage swings by distributing voltage stress across the devices, thereby reducing the risk of breakdown. It also facilities impedance matching and enables higher output power, supporting wideband performance. All of these advantages make the stacked configuration especially suitable for mmWave applications, where high data rates and spectral efficiency are essential.

The main aim of this work is to design and analyze a stacked-FET power amplifier (PA) using four transistors in a 90 nm CMOS process, with a particular focus on optimizing impedance matching among the stacked devices. This optimization is critical for enhancing output power, power-added efficiency (PAE), and bandwidth—key parameters for mmWave communication systems. The stacked configuration effectively reduces CMOS technology’s inherent limitations such as low voltage handling and thermal stress. The design lowers the possibility of thermal runaway and increases device reliability by dividing the voltage and thermal load among several transistors. Optimizing on-chip passive components (such as inductors and capacitors) also helps to maintain a high Q-factor and reduce losses. Overall, the proposed design demonstrates strong potential for high-efficiency mmWave power amplifiers in modern wireless systems.

Finally, we present the performance of a wideband power amplifier with four stacked FETs implemented in a 90 nm CMOS process. The combination of output power and efficiency achieved for CMOS-based amplifiers, making it suitable for mmWave and wideband applications.

2. Modeling and Design of Choke-Less Inverter-Based Stacked PA

2.1. Choke-Less Inverter-Based PA: Splitting $V_{\mathrm{DS}}$ Stress and Combining $g_m$ for Wideband Gain

In conventional Class-E power amplifiers, a single switching device experiences a high peak $V_{\mathrm{DS}}$ whereas signal swing is twice the supply voltage and hence voltage stress is $2V_{\mathrm{DD}}$ across $V_{\mathrm{DS}}$, which can exceed the breakdown voltage of CMOS transistors, particularly in handset applications where the supply voltage is typically 3.3 V or higher [20]. The proposed design introduces an additional switching device to split the output voltage swing between the drain nodes of NMOS and PMOS transistors in which $V_{\mathrm{DS}}$ will be at most $V_{\mathrm{DD}}$, eliminating the need for a choke inductor and simplifying the amplifier structure. Instead of reducing $V_{\mathrm{DD}}$, the proposed inverter-based amplifier lowers the drain-source voltage of each active device compared to a conventional Class-E amplifier operating at the same supply voltage [15]. The conventional PA has the gain that depends only on NMOS transconductance. But in inverter-based amplifier has NMOS and PMOS transconductances combined, resulting in higher effective $g_m$ and greater voltage gain [21]. In addition, the inverter also lacks internal nodes, which means there are no additional poles or zeros. This allows it to maintain better frequency response and bandwidth than that of the conventional common-source amplifier especially at high frequencies [22].

2.2. Modeling of Transistors, Capacitors, and Bias Resistors for Intermediate-Node Matching and Balanced $V_{\mathrm{DS}}$

In a stacked configuration, multiple transistors are in series; only the bottom device is directly driven to preserve input power and enhance PAE. Upper-stack devices switch due to intermediary node swings, while the top drain sustains a class-E-like waveform, ensuring balanced voltage stress across all devices. For reliability, the voltage swing between transistor junctions must not exceed $2V_{\mathrm{DD}}$, resulting in a peak output swing of $2V_{\mathrm{DD}}$ for an n-stack PA [8].

Intermediary node voltage swing can be achieved using techniques like capacitive charging acceleration [11]. To maintain the peak AC swing limit across the gate-source junction in the on half-cycle and the gate-drain junction in the off half-cycle. The swing at gate voltages in the stack is induced through capacitive coupling via ($C_{GS}$) and ($C_{GD}$), which are controlled by the gate capacitor $C_n$ [6]. Capacitors also adjust the impedance at each drain node, which ensures that each transistor operates at its optimum impedance for maximum power delivery. A resistive ladder from the drain to the gate of the topmost FET used for DC biasing ensures maximum voltage swing at the output. Without the feedback mechanism, the gate voltages of the stacked FETs remain zero and do not turn on while their source voltages vary under RF power conditions. This mismatch could cause early device breakdown due to gate-source voltage limitations, reducing power output.

Load impedances at intermediate nodes of the stack have a significant reactive component at mm wave frequencies due to transistor and interconnect capacitances. The reactive component of the node impedance reduces efficiency by (a) causing part of the transistor RF current to flow through ($C_{GS}$) and other capacitances instead of reaching the load and (b) disrupting the phase alignment of voltage waveforms at the transistor drains, reducing the top drain’s voltage swing. To achieve proper matching at intermediate nodes, passive elements, such as series inductance can be used [23].

2.3. Design of the Proposed Stacked PA Architecture

Most stacked PAs described so far rely entirely on NMOS transistors, except for the design by Son et al. [11]. While the PA designed by Son et al. [11] includes both NMOS and PMOS transistors, it does not fully adopt a stacked structure. Instead, only two transistors—either NMOS or PMOS—are stacked, and a transformer is used to merge their output power. In this study, we use a new strategy from the conventional CMOS inverter design by fully stacking NMOS and PMOS devices. Our method expands on the self-biased cascade technique by increasing efficiency and power management, making it a promising choice for upcoming applications [20]. An inverter-based stacked PA composed of two NMOS and two PMOS transistors is shown in Figure 1.

In our design, we used a stacked inverter-based booster that incorporates two vertically stacked inverters, utilizing two thin-oxide PMOS and two NMOS transistors, capable of achieving output swings $\ge 3{\mathrm{V}}_{\mathrm{PP}}$. In SOI CMOS process, each MOSFET is fully isolated by shallow trench isolation regions and a buried oxide layer, allowing for effective isolation even at DC and supporting voltages up to 10 V. In our design, the drain-source ($V_{DS}$), gate-source ($V_{GS}$), and gate-drain ($V_{GD}$) voltages for each transistor are kept within the maximum supply voltage of 1.1 V. In the booster design, the dimensions of the upper MOSFETs in the stack are gradually reduced, as they experience smaller current swings. This minimizes output capacitance $C_S$ and enhances the output stage’s bandwidth and output power. Additionally, capacitors are placed between the gates of the MOSFETs and ground to create a capacitive voltage divider with the gate-source ($C_{GS}$) and drain-gate ($C_{GD}$) capacitances of their respective MOSFETs using (1).

$$C_n={\displaystyle \frac{C_{GS,n+3}{C}_{GD,n}}{2n-3}}n\ge 2$$

(1)

This configuration ensures that a larger fraction of the input voltage signal is presented at the gate of the MOSFETs located higher up in the stack, such a way that voltage swings across each transistor in the stack will add up in phase at the output node. The appropriate DC bias gate voltage for the stacked MOSFETs is established via a resistive divider, ensuring that each transistor experiences a drain-source voltage ($V_{DS}$) of approximately $V_{DD}$/4. Resistor values were calculated accordingly, with minor adjustments made in the final design to balance power consumption and load matching.

Furthermore, the output stage’s high-frequency performance is improved by adjusted MOSFET finger width and gate finger count. The input matching network is designed to convert the 50 Ω system impedance to the transistor’s input impedance, ensuring maximum power transfer and gain enhancement [11]. The T-network was chosen for its ability to match a wide range of impedances, consisting of two shunt capacitors $C_{in1}$ and $C_{in2}$ and one series inductor $L_{in1}$. Similarly, the output matching network transforms the transistor’s output impedance to 50 Ω, optimizing both gain and stability of the power amplifier through a low-pass matching network, which consists of a series inductor $L_{out1}$ followed by a capacitor $C_{dcblock}$.

2.4. Analytical Modeling and Design Equations

2.4.1. PA Gain, Output Power, Efficiency, and Linearity

For a matched load $R_{\mathrm{L}}$ at ${\omega }_0$, the large-signal fundamental output power is follows the relation shown in Equation (2).

$$P_{\mathrm{out}}={\displaystyle \frac{V_{o,1}^2}{2R_{\mathrm{out}}}}={\displaystyle \frac{I_{o,1}^2{R}_{\mathrm{out}}}{2}}$$

(2)

where $V_{o,1}$ and $I_{o,1}$ are the fundamental components of the output voltage and current, respectively. In small-signal, the midband power gain ($G_p$) can be approximated as Equation (3).

$$G_p\left({\omega }_0\right)={\left|g_{m,\mathrm{eff}}\left({\omega }_0\right)Z_{L,\mathrm{eff}}\left({\omega }_0\right)\right|}^2$$

(3)

which holds at ${\omega }_0$ under near-conjugate match where $\Im \left\{Z_{L,\mathrm{eff}}\right\}\approx 0$.

Moreover, $g_{m,\mathrm{eff}}$ is the effective transconductance driving the load seen by the PA core (combined transconductance of $M_2$ and $M_3$), and $R_{\mathrm{L},\mathrm{eff}}$ (combination of the output resistance and on resistance of $M_2$ and $M_3$) is the real part of the transformed load at the PA output node [24,25].

The power-added efficiency (PAE) and drain efficiency (DE) follow as Equation (4).

$$\mathrm{PAE}={\displaystyle \frac{P_{\mathrm{out}}-P_{\mathrm{in}}}{P_{\mathrm{DC}}}},\mathrm{DE}={\displaystyle \frac{P_{\mathrm{out}}}{P_{\mathrm{DC}}}},$$

(4)

where $P_{\mathrm{in}}$ is the RF input power and $P_{\mathrm{DC}}=V_{\mathrm{DD}}{I}_{\mathrm{DD}}$. The saturated output power $P_{\mathrm{sat}}$ is the maximum $P_{\mathrm{out}}$ before hard clipping (or at the knee of the $P_{\mathrm{out}}$ vs. $P_{\mathrm{in}}$ curve); practically, it is extracted from large-signal simulations/measurements at the onset of saturation.

A memoryless weakly nonlinear baseband model can be described as Equation (5) [26,27].

$$y\left(t\right)=a_{1}x\left(t\right)+a_3{x}^3\left(t\right)+\dots ,$$

(5)

captures AM/AM nonlinearity. The input-referred third-order intercept point is shown in Equation (6) [26,27].

$$\mathrm{IIP}3\approx \sqrt{{\displaystyle \frac{4}{3}}{\displaystyle \frac{a_1}{|a_3|}}},\mathrm{OIP}3=\mathrm{IIP}3+G_{\mathrm{p}}\left(\mathrm{in}\mathrm{dB}\right),$$

(6)

and the 1 dB compression point $P_{1\mathrm{dB}}$ occurs where the small-signal gain drops by 1 dB relative to $a_1$. In practice, $P_{1\mathrm{dB}}$ and (O/I)IP3 are obtained from PSS (Periodic Steady-State Analysis) /PAC (Periodic AC Analysis) and two-tone simulations are consistent with the results explained in later section of this article.

2.4.2. Small-Signal Model of the Stacked Inverter: Stress Sharing and Impedance

An inverter-based unit provides an additive transconductance as shown in Equation (7).

$$g_{m,\mathrm{inv}}\approx g_{m,n}+g_{m,p},$$

(7)

while its small-signal output resistance satisfies as Equation (8).

$$r_{o,\mathrm{inv}}\approx {\left(r_{o,n}^{-1}+r_{o,p}^{-1}\right)}^{-1}.$$

(8)

For an N-device voltage stack (alternating p/n devices as in this work), a first-order small-signal stress-sharing model assumes a capacitive divider between adjacent device nodes. Denote the intrinsic capacitances of device k by $C_{\mathrm{gs},k}$ and $C_{\mathrm{gd},k}$ and any intentional gate capacitors by $C_k$; the interstage voltage division yields as Equation (9).

$$\mathrm{A}v=b{v}_o,\Rightarrow v_k={\alpha }_k{v}_o,k=1\dots N-1,$$

(9)

where the tridiagonal matrix $\mathbf{A}$ collects node-to-node capacitances ($C_{\mathrm{gs}},C_{\mathrm{gd}},C_k$) and ${\alpha }_k$ are frequency-dependent division ratios. The device peak stress can be calculated as Equation (10).

$$|v_{\mathrm{ds},k}{|}_{\mathrm{pk}}\lesssim {\displaystyle \frac{V_{\mathrm{DD}}}{N}}+{\mathsf{\Delta }}_k(\omega ,C’\mathrm{s},Q),$$

(10)

with ${\mathsf{\Delta }}_k$ a small imbalance term due to parasitics/mismatch. In this design, biasing targets $v_{\mathrm{DS}}\approx V_{\mathrm{DD}}/4$ per device for a 4-stack, consistent with the post-layout operating points and the divider expression used in Equation (1) of the manuscript. (See Section 2 and

Table 1. DC operating point parameters of transistors.

Component	Type	Aspect Ratio (W/L)	${\mathit{V}}_{\mathit{GS}}\mathbf{m}$ (V)	${\mathit{V}}_{\mathit{DS}}$ (V)	${\mathit{I}}_{\mathit{DS}}$ (mA)
M4	PMOS	76 u/100 n	−568.645	−994.075 m	−6.77928
M3	PMOS	60 u/100 n	−686.915	−1.09647	−6.77928
M2	NMOS	48 u/100 n	452.291	1.10061	6.77928
M1	NMOS	60.8 u/100 n	436.485	808.851 m	6.77918

and

Table 2. Current (I) flowing through each resistor in the parallel branch.

Component	Value (KΩ)	I (µA)
R5	10	56.8645
R4	19.56	56.8684
R3	18.6	56.8746
R2	14.5	56.8729
R1	7.675	56.871

for device stresses and the capacitor-divider choice).

The inverter stack’s effective driving transconductance to the top node can be expressed as Equation (11).

$$g_{m,\mathrm{eff}}\left(\omega \right)\approx \beta \left(\omega \right)\left(g_{m,n}+g_{m,p}\right),$$

(11)

where $\beta \left(\omega \right)\in (0,1)$ captures the attenuation across the stacked ladder (set by $\{C_{\mathrm{gs}},C_{\mathrm{gd}},C_k\}$ and device $r_o$). The load seen by the top node is the transformed $R_{\mathrm{L}}$ and can be correlated as Equation (12) [Appendix A.1].

$$Z_{\mathrm{L},\mathrm{eff}}\left(\omega \right)=\Re \left\{Z_{\mathrm{match}}\left(\omega \right)\right\}+j\Im \left\{Z_{\mathrm{match}}\left(\omega \right)\right\},$$

(12)

and $R_{\mathrm{L},\mathrm{eff}}=\Re \left\{Z_{\mathrm{L},\mathrm{eff}}\right\}$ enters Equation (3).

2.4.3. Input/Output Matching Networks (L and T) at ${\omega }_0$

For an L-match between real resistances $R_{\mathrm{S}}$ and $R_{\mathrm{L}}$ at center frequency ${\omega }_0$:

• Case A: $R_{\mathrm{S}}<R_{\mathrm{L}}$ (series $X_s$, shunt $X_p$ at the load).

$$Q=\sqrt{{\displaystyle \frac{R_{\mathrm{L}}}{R_{\mathrm{S}}}}-1},X_s=Q{R}_{\mathrm{S}},X_p={\displaystyle \frac{R_{\mathrm{L}}}{Q}}.$$

(13)

Choose reactances as inductive/capacitive per topology (high-pass or low-pass). Convert to parts via $L=X/{\omega }_0$, $C=1/\left({\omega }_{0}X\right)$.

• Case B: $R_{\mathrm{S}}>R_{\mathrm{L}}$ (series $X_s$, shunt $X_p$ at the source).

$$Q=\sqrt{{\displaystyle \frac{R_{\mathrm{S}}}{R_{\mathrm{L}}}}-1},X_s={\displaystyle \frac{R_{\mathrm{S}}}{Q}},X_p=Q{R}_{\mathrm{L}}.$$

(14)

For a T-network (all-reactive, real $R_{\mathrm{S}}\to R_{\mathrm{L}}$), selecting a desired loaded quality factor $Q_{\mathrm{T}}$ gives the series and shunt reactances can be calculated as Equations (15) and (16).

$$\begin{array}{cc}\hfill X_{s1}& =Q_{\mathrm{T}}{R}_{\mathrm{S}},X_{s2}=Q_{\mathrm{T}}{R}_{\mathrm{L}},\hfill \end{array}$$

(15)

$$\begin{array}{cc}\hfill X_p& ={\displaystyle \frac{R_{\mathrm{S}}{R}_{\mathrm{L}}}{Q_{\mathrm{T}}(R_{\mathrm{S}}+R_{\mathrm{L}})}}.\hfill \end{array}$$

(16)

The three reactances $(X_{s1},X_p,X_{s2})$ are then implemented as series $L/C$ and a shunt $L/C$ at ${\omega }_0$. For band-edge shaping or realizability with on-chip passives, one can sweep $Q_{\mathrm{T}}$ to trade off insertion loss (hence, PAE) against bandwidth [Appendix A.2]. The same synthesis applies to the input network by substituting the source impedance (usually 50 Ω) and the PA input resistance/capacitance (dominated by $1/g_{m,\mathrm{inv}}$ in (7) and $C_{\mathrm{in}}\approx C_{\mathrm{gs},n}+C_{\mathrm{gs},p}$). Combining (11) and (12) with the chosen L/T match yields $R_{\mathrm{L},\mathrm{eff}}$, and thus, $G_{\mathrm{p}}$ via Equation (3) [Appendix A.3]. Using the large-signal $V_{o,1}$ at the matched node gives $P_{\mathrm{out}}$ from (2), and then $\mathrm{DE}$ and $\mathrm{PAE}$ from (4) [Appendix A.4]. Linearity metrics (1 dB compression and O/IIP3) follow from the cubic model (5) and (6) and are validated against PSS/two-tone simulations.

3. Physical Implementation and Post-Layout Characterization of the Proposed Design

3.1. Layout

The layout of the stacked inverter-based power amplifier shown in Figure 2 is designed using 90 nm CMOS technology, occupying a chip area of 1.6 mm × 1.6 mm. This design optimizes metal routing and transistor placement which ensure minimal parasitic effects and efficient power distribution. Also multilayer metal interconnects were used to handle high current flow, and careful ground planning was applied to reduce inductive noise. The power amplifier consumes 31.08 mW, demonstrating low-power operation.

Figure 2 shows the on-wafer pad geometry used for measurement. The RF GSG pads adopt a 100 µm center-to-center pitch (probe-standard), with individual pad metal approximately 70 µm × 70 µm and a top-metal overglass opening/via stack to the pad ring. DC/bias pads use an 80 µm pitch with approximately 60 µm × 60 µm pad metal. This sizing balances (i) mechanical compatibility and repeatable contact with 100 µm GSG probes, (ii) EM performance—limiting pad capacitance/coupling while maintaining robust ground return via fenced surrounds and guard rings—and (iii) DRC/ESD requirements of the 90 nm CMOS technology. All S-parameter data are de-embedded to the GSG reference plane at the pad edges, so the reported results exclude pad/landing parasitics. The bridge connections between multiple metal layers used for signal routing are highlighted by the pink box in Figure 2.

3.2. Result and Discussion

3.2.1. DC Simulation

The results section contains DC simulated schematic illustrating the operating points of all transistors in Figure 3. Additionally, Table 1 lists each transistor’s $V_{GS}$, $V_{DS}$, and $I_{DS}$ along with in Table 2 the specific currents flowing through the parallel resistors is included. This confirms that every device operates within the 1.2 V safe breakdown threshold. Furthermore, the analysis verifies that the circuit performs reliably and effectively within the specified parameters.

3.2.2. Transient Simulation

To verify the large-signal behavior of the proposed stacked inverter-based power amplifier, a transient simulation was performed. A sinusoidal signal of $V_{pp}$ = 1 at operating frequency was applied at the input. The transient waveforms of the input signal, output signal, and the intermediate node voltages $V_1$ and $V_2$ are shown in Figure 4. From the waveforms, it can be observed that the input signal is properly amplified at the output, indicating that the amplifier operates as expected under large-signal excitation.

3.2.3. Post Layout Simulation

The simulated small-signal scattering parameters (S parameters) of the power amplifier (PA) using Cadence spectre simulator are presented in Figure 5a,b. The designed PA achieves a gain of 10 dB at a center frequency of 39.84 GHz, which is ideal for mmWave uses calling for high-frequency operation. The 3 dB bandwidth extends over 7 GHz, from 36 GHz to 43 GHz, this bandwidth especially beneficial for wideband communication systems since high data rate transmission depends on maintaining constant gain across a large spectrum. The PA is a good option for applications requiring reliable signal amplification and spectral efficiency as a result of its gain and bandwidth characteristics based on the simulated data, though the chip fabrication is yet to be completed.

In RF systems, effective impedance matching is essential to ensure maximum power transfer and minimize signal reflections, thereby improving overall performance and efficiency. The input of the PA is well matched to 50 Ω with S11 of less than −15 dB across the operating bandwidth. This low S11 value signifies minimal signal reflection at the input, ensuring efficient coupling of the input signal into the amplifier. A reverse isolation (S12) of −16 dB indicates that there is minimal signal leakage from the output port back to the input port in the power amplifier design, which helps maintain signal integrity and stability. Linearity is an important parameter in PA design, alongside gain. It determines the maximum usable output power that the PA can deliver to the load. To evaluate linearity, periodic steady-state (PSS) analysis is typically used in simulations. As can be seen from Figure 6a and Figure 6b input and output referred 1-dB compression point of −7.20826 dBm and 1.80812 dBm respectively, is obtained at frequency of 39.84 GHz.

The input third order inter-modulation IIP3 of 14.54 dBm is obtained at 4.73 dBm input power in Figure 7. Since mmWave systems demand high power levels, power-added efficiency (PAE) and output power are critical parameters for assessing the performance of a power amplifier (PA). Figure 8 shows the measured output power and power-added efficiency (PAE) over a frequency band of 36–46 GHz at a supply voltage of 4 V. The power-added efficiency of the PA peaks at 18.38% at 41 GHz. The saturated output power ($P_{sat}$) reaches 8.67 dBm, proving that the PA can provide enough power for mmWave applications.

3.3. Quantifying Robustness Under Mismatch: MC/Sensitivity/EM Results

In addition to the baseline results, we performed statistical and layout-aware evaluations to quantify robustness and to isolate the impact of on-chip passives. A 200-point Monte Carlo (MC) campaign incorporating threshold, mobility, and passive-variation corners shows that both $P_{\mathrm{sat}}$ and PAE remain tightly clustered about their nominal values, indicating adequate variance immunity for the stacked-inverter core and its matching networks. The PAE distribution in Figure 9a is approximately Gaussian with a narrow spread, while the $P_{\mathrm{sat}}$ histogram in Figure 9b exhibits similar concentration, reflecting stable large-signal swing and load transformation across mismatch realizations. To quantify design levers, we conducted local sensitivity sweeps. Transistor width scaling (Figure 10) shows that enlarging the unit devices increases $g_m$ and improves $P_{\mathrm{sat}}$ monotically (beneficial for $P_{\mathrm{out}}$ in (2)), but degrades PAE due to higher parasitic charging loss and diminished $R_{\mathrm{L},\mathrm{eff}}$ leverage in Equation (3); this sets an upper bound on practical sizing before efficiency roll-off dominates. Inductor tolerance (Figure 11) and capacitor tolerance (Figure 12) each perturb the matching Q and resonant frequency, producing predictable shifts in peak response and small reductions in efficiency/output power; these trends match the L/T-network relations in (13)–(16) and confirm that modest guard-bands ($\pm 10\%$ passives) keep performance within spec without over-constraining on-chip passive design rules. The MC scatter plot in Figure 13a reveals a weak anti-correlation between PAE and $P_{\mathrm{sat}}$: realizations that slightly favor load-line swing (marginally higher $P_{\mathrm{sat}}$) tend to incur a modest efficiency penalty due to increased device conduction and reactive loss, consistent with the power balance in (4) and the gain dependence in Equation (3). Finally, EM co-simulation of inductors and critical interconnects (Figure 13) shows a slight downshift in the passband and a small insertion-loss increase (finite inductor Q and weak mutual coupling), yet post-EM $|S_{21}|$ tracks the schematic shape closely and preserves the targeted bandwidth and efficiency envelope, validating the stress-sharing assumption in (10) and the effective transconductance transfer in (11). Taken together, the MC, sensitivity, and EM overlays indicate that (i) the stacked ladder’s voltage division and impedance transformation are tolerant to local mismatch, (ii) device sizing should be capped by the PAE turning point identified by the width sweep, and (iii) first-order L/T designs remain accurate after EM back-annotation, requiring only minor retuning of the matching reactances for tape-out.

The performance of the proposed CMOS power amplifier, as shown in

Table 3. Comparison of CMOS stacked-inverter-based power amplifier configuration.

Ref.	Tech. (nm)	Freq. (GHz)	Gain (dB)	Bandwidth	PAE (%)	Frequency-Normalized FOM ($\frac{\mathbf{mW}}{\mathbf{GHz}·{\mathbf{mm}}^2·\mathbf{V}}$)	Topology
[1]	65	60	20.2	9	15.1	$80.24\times {10}^{-3}$	Dual-differential-input DAT
[2]	65	98	20	6	21.1	$27.72\times {10}^{-3}$	Compact Power Amplifier.
[8]	130	1.9	14.6	-	47	-	Single-stage stacked-FET
[29]	130	27.3	18.93	18.3	22.8	$6.93\times {10}^{-2}$	two-way Wilkinson power combined stacked power amplifier.
[20]	130	160	24	20	9.4	$1.6\times {10}^{-3}$	3-stage CC 4-way Comb
This work	90	38.94	10	5.6	18.38	$1.86\times {10}^{-3}$	Single-Stage Inverter Stack

, outperforms many earlier studies at comparable frequencies with a good balance of gain, bandwidth, and power-added efficiency. Against recent FD-SOI mmWave exemplars (22 nm, 29.5 GHz dual-input stacked PA, and a 22 nm broadband PA covering 24–43.5 GHz) [17,18], the proposed bulk-90 nm design trades absolute power/gain for process accessibility, area compactness (1.6 × 1.6 mm²), and layout-aware robustness (Monte Carlo, sensitivity, EM co-sim), while retaining competitive PAE for its node and complexity. Conventional Class-E PAs concentrate a ∼$2V_{DD}$ swing across a single device, stressing $V_{\mathrm{DS}}$ [15,20]; in contrast, the choke-less stacked-inverter core redistributes voltage and raises effective drive via combined NMOS/PMOS $g_m$ [21,22,23], with capacitive charging acceleration and intermediate-node matching stabilizing stress and bandwidth [6,11,23,28].

In addition to the Monte Carlo, sensitivity, and EM overlays, Figure 14a–d has been extended to report three overlaid S-parameter responses (S11, S21, S22, S12) corresponding to (i) the schematic with ideal on-chip passives, (ii) the schematic with PDK-based inductors/capacitors and pad models, and (iii) the full post-layout EM/RCx netlist. Across 36–46 GHz, the ideal-passive schematic exhibits the highest |S21|, followed by the real-passive schematic, with the PLS trace showing only a modest reduction in peak gain and a small down-shift in center frequency, while preserving the ≈10 dB gain at 39.8 GHz and the 3 dB bandwidth from 36.8 to 42.4 GHz. The corresponding S11 and S22 curves confirm that input and output matching remain better than −15 dB and −10 dB, respectively, even after layout and EM back-annotation, and S12 maintains ≈ −16 dB reverse isolation. This three-case comparison quantitatively links the schematic-level design to the EM-validated implementation, demonstrating that passive loss, pad capacitance, and routing parasitics introduce only minor degradation and are consistent with the robustness trends observed in the MC and sensitivity analyses.

4. Discussion

This work demonstrated a choke-less, inverter-stacked PA in 90 nm CMOS for mmWave operation with $|S_{21}| = 10$ dB at 39.84 GHz and a 3 dB bandwidth of 36.8–42.4 GHz, achieving peak PAE of 18.38% at 41 GHz and $P_{\mathrm{sat}}=8.67$ dBm at $V_{DD}=4$ V. To compare across different $f_0$ (operating frequency)and bandwidths, we introduce a compact, process-agnostic mmWave PA FOM that rewards efficiency, output power, and fractional bandwidth, while penalizing die area and operating frequency (harder passives/devices at higher $f_0$) in Table 3.

While these results confirm efficient power utilization and broadband matching, several factors bound ultimate performance. The PAE ceiling at Q-band is constrained by device knee/conduction losses, incomplete harmonic terminations, and finite on-chip passive Q; even carefully synthesized L/T networks incur metal and substrate loss that limits drain efficiency and back-off PAE. Thermal reliability also becomes critical at mmWave: self-heating degrades $g_m$ and $r_o$, shifts bias, and narrows the safe operating area, while EM/IR drop and current crowding cap sustainable output power. Finally, stacking complexity imposes practical overhead—intermediate-node impedances are partly reactive, so any mismatch increases circulating current and phase error, reducing the top-node swing; robust operation therefore requires tightly tuned gate capacitors and bias ladders to keep $|V_{\mathrm{GS}}|,|V_{\mathrm{GD}}|$ within limits across PVT, along with start-up biasing that avoids latch-up or over-voltage.

Looking forward, several directions can raise linearity, efficiency, and integration readiness. Linearity can be improved via digital predistortion (DPD) tailored to FR2 EVM/ACLR masks, envelope/rail tracking aligned with stacked-inverter dynamics, and selective analog techniques (adaptive bias, light degeneration, neutralization) that mitigate AM/AM and AM/PM with modest PAE cost; co-optimizing bias and matching with two-tone/IP3 and PSS/PAC analyses tightens the $P_{1\mathrm{dB}}$–PAE trade. Architectural scaling with a modest-gain driver relaxes the main stage’s input impedance target, enabling a slightly higher load line and improved $P_{\mathrm{sat}}$; asymmetric device sizing or gate-capacitor tapering across the stack can refine stress sharing and reduce dynamic loss. Migration to SOI/FD-SOI (22–45 nm) promises higher effective breakdown, lower substrate loss, and better isolation for passives and interconnects, typically lifting PAE and easing EM closure. Finally, integrating compact on-chip baluns or magnetically coupled lines enables differential drive/combining and simplifies antenna co-integration; EM-first co-design of spirals and transmission lines, with metal-density-aware ground grids and coupling management, can raise passive Q, reduce mismatch sensitivity, and stabilize phase across intermediate nodes.

Overall, the presented 90 nm design establishes a solid baseline for stacked-inverter mmWave PAs—broadband gain, competitive PAE, and layout-aware robustness—while clarifying the remaining gaps to state of the art. Closing those gaps will require simultaneously lowering passive and dynamic loss to lift the PAE ceiling, applying thermally aware floorplanning and power-grid design to sustain higher $P_{\mathrm{out}}$, and combining driver stages, load-modulation strategies, SOI migration, and EM-first passive/balun co-design. These steps provide a concrete path to higher back-off efficiency, improved linearity for high-order QAM, and resilient tape-out in advanced nodes.

5. Conclusions

This work presented a choke-less, inverter-stacked millimeter-wave PA in 90 nm CMOS that demonstrates a balanced gain–efficiency–power trade-off with layout-aware robustness. The fully stacked inverter core (two PMOS + two NMOS) distributes device stress to constrain per-device $V_{\mathrm{DS}}$, eliminates the RF choke, and combines NMOS/PMOS transconductances for strong midband drive. Guided by closed-form models for gain, output power, PAE, and linearity, as well as small-signal ladder analysis for stress sharing and impedance transformation, the design employs L/T network synthesis to co-optimize bandwidth and insertion loss. Post-layout simulations show $|S_{21}|=10$ dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and $P_{\mathrm{sat}}=8.67$ dBm at $V_{DD}=4$ V, while maintaining $S_{11}<-15$ dB and reverse isolation ≈ $-16$ dB. The implementation occupies $1.6\times 1.6$ mm² and draws 31.08 mW. Robustness was validated through a 200-run Monte Carlo (tight clustering of $P_{\mathrm{sat}}$ and PAE), device/passive sensitivity sweeps (predictable sizing/tolerance trade-offs), and EM co-simulation (minor post-EM loss/shift with preserved bandwidth), collectively confirming resilience to process/mismatch and physical parasitics. Overall, the results establish the stacked-inverter topology as a power- and area-efficient mmWave PA solution in bulk 90 nm CMOS, and provide a solid foundation for further gains via linearization, staged architectures, SOI/FD-SOI migration, and EM-first passive/balun co-design.