Design and Analysis of a Configurable Dual-Path Huffman-Arithmetic Encoder with Frequency-Based Sorting

Abstract

The designs of lossless data compression architectures create a natural trade-off between throughput, power consumption, and compression efficiency, making it difficult for designers to identify an optimal configuration that satisfies all three criteria. This paper proposes a Configurable Dual-Path Huffman/Arithmetic Encoder (CDP-HAE), which offers an architecture that supports the use of shared preprocessing, parallel path encoding using Huffman and Arithmetic, as well as selectable output. The CDP-HAE’s design prevents the waste of excess bandwidth by sending only one selected bit stream at a time. This also enables adaptation to the dynamically changing statistical characteristics of the input data. CDP-HAE’s architecture underwent ASIC synthesis in 90 nm CMOS technology and is implemented on an Artix-7 (A7-100T) using the Vivado EDA tool, confirming the scalability of the architecture to both devices. Synthesis results show that CDP-HAE improves operating frequency by 28.6% and reduces critical path delay by 27.2% compared to reference designs. Additionally, the dual-path design has a slight increase in area; the area utilization remains within reasonable limits. Power analysis indicates that optimizing logic sharing and minimizing switching activity reduces total power consumption by 34.4%. Compression tests show that the CDP-HAE delivers performance comparable to that of a conventional Huffman Encoder using application-specific datasets. Furthermore, the proposed CDP-HAE achieves performance comparable to conventional Huffman encoders on application-specific datasets, while providing up to 10% improvement in compression ratio over Huffman-only encoding.

1. Introduction

The proliferation of data-intensive applications in embedded systems, multimedia processing, and communication networks has made efficient data compression a fundamental requirement of modern digital design. Contemporary systems are increasingly required to process, transmit, and store large volumes of data under strict constraints related to bandwidth availability, power consumption, latency, and silicon area. Prior work on Canonical Huffman encoders demonstrates that carefully optimized entropy coding architectures can substantially reduce data size while preserving exact data fidelity, thereby enabling efficient data handling in constrained environments [1]. Similarly, hardware implementations of Huffman and GZIP-based compression techniques show significant improvements in throughput and bandwidth efficiency, underscoring the value of compression as an initial data reduction step in real-time systems [2].

Lossless compression methods are crucial in application areas where the loss of even a single bit of information is intolerable. For example, in medical imaging, scientific instrumentation, secure communications, and embedded control systems. In these applications, entropy encoding plays a central role by exploiting statistical redundancy in incoming streams to achieve compact representations without distortion. As data rates and system complexity continue to increase, conventional entropy encoding architectures struggle to meet the performance, power, and scalability requirements imposed by hardware implementation.

These challenges are further exacerbated in the IoT and embedded environments. Modern IoT devices are no longer limited to simple sensing tasks; however, they are expected to perform data-intensive and security-critical operations, such as encrypted communication, privacy-preserving analytics, and real-time intrusion detection, under severe energy and hardware limitations. Recent studies on IoT–Cloud security architectures highlight that conventional cryptographic and compression-based methods often introduce excessive computational and power overheads on edge devices, thereby reducing system efficiency and scalability [3]. This problem becomes further critical in highly data-intensive applications, such as multimedia sensing and monitoring, where advanced entropy coding methods—such as arithmetic encoding in AV1 video compression—exhibit superior compression performance while suffering from bounded parallelism and throughput in practical hardware implementations [4].

Beyond multimedia workloads, IoT platforms increasingly rely on machine-learning-based analytics for security and system monitoring. Due to their interpretability and effectiveness, intrusion detection and classification frameworks based on decision trees have been widely adopted. However, privacy-preserving implementations of the same based on secure multi-party computation or homomorphic encryption introduce substantial computational complexity and latency that render them infeasible for resource-constrained edge devices alone [5]. These create a compelling motivation for efficient data reduction before encryption or analysis. A lightweight, hardware-efficient lossless compression layer can significantly reduce communication bandwidth, memory, and energy usage, improving the feasibility of secure and intelligent IoT systems.

The advantages of efficient lossless compression have been realized within a broad array of data-intensive scientific and engineering applications. In the systems of space telescope imaging, for instance, lossless methods such as Huffman coding in conjunction with predictive preprocessing have been widely used to reduce transmission bandwidth without compromising scientific accuracy and measurement integrity [6]. Likewise, emerging paradigms of DNA-based molecular communication and data storage have investigated several compression and encoding schemes, including LZW, Huffman, and fixed-rule mappings, to increase information density [7]. However, these approaches often suffer from redundancy or limited adaptability compared to entropy-optimal methods such as arithmetic coding.

To overcome these, various DNA-encoding optimization studies have utilized heuristic and swarm-intelligence-based methods to fulfill biological constraints and enhance the efficiency of the coding process. Additionally, these methods often improve encoding quality, but they suffer from slow convergence and suboptimal solutions. This has motivated investigations into configurable dual-path and adaptive encoding schemes that can effectively balance efficiency with practicality [8]. In another direction, secure communication systems employ lossless compression in tandem with cryptographic algorithms, for example, Huffman or arithmetic coding followed by AES encryption, to reduce size before encryption [9]. These approaches introduce additional gains in transmission efficiency while retaining strong security guarantees, particularly in bandwidth and energy-limited environments.

Theoretically, arithmetic coding provides higher compression efficiency since the entropy represents a fractional interval that is closer to the Shannon entropy limit for symbol sequences. Adaptive arithmetic coding adjusts symbol probabilities on the fly and consistently achieves high compression efficiency, particularly when dealing with non-uniform data and large datasets [10]. However, arithmetic coding is computationally intensive and possesses inherent serial dependencies, making hardware implementation costly in terms of complexity, latency, and power consumption [11]. Quasi-static entropy encoders have been developed to alleviate some of these challenges at the cost of a slight reduction in compression efficiency. Consequently, this facilitates faster encoding, especially for text and binary streams.

For security-sensitive applications such as intrusion detection systems, data preprocessing and representation have become highly imperative. Recent studies adopted configurable dual-path optimization and deep learning frameworks where metaheuristic algorithms perform feature selection and recurrent neural networks enhance detection accuracy on benchmark datasets [12]. This emphasizes the need for efficient compression mechanisms to reduce data dimensionality and processing overhead. Configurable dual-path compression models have also achieved improved compression ratios while maintaining acceptable computational efficiency and data quality in image [13] and signal processing applications [14].

In the field of high-efficiency video coding, CABAC is still one of the most sophisticated entropy coding techniques. Previous hardware architectures for CABAC decoding address data dependencies and limited parallelism by employing optimized arithmetic decoders, increasing throughput through critical-path reduction and fast-path techniques [15]. Data compression and efficient processing have advanced across various domains. Context-based adaptive arithmetic coding with local frequency tables improves text compression [16], while Huffman coding techniques have been implemented for MATLAB arrays [17] and energy-efficient FPGA/CPU systems [18]. Lossy and lossless methods optimize image and geospatial data compression [19], with enhanced AC coefficient compression using adaptive scanning and multi-feature context coding [20]. Additionally, CNN-based models have shown superior performance over MLPs in tasks like fire detection by learning discriminative features from video frames [21], and an Android application demonstrates practical arithmetic encoding and decoding [22]. However, these designs remain complex and power-hungry, unsuitable for low-power embedded and IoT platforms.

Despite volumes being written about various entropy coding techniques, most state-of-the-art configurable dual-path compression schemes operate solely at the algorithmic level and rarely consider challenges related to hardware-level integration. Most systems also consider Huffman and Arithmetic coding as mutually exclusive choices rather than complementary techniques. This paper introduces a hardware-oriented configurable dual-path Huffman-Arithmetic encoder architecture where both encoding techniques work in parallel yet share common preprocessing stages to address these discrepancies. The proposed architecture tightly integrates the major functional modules comprising frequency counting, frequency-based symbol ordering, bitmap generation, and code table construction, which enable synchronized preprocessing with parallel entropy encoding. A frequency-aware dynamic symbol-ordering mechanism adapts to input statistics, while parallel encoding paths provide flexibility to select outputs based on application-specific constraints such as latency, power consumption, or compression efficiency. By focusing on architectural efficiency, hardware feasibility, and several key implementation trade-offs, the proposed design presents an efficient and adaptable solution for data-intensive embedded and IoT systems.

Current hardware designs for lossless data compression primarily use Huffman coding or arithmetic encoding for compression, with each encoding suited for different types of input statistics. Designs based on Huffman coding are more efficient in terms of complexity and rate of output, and less efficient than arithmetic encoders when the probabilities of the symbols vary widely. Design based on arithmetic encoding provides better compression efficiency; however, its higher implementation complexity results in greater power consumption and lower operating frequencies compared to Huffman-based compression solutions. Most previous works adopt a single fixed entropy coding method, which cannot accommodate variations in input statistics as they occur throughout operation. Furthermore, most are designed for high power consumption and/or low throughput or have only been tested on a single implementation platform (ASIC or FPGA), making it difficult to assess the scalability and practical deployability of the architecture across multiple hardware targets. Therefore, there is a need for a unified encoder architecture that is adaptable and balances compression efficiency, speed, area, and power consumption.

The main contributions of this paper are as follows:

• Configurable Dual-Path Architecture:

A novel configurable dual-path Huffman-Arithmetic encoder (CDP-HAE) is proposed, enabling parallel Huffman and Arithmetic encoding with a selectable output that adapts dynamically to changing input data statistics.

• Shared Preprocessing and Bandwidth-Efficient Design:

The architecture employs shared preprocessing stages and forwards only a single selected bitstream, eliminating redundant data transmission and minimizing bandwidth overhead.

• High-Performance and Low-Delay Implementation:

The proposed encoder achieves up to 28.6% higher operating frequency and 27.2% reduction in critical-path delay compared to representative reference designs, enabling high-throughput operation.

• Low-power Operation:

Through optimized logic sharing and controlled switching activity, the design makes it suitable for low-power embedded and communication systems.

The rest of the paper is organized as follows. Section 2 describes the proposed configurable dual-path Huffman-Arithmetic encoder architecture, including the overall system workflow and the integration of frequency-based preprocessing modules. Section 3 elaborates on the hardware implementation of the proposed design, including the functionality of individual modules and the multiplexer-based selection logic used to choose the optimal encoded output based on system constraints. Section 4 synthesizes results and discussion of a comparative analysis in the area, power, and compression performance with reference designs. Section 5 briefs the applications where the design can be used. Finally, Section 6 summarizes the paper by highlighting the key contributions and outlining potential directions for future research.

2. Methodology

This section describes the proposed configurable dual-path Huffman-Arithmetic encoder architecture, its functional workflow, and the hardware implementation methodology. The architecture is designed to provide flexible, low-power, and efficient lossless compression suitable for embedded and IoT systems operating under strict area, power, and latency constraints.

2.1. Architecture of Configurable Dual-Path Huffman-Arithmetic Encoder

The proposed encoder architecture integrates shared preprocessing stages with dual entropy encoding paths and finally performs a selection mechanism to determine the final compressed output. Its key modules are the Frequency Counter, Frequency Sorter, Bitmap Generator, Code Table Generator, Huffman Encoder, Arithmetic Encoder, and Selection Logic is shown in Figure 1.

The input data stream is processed sequentially under a global clock and reset. Initially, the symbols go through some common pre-processing stages that extract the statistical information used by both encoding schemes. Then, the pre-processed data is encoded in parallel using the Huffman and Arithmetic encoders. A selection logic, implemented according to design criteria, selects which of the encoded streams should be forwarded as the final output. The final encoded output will be routed through a hierarchical multiplexer structure to ensure that, at any given time, only one entropy-coded bit-stream will be transmitted.

2.1.1. Frequency Counter

The Frequency Counter module computes the occurrence count of each input symbol. It consists of a 256-entry register file, with each entry corresponding to an 8-bit symbol and storing its frequency count. The counter is updated synchronously on every valid input symbol. This frequency information serves as the primary statistical input for symbol ordering, bitmap generation, and entropy encoding.

2.1.2. Frequency Sorter

The Frequency Sorter organizes symbols based on their observed frequencies. Sorting enables prioritization of higher-probability symbols during encoding. In the current implementation, a simplified sorting mechanism is employed to demonstrate functionality; architecture supports integration of more advanced sorting algorithms (e.g., partial or hardware-efficient priority sorting) in future extensions.

2.1.3. Bitmap Generator

The Bitmap Generator produces a binary presence map indicating whether a symbol has appeared in the input stream. Each bitmap bit is set to ‘1’ when the corresponding symbol frequency is non-zero. This bitmap is used to:

• Eliminate redundant processing of unused symbols,
• Limit code table generation to active symbols only, and
• Reduce unnecessary switching activity, thereby lowering dynamic power consumption.

The bitmap module connects the sorted frequency information to the code table generator. The lookup mechanism provides the code table generator with the index needed to access the symbols from the sorted frequency list to quickly retrieve (and encode) the codeword associated with these input signals. The bitmap module forms a critical path in the encoding process and constitutes an integral component of synthesis and power analysis processes.

2.1.4. Code Table Generator

The Code Table Generator constructs symbol-to-code mappings based on frequency and bitmap information. In the current prototype, fixed-length codes are used to validate the architecture. However, the design supports extension to canonical Huffman code generation, enabling variable-length prefix codes derived from sorted symbol frequencies.

2.1.5. Huffman Encoder

The Huffman Encoder uses the generated code table to encode incoming symbols into variable-length prefix codes. This encoder provides deterministic latency and low computational complexity, making it suitable for real-time and low-power operation. The Huffman path represents the low-latency encoding option within the configurable dual-path architecture.

2.1.6. Arithmetic Encoder

The Arithmetic Encoder encodes the input symbol stream by maintaining dynamically updated probability intervals. It achieves compression ratios closer to the theoretical entropy limit, particularly for non-uniform symbol distributions. In addition, this encoder incurs higher computational complexity and latency compared to Huffman encoding, but it provides superior compression efficiency for statistically complex data.

2.1.7. Selection Logic and Decision-Making Process

In this configurable dual-path encoder’s selection logic, a user can enter their own optimization constraints with regard to the encoding mode, so the encoder can adapt its output based on what the user wants to achieve in terms of compression ratio, latency, or power, without having to change how the encoder works internally. The constraint selection signal from the user represents what type of optimization they would like to have. The user controls the selection of the specific constraint through a constraint selection multiplexer, which chooses from among the encoded data streams which one will be used to produce the final encoded output.

Rather than having a run-time data-adaptive decision unit for encoding types of Huffman and Arithmetic, our proposed architecture has a mode-controlled selection method that uses a configuration-driven multiplexing system to define which encoder will be used to transmit data (numerically) before transmission. At any given time, the output of only one of the two encoders will be applied to the output interface, while the other encoder’s path is disabled (logically). The mode is selected through a configuration signal, as opposed to comparing the statistical characteristics of each encoding algorithm (as in run-time comparison modes), and contributes little to no additional area/timing/power overhead when using the coding cores compared with a coding architecture based upon run-time decisions.

Using selection logic, multiple constraint objectives are mapped to a smaller group of encoding paths. This enables effective re-use of encoder output while optimizing the desired objectives. The selected encoded stream is passed on to the final encoded output, thereby reflecting the user-specified optimization objective.

This type of selection logic provides the encoder with added flexibility during operation, simplifies control, and reduces the hardware requirements, allowing the architecture to work well within adaptive compression systems.

2.2. Flow of Configurable Dual-Path Huffman-Arithmetic Encoder

The configurable dual-path Huffman-Arithmetic encoder shown in Figure 2 begins its operation by accepting the input data stream in the form of symbols along with a validity signal. The validity check ensures that only meaningful input symbols are processed while maintaining the internal state unchanged during idle or reset conditions. Once a valid symbol is detected, the encoder proceeds to analyze the statistical properties of the input data.

Each incoming symbol contributes to a frequency accumulation process, where the occurrence count of symbols is updated continuously. These frequency values are then arranged in a sorted order to reflect the relative significance of symbols based on their occurrence. The sorted frequency information provides a structured representation of the input data distribution, which is essential for entropy-based encoding decisions.

Based on the computed frequency values, a bitmap-based classification is performed to identify active symbols. Symbols with non-zero frequency are marked as valid, while symbols with zero occurrences are excluded from further processing. This bitmap-driven mechanism efficiently filters the symbol set and minimizes unnecessary encoding operations, thereby improving overall computational efficiency.

The classified symbols are then processed through two complementary encoding paths operating in parallel. Symbols identified as active are encoded using the Huffman encoder, which is optimized for reduced latency and lower power consumption due to its simpler computational structure. In parallel, symbols directed through the code table generation path are encoded using arithmetic encoding, which exploits probabilistic modeling to achieve a higher compression ratio. This parallel processing enables the system to simultaneously generate encoding outputs appropriate for different optimization objectives.

The outputs of the Huffman and Arithmetic encoders are subsequently forwarded to a selection logic unit, which determines the final encoded output based on user-defined constraints. The selection logic is driven by a static configuration signal defined before operation, enabling deterministic selection between Huffman and Arithmetic encoding modes. This selection of logic dynamically chooses between compression efficiency and computational efficiency without altering the internal encoding structure. As a result, the final encoded output reflects the desired trade-off among compression ratio, latency, and power consumption.

Overall, the proposed configurable dual-path encoding flow combines statistical analysis, adaptive symbol classification, parallel entropy encoding, and constraint-based selection to achieve a flexible and efficient compression architecture. This design enables dynamic adaptation to varying application requirements, making it balanced and well-suited for modern data compression systems.

2.3. Working Mechanism of Configurable Dual-Path Huffman-Arithmetic Encoder

The configurable dual-path encoder continuously analyses the statistical characteristics of the incoming symbol stream and dynamically chooses the best entropy encoding technique. At the start of the operation, the input symbol is accompanied by a validity signal, which asserts the availability of meaningful data. The detection of a valid symbol takes the encoder from the initial idle state into the active processing mode, while all entries corresponding to unrelated symbols remain unchanged.

The frequency table is updated selectively for the arriving input symbol, such that only the entry corresponding to the matched symbol location is altered from its previous value, and all others remain unchanged. This selective update process minimizes unnecessary switching activity in the process of tracking symbol occurrences. The updated frequency count starts providing the output and describes the statistical distribution that exists in the input data stream. During the pre-process phase of the design, the system consists of the following components: The frequency counter counts the number of times symbols appear over a defined time interval (the window). The Frequency Sorter sorts these counted symbols into an ordered list based on how frequently they occur and supplies this sorted list to the bitmap generator. The bitmap generator uses the sorted frequency list received from the Frequency Sorter to create a single compact mapping of the symbol’s index to its bitmap bit position. Finally, the bitmap output will be utilized by both of the encoding interfaces to guarantee that whichever encoding path identifies (references) its input symbols the same way.

Generated frequency information from this step is used repeatedly during successive encoding cycles, which provides a dynamic update capability to the encoder as new symbols are presented. This update-and-output behavior on every cycle provides the continuous statistical update needed by the entropy encoder and ensures the time variation in encoder responses to changes in symbol distribution. Huffman encoding and Arithmetic encoding are supported with updated statistical information provided by the encoder. Both encoding paths operate in a parallel mode that enables the system to output encoded representations optimized for diverse design objectives. Huffman encoding guarantees low-complexity, low-latency performance, whereas Arithmetic encoding entails more efficient compression due to probabilistic interval representation.

The final aspect influencing the operation of the mechanism is the selection logic, which defines what encoded output will be produced based on some predefined criteria of optimization. When the selection logic has assessed the constraint under consideration, it will produce an encoded version of the data, which can then be sent to the actual output portion of the working mechanism. By decoupling the generation encoded data from the selection among those encodings, the overall architecture becomes capable of supporting multiple distinct optimization goals while relying on the same encoding and statistical analysis infrastructure.

In summary, the overall working mechanism of the configurable dual-path encoder illustrated in Figure 3 can provide the ability to operate using selective frequency updating, adaptive statistical analysis, parallel entropy encoding and constraint-based output selection, or in essence provide a seamless flow of information through multiple stages to achieve maximum data compression while offering the ability to balance between compression ratio, latency and power use depending on the needs of individual applications.

2.4. Timing of Configurable Dual-Path Huffman-Arithmetic Encoder

Figure 4’s timing diagram illustrates an example of synchronous, multi-cycle operation for an encoder. The encoder’s first phase (initial cycles) consists of collecting and stabilizing frequency data, followed by processing statistical information to produce encoded symbol values. The collection and stabilization of frequency information permit the encoding process to begin using symbol probabilities that have been collected and stabilized throughout all phases of operation.

After completing the initial cycles, Huffman and Arithmetic encoders both use the processed statistical data to generate their respective encoded outputs simultaneously. The logic determining which of these outputs is to be produced as the final encoded data then activates once both outputs are available. The final encoded output (configurable dual-path encoding) is produced deterministically and synchronously, thereby completing the configurable dual-path encoding process.

3. Hardware Implementation and Synthesis Setup

Verilog HDL was used to implement the complete configurable dual-path encoder architecture. Functional simulation with Cadence Incisive was followed by synthesis with Cadence Genus 21.1, which provided a basis for measuring trade-offs in performance, compression efficiency, latency, and power consumption within a constrained operation environment.

The following implementation details were used:

• Technology Node: 90 nm CMOS
• Standard Cell Library: Generic 90 nm standard cell library (Cadence Genus 21.1)
• Synthesis Constraints: Defined using Synopsys Design Constraints (SDC)
• Operating Corner: Slow corner, balanced tree optimization
• Power Analysis: Dynamic and leakage power estimation enabled

The synthesis flow is automated using TCL scripting to ensure repeatability and consistency across experiments.

Along with ASIC validation, the proposed architecture is implemented on an FPGA platform for a fair comparison with previously developed reference designs. We performed FPGA synthesis, and power analysis using the Xilinx Vivado 2020.1 EDA tool, which is designed to target an Artix-7 A7-100T device. This implementation of the proposed CDP-HAE architecture on two different platforms explains the ability to scale the proposed architecture’s performance and power consumption and supports consistent performance and power evaluations between the two platforms.

4. Results and Discussion

The ASIC technology results of the configurable dual-path Huffman -Arithmetic encoder are shown in

Table 1. ASIC technology results of the reference and proposed designs.

Parameter	Reference Design [1]	Reference Design [2]	Proposed Configurable Dual-Path Design
Encoder type	Canonical Huffman	Huffman Encoder	Configurable dual-path Huffman—Arithmetic Encoder
Operating Frequency (MHz)	400	350	450
Area (µm2)	2,008,766	2,349,604	2,558,322
Critical path delay (ns)	2.68	2.62	1.952
Area-Delay Product (ADP)	5.4 × 106	6.15 × 106	5.2 × 106
Power Consumption (mW)	850.84	320	210

, along with comparisons against two reference architectures. The implementation of the proposed architecture has resulted in a maximum operational frequency of 450 MHz, which represents an increase of 12.5% over [1] and 28.6% over [2], primarily due to the decrease in the critical path delay to 1.952 ns, representing decreases of 27.2% and 25.5% compared to [1] and [2], respectively.

In addition, the area of the proposed architecture is 8.9% greater than the reference design [1]; this was intentional and is justified by the additional functionality, namely the support for two entropy coding paths as well as the required logic to select between the different coding paths. The Area-Delay Product (ADP) of the proposed architecture is 5.20 × 10⁶, which is still competitive with [1] and improves [2], indicating that the proposed encoder has comparable area-delay efficiency while providing additional architectural flexibility.

The power consumption of the proposed architecture has also been greatly reduced. The proposed architecture has a power consumption of 210 mW, which is 34.4% lower than Design Reference 2 and 75.3% lower than Design Reference 1. These decreases were achieved through optimized dual-path logic, reduced switching activity on the critical path, and improved clock utilization.

Table 2. FPGA-based performance, resource utilization, and power comparison of reference and proposed designs.

Resource	Reference Design [1]	Reference Design [2]	Proposed Design (CDP-HAE)
Operating frequency (MHz)	180	150	200
LUTs	14,374	8581	11,134
Critical path delay (ns)	5.50	6.67	5.02
LUT Delay Product (ns)	7.97 × 104	5.72 × 104	5.58 × 104
Static Power (W)	0.118	0.099	0.106
Dynamic Power (W)	0.267	0.185	0.162
Total Power (W)	0.385	0.284	0.268

compares the proposed configurable dual-path Huffman-Arithmetic encoder (CDP-HAE) with two reference designs in terms of operating frequency, logic utilization, timing, and power consumption on an FPGA platform.

The proposed CDP-HAE outperforms reference design [1] and reference design [2] by achieving the maximum FPGA operational frequency of 200 MHz, compared to 180 MHz and 150 MHz, respectively, owing mainly to the critically shorter progression delay (5.02 ns) as opposed to 5.50 ns for RD [1] and 6.67 ns for RD [2]. The lessened critical progression also reflects that the architectural design of the configurable dual-path implementation is more capable of supporting an increased range of clock frequencies when utilizing FPGA-based designs.

The LUT–Delay Product (LDP) has been utilized as a composite performance indicator to assess the combined effects that logic utilization and timing performance have on one another. Even though the CDP-HAE design contains two different entropy-coding paths (along with supporting selection logic), it still provides relatively good performance on the basis of the LDP measurement (5.57 × 10⁴), compared to [1] and slightly less compared to [2]. Thus, the additional degrees of functional flexibility provided by the CDP-HAE do not incur an undesirably high degree of timing or logic overhead.

The evaluation of power consumption also substantiates the efficient practices of the proposed architecture. Total power consumption on this implementation is 0.268 W, with contributions of 0.106 W from static power and 0.162 W from dynamic power sources. Inclusion of additional encoding and selection logic marginally increases resource utilization; however, optimized logic sharing and controlled switching activity yield lower overall power consumption for this design versus both reference designs. These results support the argument that the CDP-HAE improves performance and maintains superior power efficiency for FPGA implementations.

Compression Ratio (CR) is related to compression efficiency (CE) as:

$$CR={\displaystyle \frac{Original Size }{Compressed Size}} ====> CE={\displaystyle \frac{1}{CR}}\times 100$$

Table 3. Compression performance comparison using the benchmark Dataset for the reference design [1] and the proposed encoder.

Parameter	Reference Design [1]	Proposed Design
Compression Method	Canonical Huffman	CDP-HAE
Dataset/Test Suite	Kodak-24 Image Dataset	Kodak-24 Image Dataset
File type	JPEG image data (Y-channel AC coefficients)	JPEG image data
Compression Ratio	1.14	1.10
Efficiency	87.76%	90.1%

presents the results of compression performance of the proposed CDP-HAE compared to the reference design [1] with the common Kodak-24 JPEG image dataset. The reference design [1] uses a canonical Huffman encoder and achieves a Compression Ratio (CR) of 1.14 with a Compression Efficiency (CE) of 87.76%. The proposed CDP-HAE achieves a CR of 1.10 but has a higher CE of 90.1%.

In addition, the proposed CDP-HAE has a lower CR, the higher CE shows that the proposed CDP-HAE removes redundant data more effectively than the reference design [1]. The higher CE of the proposed CDP-HAE indicates that the output of the encoding process is much closer in entropy to the source and therefore, a better way to compress the data than the reference design [1]. The combination of both Huffman and Arithmetic encoding on the configurable dual-path architecture of the CDP-HAE enables the CDP-HAE to select between Huffman and Arithmetic encoding based on the statistical characteristics of the symbols in the input data. Additionally, with the assistance of a configurable selection method used to optimize its operation for mixed-statistics data, a superior compression ratio of 1.10 was attained. The CDP-HAE achieves compression performance equivalent to conventional Huffman encoders for application-specific datasets, while delivering up to 10% higher compression ratio compared to Huffman-only encoding and approximately 5.8% improvement over Arithmetic-only encoding on mixed-statistics data through its configurable selection mechanism. Therefore, the implied increase in CE of the proposed CDP-HAE is due to its flexibility. The adaptive quotient encodings of the CDP-HAE provide a consistently better compression capability than the traditional Huffman encoders with respect to JPEG image data.

5. Applications

The proposed configurable dual-path Huffman-Arithmetic encoder architecture is well-suited for a wide range of data-intensive and resource-constrained digital systems. The embedded systems and IoT [3] device domain, which has limited bandwidth, memory, and power, is the primary area of application. In contrast, the configurable compression front end enables substantial data-size reduction before transmission or storage, thereby decreasing communication overhead and prolonging IoT device battery lifetime. Edge devices in the IoT, such as those sending periodic sensor readings, logging events, and performing firmware updates, would especially benefit from this application.

The architecture could also be utilized in secure communications, where it is commonplace to compress [6] the data before encrypting the data for increased transmission efficiency. By implementing the proposed encoder as a preprocessing step, the volume of data entering the encryption/decryption modules will decrease, resulting in a reduction in computational load and energy consumption without sacrificing data integrity. In addition, the adaptability of the proposed encoder allows it to accommodate a wide range of statistical characteristics, making it well-suited for use in medical and industrial data acquisition systems that require lossless compression to generate accurate reconstructions of the data.

In the area of multimedia and image processing [6], such as real-time acquisition of images or transmission of scientific data in a constrained bandwidth environment. The ability of the configurable dual-path encoder to dynamically select the optimal encoding mode will enable it to maximize the efficiency of compression while minimizing latency. Therefore, it will be able to adapt to heterogeneous data streams with different statistical properties.

6. Conclusions

The configurable dual-path Huffman-Arithmetic encoder (CDP-HAE) is presented in this paper as a method for balancing the long-standing issue of throughput, power efficiency and compression performance between lossless data compression architectures. The new data compression architecture employs shared preprocessing stages, two parallel paths for entropy coding, and a selective output mechanism allowing for adaptive encoding to be performed from a single bitstream using only necessary bandwidth. In order to validate the feasibility of the architecture, the CDP-HAE was implemented using ASIC synthesis in a 90nm CMOS technology, and the results confirm that the area, timing, and power characteristics of the implementation met the technology constraints. The CDP-HAE was also implemented in order to evaluate scalability and make fair comparisons to previously published FPGA-based reference designs. The FPGA implementation was evaluated on an Artix-7 (A7-100T) FPGA and achieved an operating frequency of up to 200 MHz, corresponding to a reduction in critical path delay to 5.02 ns, while still maintaining a comparable LUT-Delay Product with other designs from the literature, despite the additional dual-path capabilities. The CDP-HAE architecture is shown to consume a total power consumption of 0.268 W based on a power analysis study performed on an FPGA. This is considerably less than most other referenced designs evaluated based on the same metrics. Improved efficiencies were achieved through the appropriate utilization of logic sharing amongst processing elements and managing the switching activities during the process. This indicates the capability of a high-performance compression architecture to outperform other traditional architectures without consuming more than the amount of power necessary to do so. The compression evaluations conducted indicate that the CDP-HAE has an actual compression capability that is quite comparable to the original Huffman encoders built for the application-specific type data. Additionally, with the assistance of a configurable selection method used to optimize its operation for mixed-statistics data, a superior compression ratio of 1.10 was attained. The CDP-HAE achieves compression performance equivalent to conventional Huffman encoders for application-specific datasets, while delivering up to 10% higher compression ratio compared to Huffman-only encoding and approximately 5.8% improvement over Arithmetic-only encoding on mixed-statistics data through its configurable selection mechanism. Through these results, it is clear that the CDP-HAE offers a scalable, power-efficient, and adaptable lossless compression option and is therefore very appropriate for use in embedded and communications systems that require high-speed and low-power operation, within both ASIC and FPGA implementations.