Search Results (272)

We developed an AI-assisted zero-trust control system at low capital expenditure to retrofit brownfield Ethernet environments without disruptive hardware upgrades or costly software-defined networking migration. Legacy network infrastructures in small and medium-sized enterprises (SMEs) lack the flexibility and programmability required by modern zero-trust architectures, creating a persistent security gap between static Layer-1 deployments and dynamic cyber threats. The developed system addresses this gap through a modular architecture that integrates genetic-algorithm-based virtual local area network (VLAN) optimization, large language model-guided firewall rule synthesis, threat-intelligence-driven policy automation, and telemetry-triggered adaptive isolation. Network assets are enumerated and evaluated through a risk-aware clustering model to enable micro-segmentation that aligns with the principle of least privilege. Optimized segmentation outputs are translated into pfSense firewall policies through structured prompt engineering and dual-stage validation, ensuring syntactic correctness and semantic consistency. A retrieval-augmented generation pipeline connects live telemetry with historical vulnerability intelligence, enabling rapid policy adjustments and automated containment responses. The system operates as an overlay on existing managed switches, orchestrating configuration changes through standards-compliant interfaces such as simple network management protocol and network configuration protocol. Experimental evaluation in a representative SME testbed demonstrates substantial improvements in segmentation granularity, refining seven flat subnets into thirty-four purpose-specific VLANs. Compliance scores improved significantly, with the International Organization for Standardization/International Electrotechnical Commission 27001 rising from 62.3 to 94.7% and the National Institute of Standards and Technology Cybersecurity Framework alignment increasing from 58.9 to 91.2%. All 851 automatically generated firewall rules passed dual-agent validation, ensuring reliable enforcement and enhanced auditability. The results indicate that the system developed provides an operationally feasible pathway for legacy networks to achieve zero-trust segmentation with minimal cost and disruption. Future extensions will explore adaptive learning mechanisms and hybrid cloud support to further enhance scalability and contextual responsiveness. Full article

This paper proposes the development of an IEC 61850-compliant platform that is readily programmable and deployable for future digital twin applications. Given the compatibility between IEC-61850 and digital twin concepts, a focused case study was conducted involving the robust development of a Raspberry Pi platform with protection relay functionality using the open-source libIEC61850 library. Leveraging IEC-61850’s object-oriented data modelling, the relay can be represented by fully consistent virtual and physical models, providing an essential foundation for accurate digital twin instantiation. The relay implementation supports high-speed Sampled Value (SV) subscription, real-time RMS calculations, IEC Standard Inverse overcurrent trip behaviour according to IEC-60255, and Generic Object-Oriented Substation Event (GOOSE) publishing. Further integration includes setting group functionality for dynamic parameter switching, report control blocks for MMS client–server monitoring, and GOOSE subscription to simulate backup relay protection behaviour with peer trip messages. A staged development methodology was used to iteratively develop features from simple to complex. At the end of each stage, the functionality of the added features was verified before proceeding to the next stage. The integration of the Raspberry Pi into Curtin’s IEC = 61,850 digital substation was undertaken to verify interoperability between IEDs, a key outcome relevant to large-scale digital twin systems. The experimental results confirm GOOSE transmission times below 4 ms, tight adherence to trip-time curves, and performance under higher network traffic. Such measured RMS and trip-time errors fall well within industry and IEC limits, confirming the reliability of the relay logic. The takeaways from this case study establish a high-performing, standardised foundation for a digital twin system that requires fast, bidirectional communication between a virtual and a physical system. Full article

This article focuses on power supply control issues in high-speed switched reluctance motors (SRMs). The primary scientific objective of this study was to determine whether and to what extent, the controller itself imposes limitations on SRM drive operation at very high rotational speeds, and to identify the maximum achievable speed range resulting from these limitations. Unlike most existing studies, which focus mainly on motor or power electronics constraints, this work explicitly analyses the dynamic limitations introduced by the control system architecture. An analysis of the essential controller functionalities required for implementing the SRM drive control algorithm with a C-dump converter was performed. The control system, composed of specialised hardware modules operating concurrently, was implemented in an field-programmable gate array (FPGA) device. Simulation and experimental investigations were conducted to evaluate signal propagation delays within the FPGA and their impact on the motor control process. Key functional modules contributing to the maximum signal propagation delays were identified, enabling a direct determination of the maximum motor speed at which correct power supply operation can be ensured. Furthermore, delays introduced by the power electronic components were characterized for the developed test controller, allowing a comprehensive assessment of both control and hardware-induced speed limitations. The research concluded that the FPGA-based controller introduces no significant limitations to the drive’s maximum speed. The maximum speed is limited by the mechanical constraints of the rotor and the inertia of the phase windings. Furthermore, expanding the controller with additional functionality does not significantly slow down the control algorithm’s execution. Full article

A central challenge in reconfigurable photonics based on quasi bound states in the continuum (quasi-BICs) is to move beyond binary switching toward multistate and polarization-aware programmability. Here we propose a dual-phase-change material (PCM) metasurface that enables four-state nonvolatile switching and polarization-divergent dispersion rewriting within a single unit cell. Two independently switchable PCM layers provide four addressable configurations (0-0, 0-1, 1-0, 1-1) at a fixed geometry, allowing the resonance landscape to be reprogrammed through complex-index rewriting without structural modification. Angle-resolved transmission maps reveal fundamentally different evolution pathways for orthogonal polarizations. For p polarization, the quasi-BIC exhibits strong state sensitivity with dispersion reshaping and multi-branch features near normal incidence; the resonance red-shifts from ~1331 nm to ~1355 nm while the quality factor decreases from ~6.7 × 10⁴ to ~4.0 × 10⁴. In contrast, for s polarization, a single weakly dispersive branch translates coherently across states, producing a much larger shift from ~1635 nm to ~1790 nm while the quality factor increases from ~9.0 × 10³ to ~1.8 × 10⁴. The opposite quality-factor trajectories, together with the polarization-contrasting tuning ranges, demonstrate that dual-PCM programming reconfigures polarization-selective radiative coupling rather than imposing a uniform resonance shift. This compact two-bit metasurface platform provides multistate, high-Q control with active dispersion engineering, enabling polarization-multiplexed reconfigurable filters, state-addressable sensors, and other programmable photonic devices. Full article

This paper presents the design and implementation of the Power Stage GAIA (PSG), a high-current digital bias board developed by the Italian National Institute for Astrophysics (INAF) to extend the capabilities of the GAIA bias system. The PSG was developed within the Advanced European THz Receiver Array (AETHRA) project to support next-generation cryogenic receivers for millimeter-wave astronomy. Specifically, the AETHRA Work Package 1 (WP1) W-band downconverter integrates Monolithic Microwave Integrated Circuits (MMICs) requiring currents significantly exceeding the 50 mA limit of standard bias boards. To address these requirements, the PSG introduces a modular extension providing ten independent channels, each capable of delivering up to 500 mA with a programmable output range of 0–5 V. A key feature of the design is the adoption of a fully linear architecture based on LT1970 power amplifiers and INA225 precision sensors managed via an I²C digital interface. This approach ensures the high current capability required by modern power amplifiers while strictly avoiding the spectral noise and Radio Frequency Interference (RFI) typical of switching power supplies. Experimental validation confirms the system’s robustness and precision: the board demonstrated linear operation up to 460 mA and exceptional long-term stability, with a measured RMS voltage deviation below 50 µV. These results establish the PSG as a scalable, low-noise solution suitable for biasing high-power MMICs in future cryogenic receiver arrays. Full article

The coexistence of heterogeneous congestion control algorithms causes network unfairness and performance degradation. However, existing solutions suffer from the following issues: poor isolation reduces the overall performance, while sensitivity to tuning complicates deployment. In this work, we propose Warbler, a machine learning-driven active queue management (AQM) framework. Warbler classifies flows based on traffic characteristics and utilizes machine learning to adaptively control the bandwidth allocation to improve fairness. We implemented and evaluated the Warbler prototype on a programmable switch. The experimental results show that Warbler significantly improves the network performance, achieving a near-optimal Jain’s fairness index of 0.99, while reducing the delay to 60% of the baseline, cutting jitter by half, and saving 43% of buffer usage. In terms of scalability, it supports 10,000 concurrent long flows with latency below 0.7 s. The Warbler has a low cost and strong adaptability with no need for precise tuning, demonstrating its potential in dealing with heterogeneous CCAs. Full article

Laser pulses are essential in various scientific fields, yet existing laser diode drivers offer limited adjustability. This paper presents a digitally adjustable subnanosecond gain-switched laser diode driver, a first one with step sizes of the control being in the single-digit picosecond range. The proposed circuit differentially drives the laser diode (LD) using two high-current gate drivers whose relative delay is digitally adjusted by a dual programmable delay line. Pulse width is defined by the delay difference between the two channels, enabling fine control without the need for high-speed semiconductor switching. Experimental results demonstrate stable optical pulse generation with widths tunable from $350ps$ to $2.8ns$ in $9ps$ increments and repetition rates exceeding $150MHz$. Timing jitter remains below $15ps$, and amplitude variation is below 1% across the tested operating conditions. The proposed solution provides a compact, low-cost, and highly adjustable platform for applications that require precise timing and pulse-width control, such as time-resolved measurements, range finding, and nonlinear optical excitation. Full article

Neuroblastoma is an embryonal tumour that arises from the malignant transformation of neural crest cells and remains one of the deadliest malignancies in children under five. Neural crest development is regulated by dynamic switches in transcriptional programmes, guided by a variety of growth factors. Due to its developmental origin, neuroblastoma is unique in that these tumours often retain overactivation of growth factor signalling, which can be targeted by receptor tyrosine kinase (RTK) inhibitors. However, mutations in kinases, except for ALK, are extremely rare in neuroblastoma. Furthermore, the high degree of intratumoural heterogeneity often renders RTK inhibition ineffective as a monotherapy. For high-risk tumours, which lack effective treatment options, there remains an unmet need for targeted therapies. This review summarises the roles of growth factor receptors in neural crest and neuroblastoma development in light of recent single-cell studies. We provide a systematic overview of RTK inhibitors that can target growth factor signalling in neuroblastoma and detail their current status in clinical development. We also explore the role of intratumoural heterogeneity in resistance to RTK inhibitors, focusing on the adrenergic-to-mesenchymal transition, which drives a switch in growth factor receptor expression. Finally, we discuss strategies to overcome RTK inhibitor resistance by targeting neuroblastoma cell plasticity, disrupting downstream signalling pathways, or inhibiting escape mechanisms from cell death. This review provides a theoretical basis for developing novel combination therapies incorporating RTK inhibitors. Full article

The deparser stage in the Protocol-Independent Switch Architecture (PISA) is often overshadowed by parser and match-action optimizations. Yet, it remains a critical performance bottleneck in P4-programmable FPGA data planes. Challenges associated with the deparser stem from dynamic header layouts, variable emission orders, and alignment constraints, which often necessitate resource-intensive designs, such as wide, dynamic crossbar routing. While compile-time specialization techniques can reduce logic usage, they sacrifice runtime adaptability: any change to the protocol graph, including adding, removing, or reordering headers, requires full hardware resynthesis and re-implementation, limiting their practicality for evolving or multi-tenant workloads. This work presents a unified FPGA-targeted deparser architecture that merges templated and overlay concepts within a hardware–software co-design framework. At design time, template parameters define upper bounds on protocol complexity, enabling resource-efficient synthesis tailored to specific workloads. Within these bounds, runtime reconfiguration is supported through overlay control tables derived from static deparser DAG analysis, which capture the per-path emission order, header alignments, and offsets. These tables drive protocol-agnostic, chunk-based emission blocks that eliminate the overhead of crossbar interconnects, thereby significantly reducing complexity and resource usage. The proposed design sustains high throughput while preserving the flexibility needed for in-field updates and long-term protocol evolution. Full article

This paper presents a Field-Programmable Gate Array (FPGA)-based Hardware-in-the-Loop (HIL) simulation of an Interleaved Boost Power Factor Correction (PFC) converter using the Sub-Cycle Average (SCA) modeling technique. The main objective is to achieve accurate real-time simulation performance given the hardware constraints of low-cost FPGAs. By combining the SCA modeling approach with a time-averaging correction method, the proposed model effectively reduces sampling delays and duty-cycle estimation errors arising from asynchronous Pulse Width Modulation (PWM) signal acquisition. The SCA-based converter model and time-averaging correction technique were implemented in MATLAB/Simulink R2024b using the HDL Coder environment. To validate real-time simulation accuracy, power factor improvement was evaluated for a two-phase Interleaved Boost PFC operating at a switching frequency of 60 kHz. Experimental results confirm that the proposed approach enables accurate Controller–HIL testing of power converters, even when implemented on low-cost FPGA platforms such as the Zybo Z7-10 evaluation board. Full article

Body-contouring devices deliver controlled thermal energy to treat cellulite, reduce localized fat, and improve skin elasticity. Since the thermal effect is closely related to the delivered RF output power, precise control of the output power is critical for both efficacy and safety. In this study, we propose a 2.4 GHz CMOS pulse-mode transmitter for body-contouring device applications, featuring precise control of the average power delivered to the body. The transmitter comprises a fully integrated phase-locked loop (PLL) synthesizer, pulse modulator (PM), and 10 mW power amplifier (PA). It is fabricated in a 65 nm CMOS with a compact die area of 3.75 mm². The PA provides four-level continuous-mode output control from −0.3 dBm to 11.1 dBm, and the PM performs programmable PA switching for pulse-mode operation of the PA with a wide range of pulse rates and duty ratios. By combining the continuous-mode output power control and pulse-mode on–off time regulation, the average output power delivered to the skin is finely controlled, managing the delivered power within a safe skin temperature below 65 °C. The PLL loop filter is fully integrated with a wide programmability, improving the form factor and bill of materials for the target devices. Measurement results confirm that the designed transmitter can accurately control both the average output power and pulse profile across the 2.4 GHz ISM band, demonstrating its suitability for compact home-use RF body-contouring devices. Full article

Smart nucleic acid hydrogels (SNAHs), endowed with stimulus responsiveness, function as programmable molecular switches that can perceive diverse external stimuli and undergo rapid, reversible, and highly specific conformational or performance changes. These dynamic properties have enabled the rational design of biosensors with bionic behaviors, facilitating cascaded “recognition–decision–execution” processes that support advanced biological analysis. Consequently, SNAHs are recognized as a core breakthrough for the next generation of intelligent biosensing units. However, a systematic mapping between SNAH design strategies, specific stimuli, and application fields remains lacking. This review mainly analyzes advances in SNAH-based biosensors over the past five years, proposing flexible and feasible design strategies and key trends in customization. Firstly, we systematically summarize molecular recognition modules involved in the construction of SNAHs, including aptamers, DNAzymes, antibodies, and specific binding peptides. Subsequently, we elaborate on the responses of these modules to external stimuli, so as to further facilitate the signal transduction of signals derived from physical, chemical, and biological sources involving temperature, light, magnetic fields, pH, nucleic acids, proteins, other biomolecules, and pathogens. Additionally, the review outlines the research progress of SNAHs in environmental monitoring, food safety, and medical diagnostics. Finally, we provide an integrated perspective on future opportunities and challenges, highlighting the innovative framework for designing SNAH-based biosensors and offering a practical roadmap for next-generation intelligent sensing applications. Full article

The advent of sixth-generation (6G) communications envisions a paradigm of ubiquitous intelligence and seamless physical–digital fusion, demanding unprecedented performance from the optical transport infrastructure. Achieving terabit-per-second capacities, microsecond latency, and nanosecond synchronisation precision requires a convergent, flexible, open, and AI-native x-Haul architecture that integrates communication with distributed edge computing. This study conducts a systematic literature review of recent advances, challenges, and enabling optical technologies for intelligent and autonomous 6G networks. Using the PRISMA methodology, it analyses sources from IEEE, ACM, and major international conferences, complemented by standards from ITU-T, 3GPP, and O-RAN. The review examines key optical domains including Coherent PON (CPON), Spatial Division Multiplexing (SDM), Hollow-Core Fibre (HCF), Free-Space Optics (FSO), Photonic Integrated Circuits (PICs), and reconfigurable optical switching, together with intelligent management driven by SDN, NFV, and Artificial Intelligence/Machine Learning (AI/ML). The findings reveal that achieving 6G transport targets will require synergistic integration of multiple optical technologies, AI-based orchestration, and nanosecond-level synchronisation through Precision Time Protocol (PTP) over fibre. However, challenges persist regarding scalability, cost, energy efficiency, and global standardisation. Overcoming these barriers will demand strategic R&D investment, open and programmable architectures, early AI-native integration, and sustainability-oriented network design to make optical fibre a key enabler of the intelligent and autonomous 6G ecosystem. Full article

Despite the obvious shift in daily commuting towards electromobility, internal combustion engines (ICEs) still dominate the market, particularly in the transport sector. Their main drawback—cold-start emissions—has driven the development of active control strategies beyond passive exhaust optimizations. An electrically heated catalytic converter (EHC) helps the catalytic converter reach the light-off temperature more quickly through active control; however, it places additional demands on the already strained onboard electrical power distribution network. This paper presents a case study comparing two power supply and control configurations for managing the temperature of the EHC: (i) a smart-switch-based approach using bang-bang control, and (ii) a DC/DC converter with a proportional–integral–derivative (PID) controller. To define key target requirements for a dedicated DC/DC converter suitable for real-world conditions, measurement data such as temperature and electrical power demand were gathered through preliminary pollutant emissions tests performed in a laboratory environment using a programmable bench power supply. For the selected test procedure, engine cold-start emissions using various heater power supply scenarios were reduced by a factor of 6 for Total Hydrocarbons (THC) and by a factor of 5 for Carbon Monoxide (CO). Based on a comparative analysis of power supply parameters, a custom four-leg interleaved Buck converter was developed to meet the target power requirement and to specifically reduce voltage overstress caused by parasitic inductances in the onboard distribution network during rapid load current transients. The efficiency of the proposed DC/DC converter reached 95.8%. Unlike a bang-bang-controlled smart switch, the use of the DC/DC converter reduces both electrical and thermal stress on the vehicle’s cable harness. Full article

Programmable data planes are increasingly essential for enabling In-band Network Telemetry (INT), fine-grained monitoring, and congestion-aware packet processing. Although the P4 language provides a high-level abstraction to describe such behaviors, implementing them efficiently on FPGA-based platforms remains challenging due to hardware constraints and limited compiler support. Building on P4THLS framework, which leverages HLS for FPGA data-plane programmability, this paper extends the approach by introducing support for P4-style stateful objects and a structured metadata propagation mechanism throughout the processing pipeline. These extensions enrich pipeline logic with real-time context and flow-level state, thereby facilitating advanced applications while preserving programmability. The generated codebase remains extensible and customizable, allowing developers to adapt the design to various scenarios. We implement two representative use cases to demonstrate the effectiveness of the approach: an INT-enabled forwarding engine that embeds hop-by-hop telemetry into packets and a congestion-aware switch that dynamically adapts to queue conditions. Evaluation of an AMD Alveo U280 FPGA implementation reveals that incorporating INT support adds roughly 900 LUTs and 1000 Flip-Flops relative to the baseline switch. Furthermore, the proposed meter maintains rate measurement errors below 3% at 700 Mbps and achieves up to a 5× reduction in LUT and 2× reduction in Flip-Flop usage compared to existing FPGA-based stateful designs, substantially expanding the applicability of P4THLS for complex and performance-critical network functions. Full article