Search Results (139)

In the last few years, Thin Film Transistors (TFTs) based on materials such as amorphous Indium–Gallium–Zinc Oxide (a-IGZO) have gained interest in large-area and low-cost electronics due to their high carrier mobility, high on/off current ratio, low off-state current, and steep subthreshold slope. These characteristics make IGZO TFTs suitable for radio-frequency identification (RFID) tags, analog-to-digital converters (ADCs), logic circuits, sensors, and analog components, including operational amplifiers (OPAMPs). This work presents the implementation and characterization of an OPAMP based on n-type a-IGZO TFTs fabricated on glass substrate. Two previously reported design strategies were integrated: a positive feedback network to increase the output impedance and a topology to enhance the transconductance of the driver transistors, both in the differential input stage. A gain of 26 dB, a bandwidth of 2.4 kHz, a gain–bandwidth product (GBWP) of 48 kHz, and a phase margin of 64° were obtained, which confirms the reliability of the design and the fabrication process. Full article

In this paper, complementary metal-oxide semiconductor (CMOS) circuit realization of a low-pass elliptic filter of order (1 + α) is realized using the inverse follow-the-leader feedback (IFLF) topology. The transfer functions to approximate the passband and stopband ripple characteristics of the second-order elliptic low-pass filter are synthesized using the nonlinear least squares (NLS) optimization routine. The elliptic filters of orders 1.4, 1.6, and 1.8 are designed using a cross-coupled operational transconductance amplifier (OTA) in the United Microelectronics Corporation (UMC) 180 nm CMOS process. The dynamic range of the filter was found to be 49.7 dB, 52.08 dB, and 54.02 dB for an order of 1.4, 1.6, and 1.8, respectively. The circuit simulation results such as magnitude, phase, transient, and group delay plots, are validated with the MATLAB simulation plots. Monte Carlo and PVT analyses have demonstrated the accuracy and robustness of the design. The proposed approach supports quality education and industry, innovation, and infrastructure. Full article

The proposed work introduces a sizing algorithm to achieve a desired linear transconductance in the optimization of operational transconductance amplifiers (OTAs) by applying the $g_m/I_D$ method to find the initial width (W) and length (L) sizes of the transistors. These size values are used to run the non-dominated sorting genetic algorithm (NSGA-II) to perform a multi-objective optimization of three OTA topologies. The $g_m/I_D$ method begins with transistor characterization using MATLAB R2024a generated look-up tables (LUTs), which map normalized transconductance of the transistor channel dimensions, and key performance metrics of a complementary metal–oxide–semiconductor (CMOS) technology. The LUTs guide the initial population generation within NSGA-II during the optimization of OTAs to achieve not only a desired transconductance but also accuracy alongside linearity, high DC gain, low power consumption, and stability. The feasible W/L size solutions provided by NSGA-II are used to enhance the CMOS design of a memristor emulator, where the OTA with the desired transconductance is adapted to tune the behavior of the memristor, demonstrating improved pinched hysteresis loop characteristics. In addition, process, voltage and temperature (PVT) variations are performed by using TSMC 180 nm CMOS technology. The memristor-based on optimized OTAs is used to design a Leaky Integrate-and-Fire (LIF) neuron, which produces identical spike counts (seven spikes) under the same input conditions, though the time period varied with a CMOS inverter scaling. It is shown that increasing transistor widths by 100 in the inverter stage, the spike quantity is altered while changing the spiking period. This highlights the role of device sizing in modulating LIF neuron dynamics, and in addition, these findings provide valuable insights for energy-efficient neuromorphic hardware design. Full article

In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near $V_{\mathrm{DD}}/4$ per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows $|S_{21}|$ = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power $P_{\mathrm{sat}}=8.67$ dBm at $V_{\mathrm{DD}}=4$ V, with $S_{11}<-15$ dB and reverse isolation $\approx -16$ dB. The layout occupies $1.6\times 1.6$ mm² and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of $P_{\mathrm{sat}}$ and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs ($\pm 10\%$ devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends. Full article

This paper presents a novel low-power, high-quality factor, and wide-tunable CMOS active inductor based on the gyrator-C configuration. The G_m-boosting technique is employed to reduce power consumption and noise while enhancing the transconductance. The inclusion of a feedback resistor further improves the quality factor. The designed active inductor operates up to 4.1 GHz, offers a wide inductance tuning range from 4.5 nH to 215 nH, consumes only 1.82 mW at 1.8 V supply, and occupies a compact area of 0.0006 mm². The input-referred current noise is as low as $27\mathrm{p}\mathrm{A}\sqrt{\mathrm{H}\mathrm{z}}$. This study aims to provide an effective solution to the large area requirements of traditional passive inductors, while simultaneously improving key performance parameters with minimal compromise by introducing a novel active inductor design. The proposed design also exhibits superior performance in key specifications compared with existing active inductor implementations. For demonstration purposes, the active inductor is incorporated into a broadband RF amplifier, achieving near-ideal behavior across the 0.8–2.1 GHz. Corner and Monte Carlo analyses, along with temperature sweep and stability analyses, were carried out to validate the reliability and robustness of the proposed design. Results confirm the effectiveness of the G_m-boosted active inductor for high-performance RF applications, making it a promising candidate for 5G and beyond future wireless communication systems. Full article

This paper presents a high-efficiency, nW-level operational transconductance amplifier (OTA) capable of operating at 0.3 V with rail-to-rail input and output. The design utilizes a bulk-driven technique in the input stage to extend the common-mode input range under ultra-low-voltage conditions. A simplified intermediate stage ensures reliable MOS operation at ultra-low-voltage levels while reducing power consumption, and a modified Class-AB controlled output stage facilitates rail-to-rail output and enhances current efficiency. Fabricated using SMIC 0.18 $\mathsf{\mu }$m technology and operating at a 0.3 V supply, the OTA achieves a DC gain of 63.07 dB, phase margin of 61.5°, a gain-bandwidth product of 37.68 kHz, and a slew rate of 21.85 V/ms while consuming only 123 nW with a 60 pF load. The design also demonstrates superior small-signal figures of merit (12.25 MHz·pF/$\mathsf{\mu }$W) and large-signal figures of merit (10.66 V/$\mathsf{\mu }$s·pF/$\mathsf{\mu }$W) compared to state-of-the-art low-voltage OTAs. These results indicate that the proposed amplifier offers a balanced solution of low power consumption, wide bandwidth, and high slew rate, making it well-suited for energy-constrained applications such as portable electronics, IoT sensors, and biomedical devices. Full article

This paper presents a new operational transconductance amplifier (OTA) design for batteryless biomedical front-ends. The proposed OTA operates in the subthreshold region and utilizes self-cascode devices to achieve ultra-low power, low noise, and a high common-mode rejection ratio ($CMRR$). Post-layout simulations in Cadence, using 45 nm CMOS technology with 0.9 V supply voltage, show a power consumption of 49.3 nW, a $CMRR$ of 144.9 dB, an input-referred noise of 4.51 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$ integrated over 0.5–208 Hz, and a noise efficiency factor of 1.023 with a core silicon area of 0.00138 mm². Using the proposed OTA, we implemented a 10-channel neural recording amplifier for Local Field Potentials (LFPs) based on a capacitively coupled, capacitive-feedback (CC-CF) topology with a body-driven pseudo-resistor high-pass path. The system achieves a total $CMRR$ ≥ 70 dB and an estimated power of 494.2 nW for 10 channels. Compared with prior art, the proposed OTA offers competitive noise efficiency and common-mode rejection at lower power, making it a viable building block for batteryless neural and biomedical sensing front-ends. Full article

Parallel-type slew-rate enhancers (PSREs) improve the driving capability of operational transconductance amplifiers (OTAs) for large capacitive loads. While capacitive-boosting (CB) techniques enhance PSRE efficiency in fully-differential designs, their application to single-ended configurations—common in off-chip load driving—remains unexplored. This work identifies a critical limitation of standard CB in single-ended unity-gain buffers: severe slew-rate degradation due to large common-mode input swings. To overcome this, we propose a novel split CB (SCB) technique for single-ended PSREs that strategically divides the boosting capacitance. Simulated in a 0.18-µm CMOS process, the proposed method achieves a ×5.53 reduction in settling time compared to standard CB when driving a 1-nF load. With only 4 µA quiescent current under a 3.3-V supply, it attains a 1% settling time of 2.56 µs for 2.64-V steps, demonstrating robust performance across process-voltage-temperature variations. This technique enables low-power, high-speed interfaces for drivers of off-chip devices. Full article

This study presents transistor-level simulation results for a novel memristor emulator circuit. The design incorporates an inverter and a current-mode-controlled operational transconductance amplifier to stabilize the output voltage. Transient performance is evaluated across a 20 MHz to 100 MHz frequency range. Simulations using 0.18 μm TSMC technology confirm the circuit’s functionality, demonstrating a power consumption of 0.1 mW at a 1.2 V supply. The memristor model’s reliability is verified through corner simulations, along with Monte Carlo and temperature variation tests. Furthermore, the emulator is applied in a Memristive Integrate-and-Fire neuron circuit, a CMOS-based system that replicates biological neuron behavior for spike generation, enabling ultra-low-power computing and advanced processing in retinal prosthesis applications. Full article

A dual Al₂O₃ MIS gate structure is proposed to enhance the DC and RF performance of enhancement-mode GaN high-electron mobility transistors (HEMTs). As a result, the proposed MOS-HEMT with a dual recessed MIS gate structure offers 84% improvements in cutoff frequency (f_T) and 92% improvements in maximum oscillation frequency (f_max) compared to conventional HEMTs (from 7.1 GHz to 13.1 GHz and 17.5 GHz to 33.6 GHz, respectively). As for direct-current characteristics, a remarkable reduction in off-state gate leakage current and a 26% enhancement in the maximum saturation drain current (from 519 mA·mm⁻¹ to 658 A·mm⁻¹) are manifested in HEMTs with new structures. The maximum transconductance (g_m) is also raised from 209 mS·mm⁻¹ to 246 mS·mm⁻¹. Correspondingly, almost unchanged gate–source capacitance curves and gate–drain capacitance curves are also discussed to explain the electrical characteristic mechanism. These results indicate the superiority of using a dual Al₂O₃ MIS gate structure in GaN-based HEMTs to promote the RF and DC performance, providing a reference for further development in a miniwatt antenna amplifier and sub-6G frequencies of operation. Full article

Energy-efficient integrated circuits require scaled-down supply voltages, posing challenges for analog design, particularly for operational transconductance amplifiers (OTAs) essential in high-accuracy CMOS feedback systems. Below 1 V, gate-driven OTAs are limited in common-mode input range and minimum supply voltage. This work investigates CMOS Bulk-Driven (BD) sub-threshold techniques as an efficient alternative for ultra-low voltage (ULV) and ultra-low power (ULP) designs. Although BD overcomes MOS threshold voltage limitations, historical challenges like lower transconductance, latch-up, and layout complexity hindered its use. Recent advancements in CMOS processes and the need for ULP solutions have revived industrial interest in BD. Through theoretical analysis and computer simulations, we explore BD topologies for ULP OTA input stages, classifying them as tailed/tail-less and class A/AB, evaluating their effectiveness for robust analog design, while offering valuable insights for circuit designers. Full article

This paper presents a fully integrated bandpass filter (BPF) with high tunability based on a novel differential active inductor (DAI), designed for sensor interface circuits operating in the ultra-high frequency (UHF) band. The design of the proposed DAI is based on a symmetrical configuration, utilizing a differential amplifier for the feedforward transconductance and a common-source (CS) transistor for the feedback transconductance. By integrating a cascode scheme with a feedback resistor, the quality factor of the active inductor is significantly improved, leading to enhanced mid-band gain for the bandpass filter. To facilitate independent tuning of the BPF‘s center frequency and mid-band gain, an active resistor adjustment and bias voltage control are employed, providing precise control over the filter’s operational parameters. Post-layout simulations and process corner results are conducted with 0.13 µm CMOS technology at 1.2 V supply voltage. The proposed second order BPF achieves a broad tuning range of 280 MHz to 2.426 GHz, with a passband gain between 8.9 dB and 16.54 dB. The design demonstrates a maximum noise figure of 16.54 dB at 280 MHz, an input-referred 1 dB compression point of −3.78 dBm, and a third-order input intercept point (IIP3) of −0.897 dBm. Additionally, the BPF occupies an active area of only 68.2×30 µm², including impedance-matching part, and consumes a DC power of 14–20 mW. The compact size and low power consumption of the design make it highly suitable for integration into modern wireless sensor interfaces where performance and area efficiency are critical. Full article

In this paper, we present a novel enhanced recycling folded cascode (ERFC) operational transconductance amplifier (OTA), which exhibits high efficiency and a fast transient response under weak inversion. Our innovative combination of adaptive biasing with nested local feedback (ABNLF) effectively enhances the input transconductance and slew rate (SR), thus improving the transient response. By incorporating coupling capacitors at the output stage, we achieve a stable operating region with large signal responses. Both the traditional RFC OTA and the proposed ERFC OTA were designed in a 0.18 $\mathsf{\mu }$m CMOS process, operating at a power supply of 1.8 V, with quiescent currents of 8 $\mathsf{\mu }$A and 10.4 $\mathsf{\mu }$A, respectively. Post-layout simulations reveal a remarkable enhancement in the proposed ERFC OTA over the traditional RFC OTA, with the SR and gain–bandwidth (GBW) surging by 120- and 5.95-fold, respectively. This advancement boosts the efficiency of the traditional RFC OTA and provides an impressive figure of merit (FoM) of 130.04 (V/$\mathsf{\mu }$s)·pF/$\mathsf{\mu }$A. Full article

We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μV_rms. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm². Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µV_rms over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 V_pp with a total harmonic distortion of −62.68 dB at 1 kHz. Full article

In this paper, a novel multiple-input operational transconductance amplifier (MI-OTA) is proposed. The MI-OTA can be obtained by using the multiple-input bulk-driven MOS transistor (MIBD MOST) technique. The circuit structure is simple, can operate with a supply voltage of 0.5 V, and consumes 937 pW at a current setting of 625 pA. The proposed MI-OTA was used to implement a high-order multiple-input voltage-mode universal filter. The proposed filter can provide non-inverting and inverting low-pass, high-pass, band-pass, band-stop, and all-pass transfer functions to the same topology. In addition, it has a high input impedance and does not need any inverted input signals, so there is no additional buffering circuit. The proposed filter can be used for biological signal processing. The proposed MI-OTA and the second-order universal filter were simulated in Cadence using CMOS process parameters of 0.18 μm from TSMC to verify the functionality and performance of the new structures. Full article