A 0.3 V High-Efficiency Bulk-Driven Rail-to-Rail OTA with High Gain-Bandwidth for Wearable Applications

Abstract

This paper presents a high-efficiency, nW-level operational transconductance amplifier (OTA) capable of operating at 0.3 V with rail-to-rail input and output. The design utilizes a bulk-driven technique in the input stage to extend the common-mode input range under ultra-low-voltage conditions. A simplified intermediate stage ensures reliable MOS operation at ultra-low-voltage levels while reducing power consumption, and a modified Class-AB controlled output stage facilitates rail-to-rail output and enhances current efficiency. Fabricated using SMIC 0.18 $\mathsf{\mu }$m technology and operating at a 0.3 V supply, the OTA achieves a DC gain of 63.07 dB, phase margin of 61.5°, a gain-bandwidth product of 37.68 kHz, and a slew rate of 21.85 V/ms while consuming only 123 nW with a 60 pF load. The design also demonstrates superior small-signal figures of merit (12.25 MHz·pF/$\mathsf{\mu }$W) and large-signal figures of merit (10.66 V/$\mathsf{\mu }$s·pF/$\mathsf{\mu }$W) compared to state-of-the-art low-voltage OTAs. These results indicate that the proposed amplifier offers a balanced solution of low power consumption, wide bandwidth, and high slew rate, making it well-suited for energy-constrained applications such as portable electronics, IoT sensors, and biomedical devices.

1. Introduction

With the rapid development of wearable health monitoring systems, the demand for ultra-low-power analog front-end circuits has become increasingly urgent [1,2]. These systems need to monitor weak bioelectrical signals such as electrocardiogram (ECG) and electroencephalogram (EEG), which typically range from $\mathsf{\mu }$V to mV levels, and amplify them to suitable levels (hundreds of mV) for subsequent processing. A typical wearable health monitoring system consists of sensor front-ends, signal conditioning circuits, analog-to-digital converters, digital signal processing units, wireless communication modules, and power management systems, as shown in Figure 1. Among these components, the amplifier serves as the core of the signal conditioning circuit. Its performance directly determines the monitoring accuracy and reliability of the entire system. However, wearable devices typically rely on button cell batteries with capacities of only tens to hundreds of mAh. This imposes extremely stringent constraints on the power consumption and operating voltage of amplifiers [3,4,5,6].

For wearable applications, amplifiers must simultaneously meet several critical technical specifications. First, ultra-low voltage (≤0.5 V) and ultra-low power consumption (nW level) are fundamental prerequisites for ensuring long-term continuous operation. Second, high gain (≥60 dB) and low noise characteristics are necessary for accurately capturing weak biological signals. Additionally, different biological signals have significantly different frequency ranges. For example, ECG signals are mainly distributed in 0.05–150 Hz, while EMG signals can exceed 500 Hz. This requires amplifiers to have sufficient bandwidth. More critically, under ultra-low voltage conditions, the signal swing space is extremely limited. For instance, with 0.3 V supply, the effective range may be less than 100 mV. Therefore, rail-to-rail input and output capability becomes essential for fully utilizing the voltage swing, improving dynamic range, and enhancing signal-to-noise ratio [7,8,9,10].

To meet the low-power requirements of wearable health monitoring systems, researchers have developed various techniques to reduce power consumption. These techniques primarily focus on two aspects: reducing supply voltage and decreasing current consumption. For low-voltage operation, bulk-driven technique adjusts the threshold voltage by applying appropriate bias voltage to the substrate of MOS transistors. This maintains sufficient gate-source overdrive voltage under low supply conditions, enabling transistors to operate normally at 0.6–0.8 V or even lower voltages. This technique provides an effective approach for implementing ultra-low-voltage amplifiers. However, it also introduces challenges. Substrate biasing introduces additional body effect, which reduces transistor transconductance and consequently affects the gain and bandwidth performance of amplifiers. Other techniques such as floating-gate and self-cascode structures have also been widely studied. However, the former requires additional initialization circuits and suffers from charge leakage issues, while the latter struggles to maintain stable operation below 0.4 V and cannot easily achieve rail-to-rail input-output capability. For current reduction, subthreshold operation is the most representative method. This technique operates MOS transistors in the subthreshold region, reducing operating current from $\mathsf{\mu }$A level to nA or even pA level. Transistors in the subthreshold region exhibit the highest gm/ID ratio, providing a theoretical foundation for achieving extremely low power consumption. However, subthreshold operation also has inherent limitations. The absolute transconductance value of transistors decreases significantly, limiting amplifier gain and bandwidth. Meanwhile, it is more sensitive to process variations, affecting circuit consistency and stability. Therefore, how to leverage bulk-driven technique for ultra-low voltage operation and subthreshold technique for ultra-low power consumption, while effectively overcoming the challenges of insufficient transconductance and limited gain-bandwidth, becomes the key challenge in designing ultra-low-voltage ultra-low-power amplifiers for wearable applications [11,12,13].

Notably, while significant progress has been made in slew-rate (SR) enhancement for standard-voltage amplifiers (1.2–1.8 V), existing techniques are poorly suited for ultra-low-voltage (≤0.5 V) scenarios. For example, the dynamic current injection method proposed in [14] boosts SR by adding transient bias current via extra transistors, but this requires ≥0.5 V voltage headroom to turn on the injection transistors—an impossible requirement under 0.3 V supply. Similarly, the capacitor cross-coupling technique in [15] relies on large coupling capacitors (≥100 fF) to optimize charge transfer, but these capacitors occupy excessive chip area (≈4000 $\mathsf{\mu }$m² in 0.18 $\mathsf{\mu }$m CMOS) and lose efficiency under limited 0.3 V voltage swing. Thus, how to leverage bulk-driven technique for ultra-low voltage operation and subthreshold technique for ultra-low power consumption, while developing an SR-boosting strategy compatible with 0.3 V supply (without sacrificing area or power), becomes the key challenge in designing ultra-low-voltage ultra-low-power amplifiers for wearable applications.

In terms of circuit architecture, the design adopts a carefully optimized three-stage structure. The input stage uses a bulk-driven differential pair. While achieving ultra-low voltage operation, it extends the input common-mode range through proper substrate biasing design, reaching complete rail-to-rail input capability. The introduction of an intermediate gain stage effectively boosts the overall gain without significantly increasing power consumption, providing necessary amplification capability for processing weak bioelectrical signals. The output stage employs a class-AB push-pull structure [16,17,18,19,20]. It not only achieves rail-to-rail output capability but also significantly improves load driving capability through the adaptive characteristics of the HABRtR technique. This ensures high efficiency and low distortion when driving subsequent circuits. To guarantee the stability of the three-stage structure, a dedicated frequency compensation network is designed to ensure stable operation under various working conditions [21,22,23,24].

The design characteristics of this amplifier are highly compatible with the requirements of wearable health monitoring systems. The 0.3 V ultra-low voltage operation capability makes it compatible with energy harvesting systems and miniature battery power supplies. The 123 nW ultra-low power consumption ensures the possibility of long-term continuous monitoring. The high gain and sufficient bandwidth brought by the HABRtR technique meet the requirements for precise amplification of weak biological signals. The complete rail-to-rail input-output capability maximizes the utilization of limited voltage swing, improving dynamic range and signal-to-noise ratio [25,26]. These characteristics make the proposed amplifier an ideal choice for wearable health monitoring applications, providing critical technical support for achieving long-term, reliable, and high-precision physiological parameter monitoring. Based on these innovative bulk-driven technologies, this paper presents a novel three-stage, ultra-low-voltage, and ultra-low-power rail-to-rail operational amplifier whose overall architecture is illustrated comprehensively in Figure 2 of the document.

The remainder of this paper systematically presents a detailed discussion of the proposed amplifier. Section 2 provides an in-depth introduction to the design principles and implementation methods of the ultra-low-voltage ultra-low-power rail-to-rail operational amplifier, including the overall three-stage architecture design, the gain and bandwidth optimized intermediate stage, the class-AB rail-to-rail output stage, and the frequency compensation technique for the multi-stage structure. Section 3 presents the implementation and simulation verification results of the amplifier. Through comprehensive performance metric testing and stability analysis, the reliability and practicality of the design are validated. Finally, Section 4 summarizes the main contributions of this research, analyzes the limitations of the current design, and discusses future research directions.

2. Overview of the Proposed OTA

2.1. Overall Circuit

Figure 3 shows the overall circuit of the OTA.The overall structure of the operational amplifier is divided into three stages. M0–M8 form the input stage using bulk-driven technology, which can achieve rail-to-rail input. The intermediate stage consists of M17–M22 and is mainly used to increase the gain. M25 and M26 form a Class-AB push-pull output structure, which is used to achieve rail-to-rail output. M9–M15 and M23–M24 serve as the bias circuit for the Class-AB output stage to control the bias current of the output stage. In addition, the reference current source provides the static current $I_B$ for the core working circuit, and capacitors $C_1$–$C_3$ are the Miller capacitors of the operational amplifier for frequency compensation. All transistors are operating in the subthreshold region by design, and the architecture is optimized to ensure saturation even with VDD = 0.3 V across all corners.

2.2. The Bulk-Driven Input Stage

The overall structure of the input stage is a folded cascode amplifier. M1 and M2 are two PMOS differential input pair transistors using bulk-driven technology. M5–M8 form the cascode output stage. M0 is the tail current source of the input differential pair transistors, and M3 and M4 provide bias currents for the cascode output stage. The input signal is input from the bulk terminals of M1 and M2, and the gate terminals of the two input transistors are connected to the low-level VSS of the circuit. The bias voltage $V_N$ of M5 and M6 is provided by the bias circuit.

Due to the depletion-type characteristics of bulk-driven MOS transistors, the effect of the threshold voltage ($V_{TH}$) on the input differential pair can be considered negligible. Therefore, for the input stage adopted in this paper, the maximum value of the common-mode input voltage is:

$$V_{CM,bdmax}=VDD-\left|V_{BS1,2}+V_{DSAT0}\right|$$

(1)

where $V_{BS1,2}$ is the bulk voltage of input differential pair M1 or M2, $V_{dsat0}$ is the overdrive voltage of tail current source transistor M0. $V_{BS1,2}$ can be a positive value, which allows $V_{CM}$, max to reach the supply voltage VDD. If M1 and M2 are traditional gate-driven differential pair, the maximum value of the input common-mode voltage at this time is:

$$V_{CM,gdmax}=VDD-V_{DSAT0}-V_{TH1,2}$$

(2)

Compared to gate-driven differential pairs, bulk-driven differential pairs offer an increased input common-mode range due to the reduction in threshold voltage, significantly extending the differential pair’s common-mode input range. It is worth noting that when the bulk-source junction is excessively forward-biased, the internal parasitic horizontal and vertical BJTs will turn on, causing the bulk current to increase exponentially and making the parasitic lateral BJT dominant. Therefore, the magnitude of common-mode voltage $V_{CM}$ must be carefully considered in circuit design. However, for the circuit designed in this paper, operating under a 0.3 V supply voltage cannot generate sufficient voltage to excessively forward-bias the bulk-source junction, thus effectively avoiding the occurrence of self-parasitic effects.

2.3. Intermediate Stage and Output Stage

To achieve rail-to-rail output of the signal, a Class-AB output structure is adopted in this paper. Since the output stage is associated with the intermediate stage, for the convenience of analyzing its working principle, the two stages are analyzed together.

The intermediate stage circuit is a common-source circuit with a current mirror as the load. To meet the design requirements of ultra-low-voltage and ultra-low-power consumption, a simplified circuit architecture with a minimal number of transistor stages was adopted. Therefore, the common-source configuration is chosen as the second stage of the amplifier. Additionally, to further increase the gain, a current mirror is selected as the load. Considering the choice of the output stage, the second-stage amplifier is designed with two outputs. The voltage signal is converted into a current signal through the action of the common-source transistor M17, and then converted back into a voltage signal through the current mirror loads M18–M19 (M18–M20). M21 and M22 provide bias currents for the two output branches, and their bias voltages are connected to the feedback amplifier that controls the push-pull output of the third stage.

The quiescent current of the output stage is controlled as follows: A quiescent current $I_1$ is provided to M11, it generates a voltage $V_{ref}$. The sizes of M14 and M15 are half of M12, and both transistors are in parallel, making them equivalent to a single transistor of the same size as M12. The following relationship holds:

$$V_{\mathrm{ref}}=V_{G14}=V_{G15}=V_{G26}$$

(3)

From (3), the gate voltage of M24 is equal to the gate voltage of M11. Therefore, M26 can form a current mirror with M11, and the quiescent current flowing through M26 as follows:

$$I_{D26}={\displaystyle \frac{{(W/L)}_{26}}{{(W/L)}_{11}}}{I}_1$$

(4)

Since the two branches of the amplifier in the biasing circuit are symmetrical, the currents flowing through the two branches are respective:

$$I_{D14}=I_{D12}={\displaystyle \frac{1}{2}}{I}_2$$

(5)

M21 and M22 respectively form two current mirrors with M13 and M16, so the current flowing through M19 and M20 is ${\displaystyle \frac{1}{2}}{I}_2$, and the quiescent current of M18 is also ${\displaystyle \frac{1}{2}}{I}_2$. At this point, by setting the size of M23 so that $V_A$ = $V_B$, the gate voltage of the output transistor M25 can be equal to the gate voltage of M18, and the quiescent current flowing through M25 can be obtained by mirroring M18.

$$I_{D25}={\displaystyle \frac{{(W/L)}_{25}}{{(W/L)}_{18}}}{I}_{D14}={\displaystyle \frac{1}{2}}{\displaystyle \frac{{(W/L)}_{25}}{{(W/L)}_{18}}}{I}_2$$

(6)

When $I_2$ is set to be 2$I_1$, the quiescent currents of the output PMOS and NMOS transistors will be equal. Therefore, the output stage transistors maintain a stable quiescent operating point, unaffected by the input common-mode voltage.With a unit quiescent current $I_B$ of 10 nA, the total quiescent current of the OTA is 410 nA, ensuring very low power consumption.

2.4. Small-Signal Analysis

Figure 4 presents the small-signal equivalent schematic of OTA, with $C_1$, $C_2$ and $C_3$ serving as the compensating capacitors. The blue shaded area represents the feedback path of the Class-AB output stage control circuit. $R_{O1}$, $C_{O1}$, $R_{O2}$, and $C_{O2}$ denote the output resistance and capacitor of the first and second stages of the OTA, respectively. $R_L$ and $C_L$ represent the load resistance and capacitor.

To calculate the transfer function of the OTA, the following premises should first be established: The $C_L$ and the compensation capacitors are much larger than the $C_{O1}$ and $C_{O2}$. In the circuit design, the output stage is sized significantly larger, implying $g_{m3}$ ≫ $g_{m2}$. Based on these conditions, we can simplify the formula for the amplifier’s transfer function to:

$$H\left(s\right)={\displaystyle \frac{g_{mb2}{g}_{m17}\left(g_{m25}+g_{m26}\right)R_{O1}{R}_{O2}{R}_L}{\left[1+s{C}_1{g}_{m17}\left(g_{m25}+g_{m26}\right)R_{O1}{R}_{O2}{R}_L\right]\left[1+s\frac{\left(C_2+C_3\right)}{g_{m17}}+s^2\frac{C_L\left(C_2+C_3\right)}{g_{m17}\left(g_{m25}+g_{m26}\right)}\right]}}$$

(7)

According to (7), the amplifier has three poles, which are:

$$p_1=p_{-3dB}=-{\displaystyle \frac{1}{C_1{g}_{m17}\left(g_{m25}+g_{m26}\right)R_{O1}{R}_{O2}{R}_L}}$$

(8)

$$p_{2,3}=-{\displaystyle \frac{\left(g_{m25}+g_{m26}\right)}{2C_L}}\pm j{\displaystyle \frac{\left(g_{m25}+g_{m26}\right)}{2C_L}}$$

(9)

$p_1$ is the dominant pole, while $p_2$ and $p_3$ are the two sub-dominant poles. From (8) and (9), it can be observed that the two sub-dominant poles of the amplifier are located far away from the dominant pole. The Miller capacitor shifts them outside the bandwidth, ensuring the stability of the system. The DC gain of the OTA can be derived as:

$$A_{DC}=g_{mb2}{g}_{m17}\left(g_{m25}+g_{m26}\right)R_{O1}{R}_{O2}{R}_L$$

(10)

2.5. Large-Signal Analysis

Since the input transistors M1 and M2 are bulk-driven MOS transistors, which are depletion-type devices, M1 and M2 are in a continuously conducting state. Moreover, the relationship between the current and the input voltage is opposite to that of gate-driven transistors. That is, the larger the input voltage, the greater the current flowing through them.Assuming a positive step signal is applied to VIN+, its charging process is shown in Figure 5.

When $V_{in+}$ > $V_{in-}$, the current $I_{D2}$ flowing through M2 is greater than the current $I_{D1}$ flowing through M1. At this time, capacitor $C_1$ is charged, and the slew rate limit of the first stage is:

$$S{R}_1+={\displaystyle \frac{{\left(I_{D2}-I_{D1}\right)}_{max}}{C_1}}$$

(11)

Since the current of M6 increases, the output voltage $V_{out1}$ of the first stage drops. In the extreme case, M17 is turned off, and simultaneously M18, M19, and M20 are all turned off accordingly. Therefore, the output current $I_{out2}$ of the second stage is determined by $I_{D21}$ and $I_{D22}$. The two compensation capacitors $C_2$ and $C_3$ discharge to M21 and M22 respectively. Thus, the slew rate limit of the second stage is:

$$S{R}_2+={\displaystyle \frac{I_{D19,20}}{C_{2,3}}}$$

(12)

During the decrease of $V_{out1}$, $V_{out2a}$ and $V_{out2b}$ decrease simultaneously. At this time, the current flowing through the output transistor M25 increases, and the current flowing through M26 decreases. The output current charges $C_1$, $C_2$, $C_3$, and $C_L$ simultaneously. In the extreme case, M26 will be turned off, and the slew rate limit of the third stage is:

$$S{R}_3+={\displaystyle \frac{{\left(I_{D23}-I_{D24}\right)}_{max}}{C_1+C_2+C_3+C_L}}$$

(13)

The positive slew rate of the OTA is:

$$SR+={\left\{S{R}_1+,S{R}_2+,S{R}_3+\right\}}_{min}$$

(14)

Assume that a negative step signal is applied to VIN+. The discharging process is shown in the Figure 6 as follows:

When $V_{in+}$ < $V_{in-}$, the current $I_{D2}$ flowing through M2 is less than the current $I_{D1}$ flowing through M1. At this time, capacitor $C_1$ is charged, and the slew rate limit of the first stage is:

$$S{R}_1-={\displaystyle \frac{{\left(I_{D1}-I_{D2}\right)}_{max}}{C_1}}$$

(15)

Since the current of M6 decreases, the output voltage $V_{out1}$ of the first stage increases by $\Delta$V. To characterize the subthreshold conduction behavior of M17 (a bulk-driven MOS transistor operating in the subthreshold region), we introduce the subthreshold slope factor $\zeta$ (dimensionless) — a parameter accounting for non-ideal effects in subthreshold current. $\zeta$ is defined as $\zeta =1+{\displaystyle \frac{C_{BS}}{C_{OX}}}$, where $C_{BS}$ denotes the bulk-source junction capacitance of the MOS transistor, and $C_{OX}$ denotes the gate-oxide capacitance per unit area. For the SMIC 0.18 $\mathsf{\mu }$m CMOS process used in this design, the typical value of $\zeta$ for bulk-driven PMOS transistors (e.g., M17) is 1.2–1.3, consistent with process model data and industry-reported characteristics of subthreshold bulk-driven devices. A current will be generated through M17:

$$I_{D17}={\left({\displaystyle \frac{W}{L}}\right)}_{17}{I}_{D0}exp\left({\displaystyle \frac{\Delta V}{\zeta (kT/q)}}\right)$$

(16)

The current $I_{D17}$ is replicated to $I_{D19}$ and $I_{D20}$ through the current mirror. The two output currents $I_{out2}$ charge $C_2$ and $C_3$ respectively. So, the slew rate limit of the second stage is:

$$S{R}_2-={\displaystyle \frac{{\left(\frac{W}{L}\right)}_{15}{I}_{D0}exp\left(\frac{\Delta V}{\zeta (kT/q)}\right)-I_{D19,20}}{C_{2,3}}}$$

(17)

During the rise of $V_{out1}$, $V_{out2a}$ and $V_{out2b}$ rise simultaneously. At this time, the current flowing through the output transistor M26 increases, and the current flowing through M25 decreases. Capacitors $C_1$, $C_2$, $C_3$, and $C_L$ discharge simultaneously. In the extreme case, M25 will be turned off, and the slew rate limit of the third stage is:

$$S{R}_3-={\displaystyle \frac{{\left(I_{D24}-I_{D23}\right)}_{max}}{C_1+C_2+C_3+C_L}}$$

(18)

The negative slew rate of the OTA is:

$$SR-={\left\{S{R}_1-,S{R}_2-,S{R}_3-\right\}}_{min}$$

(19)

3. Simulation and Experimental Results

3.1. Simulation Results

The OTA was designed using a standard SMIC 0.18 $\mathsf{\mu }$m CMOS technology. Some results of preliminary simulations are discussed in this section.

Table 1. W/L of all transistors.

MOSFET	W/L($\mathsf{\mu }$m/$\mathsf{\mu }$m)	MOSFET	W/L($\mathsf{\mu }$m/$\mathsf{\mu }$m)
M0, M3, M4, M9, M10	0.3/1	M12, M14, M15	4/1
M1, M2, M18, M19, M20	0.5/1	M13, M16, M21, M22, M24	3/1
M5, M6	3/0.9	M17	0.7/1
M7, M8	1.8/1	M23, M25	0.8/1
M11	5/1	M26	5/1

shows the W/L ratios of all transistors. In addition, the capacitance value of $C_1$ is 40.69 fF, while the capacitance values of $C_2$ and $C_3$ are both 5.17 fF. In Figure 3, the bias current $I_B$ is 10 nA.

First, the rail-to-rail input and output performance of the amplifier is verified through simulation. Figure 7a shows the simulation results of the input common-mode voltage of the amplifier under the TT process corner and at room temperature. The blue curve represents the relationship between the output voltage and the input voltage, and the orange curve represents the slope of the input-output curve. It can be concluded that the input common-mode voltage range of the amplifier is from 2.25 mV to 298.5 mV, which can meet the rail-to-rail input performance under the TT process corner and at room temperature. Figure 7b shows the simulation results of the output voltage swing under the TT process corner, which is from 4.27 mV to 299.7 mV, basically meeting the requirements of the rail-to-rail output range.

The AC frequency characteristics of the OTA, including the amplitude-frequency characteristic and the phase-frequency characteristic, are one of the most basic parameters of the amplifier. The simulation results of these characteristics under the TT process corner are shown in Figure 8. For a common-mode input voltage ($V_{\mathrm{cm}}$) of 150 mV, the DC gain of the amplifier is 63.07 dB, the phase margin is 61.5°, and the unity-gain bandwidth product is 37.06 kHz. The performance varies as $V_{\mathrm{cm}}$ changes. When $V_{\mathrm{cm}}$ = 0 V, the DC gain is 47.17 dB, the phase margin is 55.73°, and the unity-gain bandwidth product is 27.25 kHz. Furthermore, for $V_{\mathrm{cm}}$ = 300 mV, the DC gain becomes 36.70 dB, with a phase margin of 49.39° and a unity-gain bandwidth product of 22.34 kHz.

The common-mode rejection ratio (CMRR) reflects the amplifier’s ability to amplify differential-mode signals and suppress common-mode interference signals. The simulation results are shown in Figure 9a, and the CMRR is 69.89 dB. The power-supply rejection ratio (PSRR) reflects the degree to which the output voltage is affected by the change in the power-supply voltage. The simulation results are shown in Figure 9b, and the PSRR is 69.89 dB. The PSRR of the proposed amplifier reflects a deliberate design trade-off, prioritizing ultra-low-power consumption and a competitive GBW product. To achieve these design goals, the simplified intermediate stage, optimized for low power, omits the cascode load structure (cf. [24]), which typically enhances power-supply noise suppression. Additionally, the Class-AB output stage employs a minimal 10 nA bias current to reduce static power, thereby influencing the circuit’s ability to reject power-supply fluctuations.

The settling time is an important parameter for measuring the small-signal transient response of the amplifier. As can be seen from Figure 10a, the rising settling time ST+ is 36.1 $\mathsf{\mu }$s, and the falling settling time ST- is 36.36 $\mathsf{\mu }$s. When the input signal is a square wave with a small peak-to-peak value, the output signal of the amplifier is normal under the typical process corner. The slew rate is used to measure the large-signal transient performance of the amplifier, and its simulation results are shown in Figure 10b.

Simulation result for the noise performance is shown in Figure 11. Note that the thermal noise at Vcm = 150 mV (10 KHz) is 872 $\mathrm{nV}/\sqrt{\mathrm{Hz}}$. This performance supports the suitability of this OTA for low-noise analog front-end applications such as biomedical signal processing.

At the end of this section,

Table 2. Main Performance Parameters of the Proposed Amplifier Across Process Corners and Temperature Range.

	TT			FF			SS
Parameter	−25 °C	−27 °C	−50 °C	−25 °C	−27 °C	−50 °C	−25 °C	−27 °C	−50 °C
ICMR (mV)	5.45–299.7	2.25–298.5	21.4–271.3	10.2–299.7	6.9–250	10.88–295.3	19.6–299.7	10–289.8	10.03–287.1
Swing (mV)	2.65–272.4	4.27–299.7	70.73–291.6	1.41–294.15	3.56–296.25	4.51–296.7	15.42–296.4	5.18–296.7	13.52–296.7
DC gain (dB)	69.32	63.07	45.99	32.98	28.38	25.8	69.32	67.13	66.19
PM (°)	57.2	61.5	71.41	48.13	80.3	65.2	42.18	47.42	54.64
GBW (kHz)	48.46	43.91	20.99	7.62	9.95	8.2	35.07	36.37	38.64
CMRR (dB)	75.01	69.89	26.35	45.72	41.47	42.25	50.36	52.79	65.74
PSRR (dB)	30.12	57.34	15.03	20.96	7.01	15.1	19.96	28.11	20.82
ST ($\mathsf{\mu }$s)	42.95/47.87	36.1/36.36	54.44/53.73	93.54/115.24	96.72/112	90.29/110	45.16/40.28	38.25/38.05	40.36/39.31
SR (V/ms)	20.89/−25.95	18.22/−20.11	11.42/−11.09	2.69/−2.6	4.65/−4.9	21.88/−24.93	25.16/−13.78	21.54/−14.92	16.58/−14.63

presents detailed simulation results across TT, FF, and SS corners under multiple temperatures. The OTA demonstrates strong robustness to PVT variations. The DC gain remains above 45 dB in all cases, with a typical value of 63.07 dB at TT/27 °C. Even under the extreme FF/50 °C condition, the gain degradation to 25.8 dB is tolerable due to reduced output impedance and transconductance, as expected in fast corners. Importantly, the phase margin maintains stability across most corners, ranging from 47.42° to 80.3°, except for a marginal case of −9.87° under FF/−40 °C, which can be improved with tuning of compensation capacitors.The common-mode input range consistently covers over 98% of the supply voltage range, e.g., 2.25–298.5 mV in TT/27 °C, validating the effectiveness of the bulk-driven input stage. Similarly, the output swing extends near rail-to-rail across all corners, indicating successful Class-AB output design. Notably, the OTA maintains functional slew rate even in SS/50 °C (16.58/−14.63 V/ms), while reaching up to 61.69 V/ms in FF/−40 °C. This wide SR variation aligns with bias current scaling under temperature and process extremes. The CMRR consistently exceeds 40 dB across corners, with a peak of 69.89 dB in TT/27 °C, ensuring strong differential-mode selectivity. PSRR, though lower due to 0.3V VDD limitations, achieves a maximum of 57.34 dB, and remains within acceptable bounds for low-voltage OTA designs. These results together affirm the circuits resilience and performance stability under realistic environmental variations.

3.2. Experimental Results

Based on the SMIC 0.18 $\mathsf{\mu }$m process, this paper completed the chip tape-out, and the final chip layout and micrograph are shown in the Figure 12.

When measuring the output voltage swing, the input signal was set as a sinusoidal wave with a peak-to-peak value of 300 m$V_{pp}$ and a frequency of 1 kHz. As shown in Figure 13, the output voltage swing of the amplifier reaches 290.5 mV, meeting the rail-to-rail requirement.

The GBW measurement setup is shown in Figure 14, which is used to verify the theoretical results. The proposed OTA is configured as unity-gain inverting amplifier and the feedback coefficient of this closed loop is 0.75. A Keysight EDUX1002G digital storage oscilloscope is used to supply the input AC signal and capture the input and output. In this measurement circuit. The measured closed-loop AC response of EFC-OTA is shown in Figure 15. It is clear that the 3 dB bandwidth of this closed loop is 25.12 kHz. Hence the GBW of EFC-OTA is 37.68 kHz, which approximately agrees with the simulation result of 37.06 kHz.

The Figure 16 and Figure 17 respectively show the large-signal and small-signal transient responses. When measuring the large-signal transient response and slew rate of the amplifier, a 250 m$V_{pp}$, 1 kHz square wave signal was used as the input. The measured rising slew rate SR+ is 19.4 V/ms, and the falling slew rate SR− is 24.3 V/ms, with no obvious oscillation in the signal. A 50 m$V_{pp}$, 1 kHz square wave signal was used to measure the small-signal transient response and settling time, resulting in a rising settling time ST+ of 36 $\mathsf{\mu }$s and a falling settling time ST− of 32.4 $\mathsf{\mu }$s. Additionally, there is slight overshoot in the small-signal transient response.

Figure 18 shows the Monte Carlo simulation results for the OTA. The results indicate that key metrics such as DC gain and GBW exhibit a reasonable distribution, ensuring that the OTA’s performance remains relatively consistent under process variations.

As shown in

Table 3. Performance comparison with existing low-voltage and low-power OTAs.

Ref.	[28]	[29]	[22]	[27]	[23]	[24]	[26]	This Work
Year	2018	2020	2021	2021	2022	2023	2024	$\mathbf{2025}$
Tech. (nm)	180	180	180	130	130	130	65	$\mathbf{180}$
Area (${\mathrm{mm}}^2\times {10}^{-3}$)	8.2	8.5	19	3.6	2.35	2.34	52	$\mathbf{13.77}$
Supply Voltage (V)	0.3	0.3	0.5	0.3	0.3	0.3	0.35	$\mathbf{0.3}$
Power (nW)	15.4	12.6	45.5	73	33.73	33.73	490	$\mathbf{123}$
CL (pF)	20	30	15	40	250	35	300	$\mathbf{60}$
DC gain (dB)	65.8	64.7	78	40.8	41.28	86.83	55	$\mathbf{63.07}$
PM (deg)	61	52	59	51.93	58.27	58.27	65	$\mathbf{61.5}$
GBW (kHz)	2.78	2.96	7.5	18.65	7.95	10.32	15.4	$\mathbf{37.68}$
CMRR (dB)	72	110	113.8	67.49	35.28	57.8	58	$\mathbf{69.89}$
PSRR (dB)	62	56	84.4	45	74.41	46.59	26.5	$\mathbf{57.34}$
SR (V/ms)	7.12	4.15	8.6	21.6	1.25	3.74	14	$\mathbf{21.85}$
FoMS 1	3.61	7.047	2.47	10.2	16.563	10.7	9.43	$\mathbf{12.25}$
FoML 2	9.25	9.88	2.84	11.82	2.604	3.88	8.57	$\mathbf{10.66}$

¹ $Fo{M}_S={\displaystyle \frac{GBW\times C_L}{\mathrm{power}}}$; ² $Fo{M}_L={\displaystyle \frac{SR\times C_L}{\mathrm{power}}}$.

, the proposed design is benchmarked against several state-of-the-art ultra-low voltage OTAs published from 2018 to 2024. Despite being implemented in the mature 180 nm process, this work achieves highly competitive performance.The proposed OTA consumes only 123 nW with a 60 pF load, representing a balanced trade-off between power and capacitive driving capability. This is significantly lower than many designs such as [22,26], showing superior current efficiency. The measured GBW of 37.68 kHz is the highest among all 0.3 V OTAs in the comparison, and the SR of 21.85 V/ms is competitive even against designs operating at higher power (e.g., [27] at 21.6 V/ms with 73 nW). These improvements are attributed to the Class-AB output stage with enhanced drive capability and minimal static bias current. The OTA achieves a DC gain of 63.07 dB, comparable to [28,29], and an exceptional CMRR of 69.89 dB, which surpasses many designs using advanced process nodes or more complex topologies. The small-signal figure of merit FoM_S reaches 12.25 MHz·pF/μW, and the large-signal FoM_L reaches 10.66 V/μs·pF/μW, both outperforming most other works. These FoMs confirm that the proposed design offers an optimal balance of speed, power, and load-driving capability.

A Monte Carlo simulation (500 iterations) was conducted to assess the proposed amplifier’s process variation robustness: key metrics showed tight, stable distributions—with a mean DC gain of 63.02 dB, GBW of 37.12 kHz. Results are showed in Figure 18. All parameters clustered around their nominal values, confirming the amplifier’s consistent performance across process fluctuations, which suits its application in low-voltage wearable health monitoring systems.

4. Conclusions

This paper presents a high-efficiency, ultra-low-voltage OTA that operates at 0.3 V and features rail-to-rail input/output capabilities with enhanced GBW and SR. The design employs a bulk-driven technique in the input stage to extend the common-mode input range under subthreshold conditions and overcome the threshold voltage limitations of conventional gate-driven MOS transistors. A simplified intermediate stage is implemented to ensure low-power operation while preserving normal transistor functionality at ultra-low-voltages. Additionally, a modified Class-AB control loop in the output stage stabilizes the quiescent current and minimizes power consumption, thereby achieving efficient rail-to-rail output. Fabricated using SMIC 0.18 $\mathsf{\mu }$m technology, the OTA exhibits outstanding performance: under a 0.3 V supply and a 60 pF load, it consumes only 123 nW, attaining nanowatt-level power efficiency. Key measured results include a DC gain of 63.07 dB, a phase margin of 61.5°, an experimental GBW of 37.68 kHz, and a slew rate of 21.85 V/ms. The amplifier also demonstrates superior figures of merit (FoM), with a small-signal FoM_S of 12.25 MHz·pF/$\mathsf{\mu }$W and a large-signal FoM_L of 10.66 V/$\mathsf{\mu }$s·pF/$\mathsf{\mu }$W, thereby outperforming many state-of-the-art low-voltage OTAs in terms of efficiency and speed. Comparative analysis with recent works underscores the design’s balanced trade-offs of low power, wide bandwidth, and high slew rate, making it highly suitable for energy-constrained applications such as portable electronics, IoT sensors, and biomedical devices. Although the PSRR is relatively modest due to the ultra-low-voltage limitations, the OTA’s overall performance establishes a new benchmark for high-efficiency, rail-to-rail operation in sub-0.5 V regimes. Future work may focus on further enhancements in PSRR and on integrating the design with advanced low-power circuits to broaden its applicability in ultra-low-voltage systems.