A 0.9 V, Ultra-Low-Power OTA with Low NEF and High CMRR for Batteryless Biomedical Front-Ends

Abstract

This paper presents a new operational transconductance amplifier (OTA) design for batteryless biomedical front-ends. The proposed OTA operates in the subthreshold region and utilizes self-cascode devices to achieve ultra-low power, low noise, and a high common-mode rejection ratio ($CMRR$). Post-layout simulations in Cadence, using 45 nm CMOS technology with 0.9 V supply voltage, show a power consumption of 49.3 nW, a $CMRR$ of 144.9 dB, an input-referred noise of 4.51 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$ integrated over 0.5–208 Hz, and a noise efficiency factor of 1.023 with a core silicon area of 0.00138 mm². Using the proposed OTA, we implemented a 10-channel neural recording amplifier for Local Field Potentials (LFPs) based on a capacitively coupled, capacitive-feedback (CC-CF) topology with a body-driven pseudo-resistor high-pass path. The system achieves a total $CMRR$ ≥ 70 dB and an estimated power of 494.2 nW for 10 channels. Compared with prior art, the proposed OTA offers competitive noise efficiency and common-mode rejection at lower power, making it a viable building block for batteryless neural and biomedical sensing front-ends.

1. Introduction

Disease diagnosis and treatment have long been aided by technology. Neural signals must be recorded to diagnose brain diseases such as Parkinson’s disease, stroke, and tumors. These brain signals are divided into four categories: action potentials (APs), local field potentials (LFPs), electroencephalography (EEG), and electrocorticography (ECoG). Except for AP (1–7 kHz), all brain signals fall within the 200 Hz frequency range. EEG, ECoG, and LFP are mainly used to examine brain activity and diseases. For recording brain signals, which are made up of $\alpha ,\beta ,\gamma ,\theta$, and $\delta$ waves, EEG is a standard non-invasive method [1]. However, ECG has a low signal-to-noise ratio (SNR) and spatial resolution [2,3]. The phrase brain–machine interface (BMI) or brain–computer interface (BCI) refers to a treatment for paralyzed individuals that creates a direct communication channel between the brain and an external device, such as a computer or robotic limb. Electrodes are usually inserted directly into the brain (invasive) or put on the scalp (non-invasive) to record APs for BMIs. The signal is digitized and sent to the data-processing block after being amplified and noise-reduced by the neural amplifiers in the data-collecting block. To find patterns linked to specific actions or intents, raw brain impulses are processed and examined. Commands are generated from these retrieved signals. These commands are then utilized to operate various assistive technologies, stimulate muscles, or activate a robotic limb [4]. Figure 1 shows a generic implementation of the EEG/ECoG/LFP signal collection setup and BMI. A BMI chip is successfully implanted by the Neuralink company in a quadriplegic human patient [5].

In addition to restoring function, diagnosing diseases and assisting devices, the use of neural signals has expanded to areas like communication (translating brain activity into speech or text), neuro-prosthetics, gaming, education, research, and security. The systems that perform these tasks come in wearable or implantable form. Hence, the requirements for next-generation neural amplifiers are very stringent in a low supply voltage and power setting. The ultra-low-power and noise neural amplifier will help in the realization of a battery-less wearable or implantable chip. The practical realization of these systems requires additional energy-harvesting circuits. With a maximum power transfer efficiency of 15%, currently existing implantable radio frequency (RF) energy-harvester devices may produce power ranging from 25 $\mathsf{\mu }$W to 1 W. The typical power needs of different biomedical devices vary from 3.65 nW to 294 mW [6].

To record the brain signals, usually multi-channel systems are used. These channels take input via electrodes (dry or wet). For prolonged recording, dry electrodes are preferred [7]. In [8], an electrical model for a silicon micro-electrode (dry) and tissue interface is developed using the Randles equivalent circuit method [9]. This model contains a parallel network (Rp and Cp) in series with a resistor (Rs). In vivo measurements give out the parameter values as Rs = 12.3 k$\Omega$, Rp = 17 G$\Omega$ and Cp = 205 nF. At 0.5 Hz of signal frequency, the total impedance of the interface is 1.55 M$\Omega$. In order to have a voltage drop of <1% across the electrode, the input impedance of the amplifier must be >153.45 M$\Omega$. Each channel, in its simplest form, is comprised of a low-noise amplifier (LNA). A neural amplifier is a specialized LNA circuit designed to detect and amplify tiny electrical signals generated by neurons in the brain or nervous system. These signals, often in the microvolt range (10 $\mathsf{\mu }$–5 mV) and mostly in sub 200 Hz (0.5–200 Hz) frequency, are incredibly weak and easily drowned out by noise [1,10,11,12,13]. The input-referred noise value of most neural amplifiers that are able to extract in vivo action potentials is less than 3–7 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$ [14,15,16]. Hence, amplifiers must be ultra-sensitive, low-noise, and power-efficient to be effective. The main features of neural amplifiers include high-pass filtering, low-pass filtering, low input-referred noise, necessary gain, low power, and compact size [17].

Neural amplifiers can be classified into the following topologies: open-loop, capacitive feedback, capacitive T-feedback, active feedback, chopper amplifier and adaptive. Open-loop designs often use an instrumentation amplifier that offers high gain and low noise. They are typically optimized for either ultra-low power or ultra-low noise but rarely both at once. Performance inconsistency due to process variability makes them an unpopular choice for implantable devices. The capacitive feedback has been widely adopted in neural amplifier circuits over the last decade due to its scalability and tunable bandwidth. This topology offers low-pass filtering and gain control in a compact design and can be optimized to provide low power. The capacitive T-feedback offers a better matching of feedback capacitors and improves the $CMRR$. Local field potential signals exist in the low-frequency range, which overlaps with flicker (1/f) noise. Chopper amplifiers shift the input signal to a higher frequency to suppress 1/f noise, enhancing signal clarity. Complex design, low input impedance and ripple artifact introduction are some demerits of this architecture. In an active feedback topology, a portion of the signal is filtered and looped back to cancel specific components, especially low-frequency signals. Enhanced stability for long-term recording, reduced capacitor size compared to capacitive feedback and elimination of DC drift are some key benefits of this architecture. Adaptive topological circuits are designed with variable performance modes to adjust power usage based on functional demands. Techniques like changing topology, tuning slew rate, and phase margin help reduce energy usage [17,18,19,20,21].

To meet the specifications of the neural amplifier, different types of OTAs are used. The two-stage Op-Amp (Miller OTA), the current mirror OTA, the telescopic cascode, the folded cascode, and the differential self-biased OTA are among the popular architectures [22,23,24,25]. These architectures, providing low $CMRR$, are capable of producing decent-quality signals at high power levels. Novel architectures are proposed from time to time to improve performance parameters. In [26], a modified split push–pull balanced (SPPB) OTA is employed at 180 nm, resulting in low power (1.69 $\mathsf{\mu }$W), wide bandwidth, high output swing and an impressive NEF of 2.3. The authors of the article [27] proposed an inverter-based OTA, which resulted in a high mid-band gain of 52 dB, low input-referred noise of 4.13 $\mathsf{\mu }$V and a power consumption of 2.8 $\mathsf{\mu }$W with a poor $CMRR$ of 50 dB. Later, a CMFB circuit is proposed to improve the $CMRR$. The design achieves an NEF of 3.19. An inverter-based OTA is proposed in [28]. In [29], an inverter stacking-based OTA is proposed, and it significantly reduced the power to 0.25 $\mathsf{\mu }$W with 5.5 $\mathsf{\mu }$V noise and an excellent NEF of 1.07. The offset voltage reduction is achieved through splitting the capacitors of the capacitive feedback topology. However, vertical stacking limited the output swing, and the design manages a gain of only 25 dB, which may limit its use. The authors of [30] proposed two novel self-cascode current mirror (SCCM) architectures, which show improvements in certain parameters over the conventional current-mirror architecture. At the expense of a 2.54 $\mathsf{\mu }$W power, the SCCM-II architecture achieves a $CMRR$ of 122.1 dB, a PSRR of 72.57 dB and a gain of 39.79 dB with an excellent NEF of 3.87 at ±0.9 V supply. However, the architecture has a limited dynamic range of 41.2 dB and an input impedance of 432 M$\Omega$ at 100 Hz. This can limit the output swing. Apart from signal attenuation and signal distortion, low input impedance can make the amplifier more susceptible to noise from the source or nearby circuits especially in sensitive applications like neural recording. In [31], the authors proposed an OTA which uses a composite transistor structure as an active load and a gate-controlled bulk-driven (GCBD) input stage structure as input. The composite transistor provides a high impedance by increasing the effective channel length and thus reduces the chip area. The GCBD input stage provides additional gain over the conventional input stage. The design leads to a lower input-referred noise of 2.6 $\mathsf{\mu }$V with a 49.9 dB gain and 2.27 NEF at the cost of 11.5 $\mathsf{\mu }$W power consumption. However, the final neural recording amplifier achieves a bandwidth of 5.3 Hz–8.6 kHz, which may fail to capture $\delta$ (0.5–4 Hz) and $\theta$ (4–8 Hz) waves but is capable of capturing APs. Dynamic Threshold MOSFET (DTMOS) is utilized in [32] in order to lower the power of the OTA. DTMOS relies on connecting the gate to the bulk (substrate), which dynamically adjusts the threshold voltage. This configuration complicates layout and isolation, especially in standard CMOS processes where bulk terminals are shared. It can lead to parasitic latch-up or leakage paths if not carefully managed. Furthermore, this configuration limits the dynamic range. Architectures such as the multiple-input bulk-driven OTA offer low power consumption but poor noise performance, and the current-reused OTA design offers a low IRN but higher power consumption [33,34]. In [35], an improved recycling telescopic cascode (RTC) OTA is proposed, where the recycling stage is added to reduce power consumption while increasing output resistance. A cross-coupled positive feedback is utilized to increase the DC gain of the amplifier. Large devices are exploited to reduce IRN and power. However, the design exhibits comparatively low input impedance and $CMRR$, which may result in noise injection from dry electrodes that act as an antenna and absorb the power-line-interference (PLI) [36]. A novel differential-like OTA is proposed in [37]. Two asymmetric branches make up the differential-like OTA. Compared to the non-inverting branch used as a reference, the inverting branch utilized for multi-channel inputs has more inverters in parallel. To effectively lower the $NEF$ and crosstalk in input channels, the differential-like OTA is developed with two virtual rails with extremely low impedance, which resulted in an excellent $NEF$ of 0.84 for 675.2 nW of power per channel at 1.1–1.8 V supply. The low $CMRR$ could potentially distort the neural signals by not rejecting the already superimposed PLI at the dry electrodes. The works in [38,39] proposed a highly linear digitally tunable OTA. High linearity is achieved by using a double differential pair, source degeneration and adaptive biasing. A current division network (CDN) is utilized to make the OTA digitally tunable. The circuit is designed and tested in 90 nm technology, where it demonstrates an excellent HD3 value of −60 dB for 0.5 V differential inputs. The OTA consumes between 140 and 669 $\mathsf{\mu }$W of power, and the work is aimed at developing biomedical and wireless systems. However, for ultra-low-power biomedical systems, this might not be suitable. In [40], a switchable gain and order filter for a multi-standard receiver is designed using the same OTA. An amplifier that may be used for multi-modal sensing can be designed using such tuning techniques.

The earlier works cited here did not concentrate on wearable or battery-less devices, which need extremely low power and noise levels at a smaller supply. The goal of the work presented here is to propose a circuit for wearable or battery-free devices. A 10-channel neural recording amplifier is designed in this study with the capacitively coupled capacitive feedback (CC-CF) architecture [18] being used in each neural amplifier channel. A novel OTA that is ultra-low power and low noise is suggested in order to satisfy the demands of next-generation wearable or battery-less devices. To increase the output swing and $CMRR$, a fully differential design is selected instead of a single-ended one. The OTA utilizes composite transistors (self-cascode) as input stages and current mirrors in the subthreshold region. The current is recycled by an additional input path for each input stage. The resistors of the neural amplifier are replaced by a bulk-driven pseudo-resistor (BDPR). The whole system is designed using a 0.9 V supply in a 45 nm standard process design kit (PDK). Performed simulations, generated layout, process corner analysis and Monte Carlo analysis are used to demonstrate the validation of the design. The proposed OTA and the neural amplifier are compared with the state-of-the-art designs. One figure-of-merit (FoM) that is widely used in comparing LNAs is NEF, which establishes a trade-off between noise and power, and this is given by Equation (1) [41].

$$NEF=V_{ni,rms}\sqrt{{\displaystyle \frac{2I_{tot}}{\pi U_{T}4kTBW}}}$$

(1)

where $V_{ni,rms}$ indicates the input-referred root mean square noise voltage, $U_T$ is the thermal voltage, $BW$ is the bandwidth, T is the temperature, k is the Boltzmann’s constant, and $I_{tot}$ is the total current.

Four parts make up the remainder of the paper. Section 2 provides a detailed description of the proposed circuit. Insightful examination of the simulation findings is presented in Section 3. The concluding remarks are provided in Section 4.

2. Proposed Design

This section explores the design details of the neural recording system and explains the relevant mathematical analysis. The description of the proposed OTA, neural amplifier and the 10-channel neural recording system is presented in sequence.

2.1. Operational Transconductance Amplifier

OTAs are important in signal-sensing applications, serving as the foundational building blocks for various analog and mixed-signal systems. This paper presents a modified OTA architecture shown in Figure 2 that incorporates innovative design improvements to address common trade-offs. The main characteristics of the suggested design include the use of composite transistors ($M_{1,2}$ and $M_{7,8}$) as the input stage, which raises the gain by raising the output impedance, in addition to being appropriate for low-voltage operation while guaranteeing a strong output swing. Again, compared to its DC equivalent transistor of uniform width, a self-cascode current mirror (SCCM), which serves as the current mirror ($M_{1,2}$ and $M_{7,8}$) of the proposed circuit, has two key advantages: a higher cutoff frequency and considerable area savings [42]. Thus, it is a valuable technique to increase the BW of the circuit. The degenerated MOSFETs improve the performance of amplifiers by increasing the output resistance, improving the stability and linearity [43]. Furthermore, the cascode devices contribute negligible noise to the OTA. A cross-coupled positive feedback is exploited to enhance the gain further. To modulate the current, $I_{ref}$, a pseudo-resistor utilizing the composite transistor structure is used. The proposed architecture leverages these advantages while addressing the standard limitation of reduced transconductance in degeneration amplifiers. Using the composite transistor as an input pair, the design achieves an increase in transconductance without compromising the inherent benefits of degeneration. This results in an OTA with superior performance metrics, making it highly suitable for modern signal processing applications.

The self-cascode or composite transistor technique for the input pair employs two transistors of the same type, arranged in a cascoded configuration, as shown in Figure 3. In this configuration, the drain of $M_1$ MOSFET is connected to the source of $M_2$ MOSFET, structuring the self-cascode structure.

The total output resistance $R_{out,SC}$ and the total transconductance $g_{m,SC}$ of the self-cascode input pair are defined by Equations (2) and (3) [42].

$$R_{out,SC}=2r_{O2}$$

(2)

$$g_{m,SC}=g_{m2}/2$$

(3)

Here, $g_{m1}$ and $g_{m2}$ are the transconductances of the $M_1$ and $M_2$ MOSFETs, respectively. $r_{O1}$ and $r_{O2}$ represent their output resistances. The selection of a pMOS with a larger area minimizes the noise in the amplifier [44]. In this work, the input pair is designed with a larger W/L ratio, where the W/L of $M_1$ is kept the same as that of $M_2$. This improves noise performance while maintaining high linearity and transconductance [45].

According to [30,46], the self-cascode current mirror (SCCM) for the load pair can be designed with a lower $V_{DSAT}$ than a conventional current mirror, allowing for low voltage operation and large output swings with a smaller area. The SCCM’s substantial output resistance improves the common-mode rejection ratio and makes it a better current mirror. Figure 4 shows the small-signal model of the SCCM.

MOSFETs $M_9$, $M_{10}$, $M_{11}$ and $M_{12}$ form the SCCM in one part of the symmetric circuit. For a scaling factor of K:1, the relation between the $I_{in}$ and $I_{out}$ is given by Equation (4).

$$\begin{array}{cc}\hfill & I_{out}=K{I}_{in}\hfill \\ \hfill & K={\displaystyle \frac{{(W/L)}_{9,10}}{{(W/L)}_{11,12}}}\hfill \end{array}$$

(4)

A positive feedback is added to the circuit via a cross-couple mechanism to increase the input impedance and gain of the circuit [47]. With both sides of the OTA completely matched, the simplified small signal model of the proposed OTA is depicted in Figure 5. Consequently, the drain node of the tail current source ($M_{18}$) becomes an AC ground. Assuming equal transconductances for each row, $g_{m1}=g_{m3}=g_{m5}=g_{m7}$, $g_{m2}=g_{m4}=g_{m6}=g_{m8}$, $g_{m9}=g_{m11}=g_{m13}=g_{m15}$ and $g_{m10}=g_{m12}=g_{m14}=g_{m16}$.

Here, $C_1$ consists of $C_{in}$, smaller portions of $C_{gd1,3},C_{gs1,3},C_{gd2,4}$, $C_{gds2,4}$ and any load capacitance $C_L$. $C_2$ consists of $C_{db2}$ and $C_{db9}$. $C_3$ consists of portions of $C_L$, $C_{gd9,11}$, $C_{gs9,11},C_{gd10,12},C_{gs10,12}$ and $C_{db6}$.

The input resistance for the open-loop OTA is given by Equation (5). Assuming no current flows from the input, the inputs are directly connected to the input transistors’ gates, resulting in an infinite input resistance. However, the resistance would be finite in both simulation and post-fabrication due to parasictics and the tiny oxide thickness in advance nodes.

$$R_{in}=\infty$$

(5)

The output resistance of the circuit is given by Equation (6).

$$R_{out}=r_{OC1}\left|\right|r_{OC2}$$

(6)

Here, $r_{OC1}=2r_{O2}=2r_{O8}$ and $r_{OC2}=2r_{O9}=2r_{O15}$.

If the transconductance of the OTA is $G_M$, then the low-frequency gain can be written as Equation (7).

$$A_{V,OTA}=G_M{R}_{out}=K{g}_{meff1}(r_{OC1}\left|\right|r_{OC2})$$

(7)

The poles and zero of the OTA is given by Equations (8)–(10).

$$P_1={\displaystyle \frac{1}{(r_{OC1}+r_{OC2})C_2}}$$

(8)

$$P_2={\displaystyle \frac{1}{(r_{OC1}+r_{OC2}+\frac{1}{g_{meff10}})C_3}}$$

(9)

$$Z=-{\displaystyle \frac{1+r_{OC1}\times r_{OC2}}{r_{OC1}+r_{OC2}+\frac{1}{g_{meff10}}}}$$

(10)

Here, $g_{meff1}$ and $g_{meff10}$ refer to the effective transconductances of the composite transistor (also known as self-cascode) at the input stage and the current mirror, respectively. It was established in Equation (3) that $g_{meff1}=g_{m2}/2$ and $g_{meff10}=g_{m9}/2$.

The major contributors to noise are the $M_{2,4,6,8}$ and $M_{9,11,13,15}$ devices. The cascode devices $M_{1,3,5,7}$ and $M_{10,12,13,16}$ have negligible contributions and are ignored in noise analysis.

The total IRN voltage of an OTA is given by Equation (11).

$$\overline{V_{ni,OTA}^2}\approx (\overline{V_{ni,thermal}^2}+\overline{V_{ni,flicker}^2})$$

(11)

The output thermal noise current of the proposed OTA can be given by Equation (12).

$$\overline{I_{no,thermal}^2}=8kT\gamma {\displaystyle \frac{1}{2}}(g_{m2}+g_{m9}+g_{m6}+g_{m11})$$

(12)

The input thermal noise voltage of the OTA is given by Equation (13).

$$\begin{array}{cc}\hfill \overline{V_{ni,thermal}^2}& ={\displaystyle \frac{\overline{V_{no,thermal}^2}}{A_v^2}}={\displaystyle \frac{\overline{I_{no,thermal}^2}{R}_{out}^2}{A_v^2}}\hfill \\ \hfill & ={\displaystyle \frac{4kT\gamma (g_{m2}+g_{m9}+g_{m6}+g_{m11})}{K^2{g}_{m1}^2}}\hfill \\ \hfill & ={\displaystyle \frac{8kT\gamma }{K^2}}({\displaystyle \frac{1}{g_{m2}}}+{\displaystyle \frac{g_{m9}}{g_{m2}^2}})\hfill \end{array}$$

(13)

where K is the scaling factor for the current mirror, $k=1.38\times {10}^{-23}$ J/K is the Boltzmann constant, $\gamma =2/3$ for long channel transistors, $T=300$ K temperature, and $g_m$ is the transconductance of the relevant transistors.

Again, Equation (14) is devised for the input flicker noise voltage.

$$\overline{V_{ni,flicker}^2}={\displaystyle \frac{2K_f}{f{C}_{OX}}}({\displaystyle \frac{1}{W_2{L}_2}}+{\displaystyle \frac{g_{m9}^2}{g_{m2}^2{W}_9{L}_9}})$$

(14)

where f is frequency in Hz, $C_{OX}$ is the gate-oxide of the MOSFETs, and $K_f$ is the process-dependent parameter and is on the order of ${10}^{-25}$ V²F. The noise analysis reveals that by increasing the $g_{m2}$ and area ($W\times L$) of $M_{2,4,6,8}$ and $M_{9,11,13,15}$ devices, low noise can be achieved. Moreover, the current mirror scaling factor, K, can be another parameter that can be utilized to reduce noise at the expense of more power. However, increasing $g_{m9}$ will increase noise. Thus, the area of $M_{9,11,13,15}$ devices can be made larger by only increasing the length, L.

The −3 dB frequency ${\omega }_{-3\mathrm{dB}}$ and gain-bandwidth product $GBW$ of the circuit can be given by Equations (15) and (16).

$${\omega }_{-3dB}={\displaystyle \frac{1}{R_{out}{C}_L}}$$

(15)

$$GBW={\displaystyle \frac{K{g}_{m2}}{2C_L}}$$

(16)

Both Equations (15) and (16) are load capacitor $C_L$ dominant.

Equations (17) and (18) are used to measure the $CMRR$ and $PSRR$ of the OTA.

$$CMRR=20log{\displaystyle \frac{A_{VD}}{A_{CM}}}$$

(17)

$$PSRR=20log{\displaystyle \frac{A_{VD}}{A_S}}$$

(18)

where $A_{VD}$ is the differential gain of the amplifier, $A_{CM}$ is the common-mode gain and $A_S$ is the gain from the supply.

2.2. Neural Amplifier

The CC-CF band-pass filter (BPF) in [18] is employed as the low-noise amplifier for the neural amplifier and shown in Figure 6. The filter uses the proposed full differential OTA, two capacitors ($C_1$ and $C_2$), and two resistors ($R_A$). $C_1$ and $R_A$ are the feedback elements and are responsible for DC offset rejection while acting as a high-pass filter (HPF). This feedback connection significantly increases linearity and reduces noise. The $C_2$ and the input impedance of the OTA form the low-pass filter (LPF). The transconductance of the NA, $g_{m,NA}$ = $g_{m,OTA}$.

Equations (19)–(22) are the mid-band gain ($A_{V,NA}$), higher cutoff ($f_{-3\mathrm{dB}}$), lower cutoff ($f_L$) and input-referred noise voltage ($\overline{V_{ni,NA}^2}$) of the NA, respectively.

$$A_{v,NA}={\displaystyle \frac{C_2}{C_1}}$$

(19)

$$f_{-3dB}={\displaystyle \frac{g_{m,OTA}}{2\pi A_{V,OTA}{C}_L}}$$

(20)

$$f_L={\displaystyle \frac{1}{2\pi R_A{C}_1}}$$

(21)

$$\overline{V_{ni,NA}^2}={\left({\displaystyle \frac{C_1+C_2+C_{in}}{C_2}}\right)}^2.\overline{V_{ni,OTA}^2}$$

(22)

Here, $C_{in}$ is the input capacitance to the OTA.

A bulk-driven pseudo-resistor (BDPR) composed of pMOS is proposed and used as a variable resistor instead of $R_A$. Figure 7 shows the BDPR when N = 2 (2 devices in series).

For simplicity, both transistors are considered identical, meaning ${(W/L)}_{MR1}$ = ${(W/L)}_{MR2}$, making $g_{m,MR1}=g_{m,MR2}$. The output resistance of the entire pseudo-resistor, $R_{out,BDPR}$, is the output resistance of $MR2$ and is given by Equation (23).

$$R_{out,BDPR}=r_{O,MR2}+(1+g_{m,MR2}{r}_{O,MR2}+g_{mb,MR2}{r}_{O,MR2})r_{O,MR1}$$

(23)

Here, $g_{mb,MR2}$ is the body-effect transconductance of the MOSFET and is related to the main transconductance, $g_{m,MR2}$, by Equation (24).

$$g_{mb,MR2}=\chi g_{m,MR2}$$

(24)

where $\chi$ is the body-effect coefficient, typically ranging from 0.1 to 0.3 [48]. As both the transistors are identical, $r_{O,MR2}=r_{O,MR1}=r_{O,MR}$. The generalized output resistance equation for N = 2 (N devices in series) can be written as in Equation (25).

$$R_{out,BDPR}=2r_{O,MR}+g_{m,MR}{r}_{O,MR}^2(1+\chi )\approx g_{m,MR}{r}_{O,MR}^2(1+\chi )$$

(25)

where $g_{m,MR1}=g_{m,MR2}=g_{m,MR}$. A larger value of resistance can be achieved by increasing N.

2.3. 10-Channel Neural Recording Amplifier

Generally, biosignal recording systems comprise pre-amplifiers, buffers, multiplexers, analog-to-digital converters (ADCs) and a wired or wireless transmitter blocks. The proposed NA is employed to design a 10-channel neural recording amplifier, and the circuit schematic is shown in Figure 8. The scope of this work is limited to the design of the 10-channel neural recording amplifier only, which is highlighted (blue) in Figure 8. For any neural recording system to have a detectable neural signal of at least 5 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}},$ the total common-mode rejection ratio ($TCMRR$) must be at least 70 dB. The $TCMRR$ equation can be given by Equation (26) [13]. Nonetheless, a shared reference input that has an input impedance that is several times lower than that of the corresponding signal inputs is frequently used in the implementation of multi-channel neural amplifiers [14]. For the proposed system, the electrodes create a single-ended input for the NAs by gathering neural signals from the brain. The 10 electrodes are connected to 10 NAs. All of the inverting ($V_{in-}$) inputs are shorted to a common reference point ($V_{REF}$), while the non-inverting ($V_{in+}$) input serves as the signal input point. This lowers each channel’s overall gain to some extent.

$$TCMRR={[{\displaystyle \frac{1}{CMRR}}+{\left({\displaystyle \frac{1+2(Z_{in}/Z_e)+Nϵ}{2(Nϵ-1)}}\right)}^{-1}]}^{-1}$$

(26)

where $Z_{in}$ is the input impedance of the OTA, $Z_e$ is the electrode impedance, N is the number of channels or inputs sharing $V_{REF}$, $ICMRR$ is the intrinsic common-mode rejection ratio of the OTA and $ϵ$ is the mismatch factor for $Z_e$. As for the $TCMRR$, the equation reveals that a higher $Z_{in}/Z_e$ ratio and higher $CMRR$ of the OTA is necessary for higher channel implementation.

3. Simulation Results

The simulations are carried out in Cadence Virtuoso using a standard 45 nm PDK. The findings from the OTA are initially shown and explained in this section, which is followed by the NA and a 10-channel brain signal recording amplifier. Unless otherwise specified, all simulations are run at $T=27$ °C.

3.1. Operational Transconductance Amplifier

The proposed OTA in Figure 2 is designed using the $g_m/I_D$ method [49]. The aspect ratios (W/L) of various devices are given in

Table 1. Aspect ratios and $g_m/I_D$ of the devices used for the OTA.

Devices	W/L	${\mathit{g}}_{\mathit{m}}/{\mathit{I}}_{\mathit{D}}$
M1, M2	40 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	34.6
M3, M7	39.98 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	34.7
M5, M6	40 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	34.7
M4, M8	39.96 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	34.7
M9, M10	10 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m	30.9
M11, M12	9.1 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m	30.9
M13, M14	9.1 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m	30.9
M15, M16	10 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m	30.9
M17	30 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	34.1
M18	90 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	34.1
M19, M20	120 nm/45 nm	24.1

. Device lengths are selected to be longer than the minimum process channel length (45 nm) in order to lessen the channel length modulation effect. For low-power operation, this work presents all devices functioning in the subthreshold region, which is indicated by region 3 in Cadence software (https://www.cadence.com/en_US/home.html).

Figure 9 illustrates the frequency response of the OTA. Figure 9a,b illustrates the pre-layout magnitude responses for single-ended and full differential inputs. The single-ended version maintains a 36.76 dB gain with 67.2° phase margin, while the differential one has 42.78 dB gain with 66.3° phase. The later one demonstrates a higher unity gain bandwidth ($UGBW$) of 158 kHz, whereas the previous one has a lower $UGBW$ of 100 kHz only. It is due to the differential action ($V_{out}=A_V(V_{in+}-V_{in-})$) which gives out a higher gain. The layout edition of differential input shown in Figure 9c demonstrates a similar gain, while the $UGBW$ is 100 kHz. The parasitics from the layout are responsible for reducing it. The obtained gains can amplify a signal of 10 $\mathsf{\mu }$V to 689 $\mathsf{\mu }$V–1.41 mV.

Figure 10a,b present the input impedance of the OTA. Within 1–100 Hz frequency, the impedance varied in the viccinity of 908 to 886 M$\Omega$. A small drop to 817–799 M$\Omega$ is observed when 100 pF as the input pad capacitance is considered. A 10-channel NA is realizable with this input impedance.

Achieving a high $TCMRR$ for the multi-channel NA requires a high $CMRR$, which is achieved by the designed OTA shown in Figure 11. Figure 9d illustrates the common-mode gain. The design achieves a value of 144.9 dB in post-layout $CMRR$ simulation.

The $PSRR$ simulation achieves a high value of 64.6 dB at 100 Hz in the post-layout simulation illustrated in Figure 12b, which is 3 dB more than the pre-layout simulation shown in Figure 12a. Given the nature of power supply noise being small, 64.6 dB is sufficient for rejection.

Figure 13 demonstrates the noise analysis of the OTA. The integrated input-referred noise from 0.5 to 208 Hz is 4.51 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$, and from 0.5 to 1 kHz, it is 8.82 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$. Such a low IRN is attributed to the selection of wider cascoded input pairs and current mirrors, which are designed using pMOS transistors.

Figure 14 reveals the Monte Carlo simulations for 200 samples for gain, $CMRR$ and $PSRR$. A standard deviation of $\sigma$ < 3 dB can be considered insignificant, which is obeserved for the gain and $PSRR$ plots. The lowest $CMRR$ value (120 dB) from the Monte Carlo simulation nevertheless yields a respectable $TCMRR$ of 65.66 dB for N = 10 channels.

Figure 15a displays the pole-zero positions of the designed OTA, demonstrating that there are no right half-plane poles in the design. This demonstrates the stability of the proposed OTA. The total harmonic distortion ($THD$) for varied input signal amplitude levels at different frequencies is shown in Figure 15b. The input signal can be 4.5 mV for signal frequencies ≤ 10 Hz while keeping $THD$ at −40 dB. At a frequency of 260 Hz, an input signal with an amplitude of ≈0.9 mV generates −40 dB $THD$. According to Figure 26a, which displays the $THD$ analysis of a pediatric subject using the CHB-MIT scalp EEG database signal (one channel) [50], the signal amplitude ranges from 12 $\mathsf{\mu }$V to 61 $\mathsf{\mu }$V with a frequency range of 50 Hz to 200 Hz. As a result, this OTA’s $THD$ performance is satisfactory.

Figure 16a reveals an output impedance of 5.18 M$\Omega$. The composite transistor paired with the subthreshold operation of devices ensured a high output swing of 426.2 mV, which is presented in Figure 16b. The fully differential output is also responsible for this high swing. High output swings are a desirable trait in extracting signals.

Figure 17 shows the effect of modulating the $Vbias$ of the OTA, which results in $I_{ref}$ modulation. When the $Vbias$ is varied from −1 to 1 V, the reference current is modulated from 31.5 $\mathsf{\mu }$A to 0.2 nA. The reference current ($I_{ref}$) modulation (1 nA–2 $\mathsf{\mu }$A) changes the gain of the amplifier from 46.86 to 38.71 dB. This modulating feature is particularly desirable for post-fabrication tuning. Simulations reveal further that when the reference current $I_{ref}$ is varied from 1 nA to 1 $\mathsf{\mu }$A, the GBW is varied from 15.51 kHz to 6.25 MHz. For the same $I_{ref}$ variation, the $BW$ ranges from 227.69 Hz to 60.4 kHz.

Figure 18a shows the gain vs. frequency plot when the supply voltage is deviated by ∼$\pm 10\%$. The simulation’s outcome demonstrates that the gain’s deviation is minimal. This demonstrates how reliable the design is. Figure 18b shows that the gain decreases as the temperature rises. The sensitivity to temperature is touted as a demerit when considering applications for neural signal processing. A deviation of <$\pm 10$% in gain (dB) is observed when the temperature is between −40 °C and 80 °C.

Figure 19 illustrates the effect of the load capacitor ($C_L$) and feedback capacitor ($C_2$) on the phase margin of the OTA. As the load on the feedback capacitor increases, the phase margin only improves. To improve the predictability of the OTA behavior, a fixed capacitor at an internal load of 1 pF is incorporated into the layout design.

Figure 20 displays the layout of the proposed OTA. The dimension of the OTA is 43.78 $\mathsf{\mu }$m × 31.62 $\mathsf{\mu }$m.

Table 2. Summarized pre-layout simulation results for the proposed OTA at various process corners.

Corner Parameter	TT	FF	SF	FS	SS
Gain (dB)	42.8	40.81	43.68	41.53	44.07
Phase Margin (°)	66.88	67.04	66.79	67.02	66.79
BW (kHz)	1.607	2.10	1.512	1.80	1.33
GBW (kHz)	141.48	146.20	144.70	138.09	137.16
THD (dB)	−71.23	−80.03	−73.47	−74.62	−74.21
INR (μ${\mathbf{V}}_{\mathbf{rms}}$)	4.53 $\mathsf{\mu }$	4.41 $\mathsf{\mu }$	4.61 $\mathsf{\mu }$	4.57 $\mathsf{\mu }$	4.49 $\mathsf{\mu }$
$PSRR$ (dB)	62.28	58.67	65.45	60.30	64.20
$CMRR$ (dB)	153.7	154.2	146.5	158.7	144.3

summarizes the results for the corner analysis of the proposed OTA. The approximated $GBW$ from hand calculations is ≈180 kHz, which is close to the simulated 141.48 kHz. The various performance parameters at different process corners varied less than $10\%$ except for the total harmonic distortion ($THD$) and $CMRR$.

The proposed OTA’s performance is compared with the state-of-the-art designs in

Table 3. Comparative analysis of the performance parameters of the proposed OTA with the state-of-the-art designs.

	This Work 1	2025 [54]	2024 [55]	2024 [56]	2024 [57]	2023 [58]	2023 [59]	2021 [60]	2019 [61]
Technology (nm)	45	28	180	45	180	180	180	180	180
Supply voltage (V)	0.9	1.2	0.4	±0.6	±0.25	±0.25	±0.5	±0.5	±0.75
Power (nW)	49.3	3400	29.15	980	60.15	31.3	104	267.5	855
Itotal (nA)	54.82	-	72.78	816	120.3	-	104	200	570
Gain (dB)	42.8	57	54.4	64.5	75	54.7	73.86	31.17	47.6
Bandwidth (Hz)	1.58 k	7.1 k	250	864	<10	6.18 k	-	212.4	-
THD (dB)	−71.23	-	-	−114.9	−32.82	−53.56	-	-	−43
IRN (μ${\mathbf{V}}_{\mathbf{rms}}$)	4.51	11.1	700@10 kHz	15.9	0.734@1 kHz	17.9	53.7	174	0.12 (PSD)
$CMRR$ (dB)	144.9	55	-	66.55	158.02	75	121.87	90.05	105.6
$PSRR$ (dB)	65.69	52	-	76.55	93.96	-	-	-	-
$NEF$	1.023	8.4	0.8@10 kHz	10.43	2.51	1.85	-	8.9	2.91
Dynamic range (dB)	52.5	-	-	52.71	-	55.5	-	66.98	66.5
Input impedance (GΩ)	0.908	105.5	-	5.1	-	74.7	-	-	0.25

¹ Post-layout simulation.

. The OTA exhibits excellent $NEF$ and $CMRR$ values with excellent power and noise performance among the contemporary designs at an advanced technology node. The OTA produces a respectable gain given its low power consumption and an input impedance of 895 M$\Omega$, which is enough for the intended use. A slew-rate (SR) of 0.049 V/$\mathsf{\mu }$s is found in the simulation by setting a 300 mV input square wave at 1 kHz frequency. There are better designs [51,52] in terms of SR. In [53], they designed for an SR of ≥100 mV/$\mathsf{\mu }$s and obtained 0.055 V/$\mathsf{\mu }$s for their proposed differential difference amplifier (DDA) to be used in bio-medical application. These findings demonstrate the OTAs’ suitability for usage in LNAs.

The NEF is computed by selecting 1.58 kHz as the BW and integrating noise across 0.5–208 Hz (application bandwidth) to compute $V_{ni,rms}$. Choosing $V_{ni,rms}$ between 0.5 and 1.58 kHz results in an NEF value of 2.51 $\mathsf{\mu }{V}_{rms}$.

3.2. Neural Amplifier

The component values are shown in

Table 4. Neural amplifier component values.

Component	Value
C1	6 pF
C2	8 nF
CL	1 pF

of the designed CC-CF NA. Due to the size of $C_2$, it will be externally inserted using a surface mount device (SMD) capacitor, ideally the model 0805, which occupies 6.72 mm² of space rather than being laid out on-chip. A large capacitor is selected to reduce the IRN of the NA.

Figure 21 reveals the output resistance variation of the BDPR for N = 2 and 3 when the bias voltage $V_{BIAS}$ for the pseudo-resistor is varied. For N = 3, the pseudo-resistor achieved 1 order more resistance than N = 2 BDPR.

Figure 22 shows the gain vs. frequency curves. The NA shows a post-layout mid-band gain of 42.89 dB. The lower −3 dB frequency is at 0.19 Hz and the higher −3 dB frequency is at 207.91 Hz, which are slightly lower than their pre-layout simulations and meet the desired range for LFPs.

Figure 23a illustrates how the cut-off frequencies change when the BDPR’s bulk voltage is adjusted using $V_{BIAS}$. When the $V_{BIAS}$ is adjusted between −0.35 V and 1 V, the lower cut-off, $F_L$, fluctuated between 0.23 and 3.2 Hz while the higher cut-off, $F_H$, exhibited changes between 208.9 and 296.8 Hz. The change in gain when the $I_{ref}$ of the OTA is modulated is seen in Figure 23b. The gain, $F_L$, and $F_H$ vary when $I_{ref}$ is varied between 1 nA and 100 nA. The range of the gain was 39 dB to 44.8 dB. The $F_H$ fluctuated between 32 Hz and 985.7 Hz, whereas the $F_L$ spanned between 0.05 Hz and 2.72 Hz. This illustrates the NA’s tweaking capability.

Figure 24 reveals the IRN of the NA. The integrated IRN root-mean-square (RMS) voltage from 0.5 Hz to 208 Hz frequency is 6.27 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$, which lies in the range of 4–7 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$. This range of IRN of NAs successfully measured brain signals through in vivo experiments.

Figure 25 shows two subfigures where one demonstrates a raw EEG signal (CBH-MIT EEG database) with added noise and the other signal is the filtered version of the previous one. The first figure is jittery, representing signal corruption with noises (60 Hz and 500 Hz). The filtered version is evidently very clean, which indicates the denoising effect of the designed NA.

Figure 26 is the frequency domain representation of the previous figure. Figure 26b demonstrates the suppression of 60 Hz power line interference through the $CMRR$ and reduction of noise at 500 Hz by LPF denoising.

Figure 27 presents the proposed layout for the single-channel NA, which consumes an area of 0.0155 mm². The layout includes a small load capacitor, $C_L$. A crude estimation of the total area per channel is 13.455 mm².

Table 5. Comparative analysis of the performance parameters of the neural amplifier.

	This Work 1	2024 [44]	2024 [62]	2024 [63]	2024 [64]	2024 [65]	2024 [66]	2022 [35]	2021 [67]
Technology (nm)	45	180	180	180	40	180	180	180	180
Supply voltage (V)	0.9	1.8	1	±0.5	1.1	1.8	0.4	1.8	1.8
Power (nW)	49.42	6840	2400	3770	922	4420	264.06	1700	3240
Itotal (nA)	54.914	3800	2400	3700	838	2450	660.15	944	1800
Gain (dB)	42.89	40	47	44.16	50	58.1	-	39.93	40
Bandwidth (Hz)	0.19–207.84	0.5–6.1 k	3–4 k	1–7.5 k	100–5.3 k	1.1–10 k	0–72.95	0.41–10.3 k	0.3–200
THD@1 m (dB)	−44.2	-	−42.1	−40	-	-	-	−41.7	−61 (5 mVpp)
IRN (μ${\mathbf{V}}_{\mathbf{rms}}$)	6.27	3.1	1.9	4.23	8	3.6	244	3.34	4.5
Area (mm2)	0.0155	0.082	0.243	0.004	0.00122	0.0785	0.00704	0.02	-

¹ Post-layout simulation.

summarizes the simulation outcomes and compares them with the contemporary notable works.

According to the comparison, the proposed design maintains an $IRN$ < 7 $\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{Hz}}$ inside the LFP band while providing the lowest power of all the works. For the application, the design provides a respectable $THD$ at 1 mV, which is more than adequate. The NA may be used for the battery-free system with this usable gain.

3.3. 10-Channel Neural Recording Amplifier

As the schematic design suggested in Figure 8, a single-ended connection is used for the 10-channel amplifier, whereas the second inputs of all the NAs are shorted to a common reference point. Figure 28 demonstrates the single-channel gain of the proposed 10-channel neural recording amplifier. The estimated power for the 10 channels is 494.2 nW, which is within the range of current power-harvesting circuits’ production (as mentioned in Section 1). And the estimated area is 134.55 mm².

4. Conclusions

In this work, a novel OTA architecture is proposed, which is tailored for ultra-low-power, battery-less biomedical applications. By employing self-cascode transistors and a fully differential design, the proposed OTA achieves an excellent balance of low power consumption, low noise, and a high $CMRR$. The simulation results, obtained using a 45 nm process, demonstrate the effectiveness of our design with a power consumption of just 49.3 nW and an impressive $CMRR$ of 144.9 dB.

The successful integration of this OTA into a 10-channel neural recording amplifier further validates its suitability for practical biomedical systems. The use of a bulk-driven pseudo-resistor (BDPR) also contributes to the system’s high performance and tunability. The recoding system consumes only 494.2 nW of power. The comparison with existing state-of-the-art designs confirms the competitive performance of our proposed solution.

However, the lack of a fabricated chip makes empirical validation impossible. The measurement findings may differ from the post-layout simulations, which is a shortcoming of this work. The neural amplifier performance on actual test individuals is therefore unattainable. Furthermore, it is not possible to determine how long-term usage will affect the circuit’s component aging. Moreover, the output voltage swing is limited by the tiny supply voltage when MOSFETs are stacked. Additionally, additional linearization techniques might have enhanced the circuit’s linearity further. Future work could focus on the physical fabrication and experimental characterization of the proposed OTA (specially $NEF$, $CMRR$, $PSRR$, and $GBW$ parameters, etc.), neural amplifier, buffer, multiplexer and ADC to validate the simulation results. Again, the study of EMI immunity and temperature-dependent noise are crucial for biomedical applications, which can form the basis for future study. Further investigation into the integration of this system with an on-chip energy-harvesting solution with RF transmission would also be a valuable next step toward realizing a fully autonomous, battery-less biomedical implant. Furthermore, the comparatively advance technologies like FinFET and FD-SOI could be investigated as well.